xref: /openbmc/linux/arch/arm64/Kconfig (revision f5ad1c74)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_CCA_REQUIRED if ACPI
5	select ACPI_GENERIC_GSI if ACPI
6	select ACPI_GTDT if ACPI
7	select ACPI_IORT if ACPI
8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9	select ACPI_MCFG if (ACPI && PCI)
10	select ACPI_SPCR_TABLE if ACPI
11	select ACPI_PPTT if ACPI
12	select ARCH_HAS_DEBUG_WX
13	select ARCH_BINFMT_ELF_STATE
14	select ARCH_HAS_DEBUG_VIRTUAL
15	select ARCH_HAS_DEBUG_VM_PGTABLE
16	select ARCH_HAS_DEVMEM_IS_ALLOWED
17	select ARCH_HAS_DMA_PREP_COHERENT
18	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19	select ARCH_HAS_FAST_MULTIPLIER
20	select ARCH_HAS_FORTIFY_SOURCE
21	select ARCH_HAS_GCOV_PROFILE_ALL
22	select ARCH_HAS_GIGANTIC_PAGE
23	select ARCH_HAS_KCOV
24	select ARCH_HAS_KEEPINITRD
25	select ARCH_HAS_MEMBARRIER_SYNC_CORE
26	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27	select ARCH_HAS_PTE_DEVMAP
28	select ARCH_HAS_PTE_SPECIAL
29	select ARCH_HAS_SETUP_DMA_OPS
30	select ARCH_HAS_SET_DIRECT_MAP
31	select ARCH_HAS_SET_MEMORY
32	select ARCH_STACKWALK
33	select ARCH_HAS_STRICT_KERNEL_RWX
34	select ARCH_HAS_STRICT_MODULE_RWX
35	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36	select ARCH_HAS_SYNC_DMA_FOR_CPU
37	select ARCH_HAS_SYSCALL_WRAPPER
38	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40	select ARCH_HAVE_ELF_PROT
41	select ARCH_HAVE_NMI_SAFE_CMPXCHG
42	select ARCH_INLINE_READ_LOCK if !PREEMPTION
43	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68	select ARCH_KEEP_MEMBLOCK
69	select ARCH_USE_CMPXCHG_LOCKREF
70	select ARCH_USE_GNU_PROPERTY
71	select ARCH_USE_QUEUED_RWLOCKS
72	select ARCH_USE_QUEUED_SPINLOCKS
73	select ARCH_USE_SYM_ANNOTATIONS
74	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
75	select ARCH_SUPPORTS_MEMORY_FAILURE
76	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
77	select ARCH_SUPPORTS_ATOMIC_RMW
78	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
79	select ARCH_SUPPORTS_NUMA_BALANCING
80	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
81	select ARCH_WANT_DEFAULT_BPF_JIT
82	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
83	select ARCH_WANT_FRAME_POINTERS
84	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
85	select ARCH_WANT_LD_ORPHAN_WARN
86	select ARCH_HAS_UBSAN_SANITIZE_ALL
87	select ARM_AMBA
88	select ARM_ARCH_TIMER
89	select ARM_GIC
90	select AUDIT_ARCH_COMPAT_GENERIC
91	select ARM_GIC_V2M if PCI
92	select ARM_GIC_V3
93	select ARM_GIC_V3_ITS if PCI
94	select ARM_PSCI_FW
95	select BUILDTIME_TABLE_SORT
96	select CLONE_BACKWARDS
97	select COMMON_CLK
98	select CPU_PM if (SUSPEND || CPU_IDLE)
99	select CRC32
100	select DCACHE_WORD_ACCESS
101	select DMA_DIRECT_REMAP
102	select EDAC_SUPPORT
103	select FRAME_POINTER
104	select GENERIC_ALLOCATOR
105	select GENERIC_ARCH_TOPOLOGY
106	select GENERIC_CLOCKEVENTS
107	select GENERIC_CLOCKEVENTS_BROADCAST
108	select GENERIC_CPU_AUTOPROBE
109	select GENERIC_CPU_VULNERABILITIES
110	select GENERIC_EARLY_IOREMAP
111	select GENERIC_IDLE_POLL_SETUP
112	select GENERIC_IRQ_IPI
113	select GENERIC_IRQ_MULTI_HANDLER
114	select GENERIC_IRQ_PROBE
115	select GENERIC_IRQ_SHOW
116	select GENERIC_IRQ_SHOW_LEVEL
117	select GENERIC_PCI_IOMAP
118	select GENERIC_PTDUMP
119	select GENERIC_SCHED_CLOCK
120	select GENERIC_SMP_IDLE_THREAD
121	select GENERIC_STRNCPY_FROM_USER
122	select GENERIC_STRNLEN_USER
123	select GENERIC_TIME_VSYSCALL
124	select GENERIC_GETTIMEOFDAY
125	select GENERIC_VDSO_TIME_NS
126	select HANDLE_DOMAIN_IRQ
127	select HARDIRQS_SW_RESEND
128	select HAVE_MOVE_PMD
129	select HAVE_MOVE_PUD
130	select HAVE_PCI
131	select HAVE_ACPI_APEI if (ACPI && EFI)
132	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
133	select HAVE_ARCH_AUDITSYSCALL
134	select HAVE_ARCH_BITREVERSE
135	select HAVE_ARCH_COMPILER_H
136	select HAVE_ARCH_HUGE_VMAP
137	select HAVE_ARCH_JUMP_LABEL
138	select HAVE_ARCH_JUMP_LABEL_RELATIVE
139	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
140	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
141	select HAVE_ARCH_KGDB
142	select HAVE_ARCH_MMAP_RND_BITS
143	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
144	select HAVE_ARCH_PFN_VALID
145	select HAVE_ARCH_PREL32_RELOCATIONS
146	select HAVE_ARCH_SECCOMP_FILTER
147	select HAVE_ARCH_STACKLEAK
148	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
149	select HAVE_ARCH_TRACEHOOK
150	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
151	select HAVE_ARCH_VMAP_STACK
152	select HAVE_ARM_SMCCC
153	select HAVE_ASM_MODVERSIONS
154	select HAVE_EBPF_JIT
155	select HAVE_C_RECORDMCOUNT
156	select HAVE_CMPXCHG_DOUBLE
157	select HAVE_CMPXCHG_LOCAL
158	select HAVE_CONTEXT_TRACKING
159	select HAVE_DEBUG_BUGVERBOSE
160	select HAVE_DEBUG_KMEMLEAK
161	select HAVE_DMA_CONTIGUOUS
162	select HAVE_DYNAMIC_FTRACE
163	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
164		if $(cc-option,-fpatchable-function-entry=2)
165	select HAVE_EFFICIENT_UNALIGNED_ACCESS
166	select HAVE_FAST_GUP
167	select HAVE_FTRACE_MCOUNT_RECORD
168	select HAVE_FUNCTION_TRACER
169	select HAVE_FUNCTION_ERROR_INJECTION
170	select HAVE_FUNCTION_GRAPH_TRACER
171	select HAVE_GCC_PLUGINS
172	select HAVE_HW_BREAKPOINT if PERF_EVENTS
173	select HAVE_IRQ_TIME_ACCOUNTING
174	select HAVE_NMI
175	select HAVE_PATA_PLATFORM
176	select HAVE_PERF_EVENTS
177	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
178	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
179	select HAVE_PERF_REGS
180	select HAVE_PERF_USER_STACK_DUMP
181	select HAVE_REGS_AND_STACK_ACCESS_API
182	select HAVE_FUNCTION_ARG_ACCESS_API
183	select HAVE_FUTEX_CMPXCHG if FUTEX
184	select MMU_GATHER_RCU_TABLE_FREE
185	select HAVE_RSEQ
186	select HAVE_STACKPROTECTOR
187	select HAVE_SYSCALL_TRACEPOINTS
188	select HAVE_KPROBES
189	select HAVE_KRETPROBES
190	select HAVE_GENERIC_VDSO
191	select IOMMU_DMA if IOMMU_SUPPORT
192	select IRQ_DOMAIN
193	select IRQ_FORCED_THREADING
194	select MODULES_USE_ELF_RELA
195	select NEED_DMA_MAP_STATE
196	select NEED_SG_DMA_LENGTH
197	select OF
198	select OF_EARLY_FLATTREE
199	select PCI_DOMAINS_GENERIC if PCI
200	select PCI_ECAM if (ACPI && PCI)
201	select PCI_SYSCALL if PCI
202	select POWER_RESET
203	select POWER_SUPPLY
204	select SPARSE_IRQ
205	select SWIOTLB
206	select SYSCTL_EXCEPTION_TRACE
207	select THREAD_INFO_IN_TASK
208	help
209	  ARM 64-bit (AArch64) Linux support.
210
211config 64BIT
212	def_bool y
213
214config MMU
215	def_bool y
216
217config ARM64_PAGE_SHIFT
218	int
219	default 16 if ARM64_64K_PAGES
220	default 14 if ARM64_16K_PAGES
221	default 12
222
223config ARM64_CONT_PTE_SHIFT
224	int
225	default 5 if ARM64_64K_PAGES
226	default 7 if ARM64_16K_PAGES
227	default 4
228
229config ARM64_CONT_PMD_SHIFT
230	int
231	default 5 if ARM64_64K_PAGES
232	default 5 if ARM64_16K_PAGES
233	default 4
234
235config ARCH_MMAP_RND_BITS_MIN
236       default 14 if ARM64_64K_PAGES
237       default 16 if ARM64_16K_PAGES
238       default 18
239
240# max bits determined by the following formula:
241#  VA_BITS - PAGE_SHIFT - 3
242config ARCH_MMAP_RND_BITS_MAX
243       default 19 if ARM64_VA_BITS=36
244       default 24 if ARM64_VA_BITS=39
245       default 27 if ARM64_VA_BITS=42
246       default 30 if ARM64_VA_BITS=47
247       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
248       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
249       default 33 if ARM64_VA_BITS=48
250       default 14 if ARM64_64K_PAGES
251       default 16 if ARM64_16K_PAGES
252       default 18
253
254config ARCH_MMAP_RND_COMPAT_BITS_MIN
255       default 7 if ARM64_64K_PAGES
256       default 9 if ARM64_16K_PAGES
257       default 11
258
259config ARCH_MMAP_RND_COMPAT_BITS_MAX
260       default 16
261
262config NO_IOPORT_MAP
263	def_bool y if !PCI
264
265config STACKTRACE_SUPPORT
266	def_bool y
267
268config ILLEGAL_POINTER_VALUE
269	hex
270	default 0xdead000000000000
271
272config LOCKDEP_SUPPORT
273	def_bool y
274
275config TRACE_IRQFLAGS_SUPPORT
276	def_bool y
277
278config GENERIC_BUG
279	def_bool y
280	depends on BUG
281
282config GENERIC_BUG_RELATIVE_POINTERS
283	def_bool y
284	depends on GENERIC_BUG
285
286config GENERIC_HWEIGHT
287	def_bool y
288
289config GENERIC_CSUM
290        def_bool y
291
292config GENERIC_CALIBRATE_DELAY
293	def_bool y
294
295config ZONE_DMA
296	bool "Support DMA zone" if EXPERT
297	default y
298
299config ZONE_DMA32
300	bool "Support DMA32 zone" if EXPERT
301	default y
302
303config ARCH_ENABLE_MEMORY_HOTPLUG
304	def_bool y
305
306config ARCH_ENABLE_MEMORY_HOTREMOVE
307	def_bool y
308
309config SMP
310	def_bool y
311
312config KERNEL_MODE_NEON
313	def_bool y
314
315config FIX_EARLYCON_MEM
316	def_bool y
317
318config PGTABLE_LEVELS
319	int
320	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
321	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
322	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
323	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
324	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
325	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
326
327config ARCH_SUPPORTS_UPROBES
328	def_bool y
329
330config ARCH_PROC_KCORE_TEXT
331	def_bool y
332
333config BROKEN_GAS_INST
334	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
335
336config KASAN_SHADOW_OFFSET
337	hex
338	depends on KASAN
339	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
340	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
341	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
342	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
343	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
344	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
345	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
346	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
347	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
348	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
349	default 0xffffffffffffffff
350
351source "arch/arm64/Kconfig.platforms"
352
353menu "Kernel Features"
354
355menu "ARM errata workarounds via the alternatives framework"
356
357config ARM64_WORKAROUND_CLEAN_CACHE
358	bool
359
360config ARM64_ERRATUM_826319
361	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
362	default y
363	select ARM64_WORKAROUND_CLEAN_CACHE
364	help
365	  This option adds an alternative code sequence to work around ARM
366	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
367	  AXI master interface and an L2 cache.
368
369	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
370	  and is unable to accept a certain write via this interface, it will
371	  not progress on read data presented on the read data channel and the
372	  system can deadlock.
373
374	  The workaround promotes data cache clean instructions to
375	  data cache clean-and-invalidate.
376	  Please note that this does not necessarily enable the workaround,
377	  as it depends on the alternative framework, which will only patch
378	  the kernel if an affected CPU is detected.
379
380	  If unsure, say Y.
381
382config ARM64_ERRATUM_827319
383	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
384	default y
385	select ARM64_WORKAROUND_CLEAN_CACHE
386	help
387	  This option adds an alternative code sequence to work around ARM
388	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
389	  master interface and an L2 cache.
390
391	  Under certain conditions this erratum can cause a clean line eviction
392	  to occur at the same time as another transaction to the same address
393	  on the AMBA 5 CHI interface, which can cause data corruption if the
394	  interconnect reorders the two transactions.
395
396	  The workaround promotes data cache clean instructions to
397	  data cache clean-and-invalidate.
398	  Please note that this does not necessarily enable the workaround,
399	  as it depends on the alternative framework, which will only patch
400	  the kernel if an affected CPU is detected.
401
402	  If unsure, say Y.
403
404config ARM64_ERRATUM_824069
405	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
406	default y
407	select ARM64_WORKAROUND_CLEAN_CACHE
408	help
409	  This option adds an alternative code sequence to work around ARM
410	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
411	  to a coherent interconnect.
412
413	  If a Cortex-A53 processor is executing a store or prefetch for
414	  write instruction at the same time as a processor in another
415	  cluster is executing a cache maintenance operation to the same
416	  address, then this erratum might cause a clean cache line to be
417	  incorrectly marked as dirty.
418
419	  The workaround promotes data cache clean instructions to
420	  data cache clean-and-invalidate.
421	  Please note that this option does not necessarily enable the
422	  workaround, as it depends on the alternative framework, which will
423	  only patch the kernel if an affected CPU is detected.
424
425	  If unsure, say Y.
426
427config ARM64_ERRATUM_819472
428	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
429	default y
430	select ARM64_WORKAROUND_CLEAN_CACHE
431	help
432	  This option adds an alternative code sequence to work around ARM
433	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
434	  present when it is connected to a coherent interconnect.
435
436	  If the processor is executing a load and store exclusive sequence at
437	  the same time as a processor in another cluster is executing a cache
438	  maintenance operation to the same address, then this erratum might
439	  cause data corruption.
440
441	  The workaround promotes data cache clean instructions to
442	  data cache clean-and-invalidate.
443	  Please note that this does not necessarily enable the workaround,
444	  as it depends on the alternative framework, which will only patch
445	  the kernel if an affected CPU is detected.
446
447	  If unsure, say Y.
448
449config ARM64_ERRATUM_832075
450	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
451	default y
452	help
453	  This option adds an alternative code sequence to work around ARM
454	  erratum 832075 on Cortex-A57 parts up to r1p2.
455
456	  Affected Cortex-A57 parts might deadlock when exclusive load/store
457	  instructions to Write-Back memory are mixed with Device loads.
458
459	  The workaround is to promote device loads to use Load-Acquire
460	  semantics.
461	  Please note that this does not necessarily enable the workaround,
462	  as it depends on the alternative framework, which will only patch
463	  the kernel if an affected CPU is detected.
464
465	  If unsure, say Y.
466
467config ARM64_ERRATUM_834220
468	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
469	depends on KVM
470	default y
471	help
472	  This option adds an alternative code sequence to work around ARM
473	  erratum 834220 on Cortex-A57 parts up to r1p2.
474
475	  Affected Cortex-A57 parts might report a Stage 2 translation
476	  fault as the result of a Stage 1 fault for load crossing a
477	  page boundary when there is a permission or device memory
478	  alignment fault at Stage 1 and a translation fault at Stage 2.
479
480	  The workaround is to verify that the Stage 1 translation
481	  doesn't generate a fault before handling the Stage 2 fault.
482	  Please note that this does not necessarily enable the workaround,
483	  as it depends on the alternative framework, which will only patch
484	  the kernel if an affected CPU is detected.
485
486	  If unsure, say Y.
487
488config ARM64_ERRATUM_845719
489	bool "Cortex-A53: 845719: a load might read incorrect data"
490	depends on COMPAT
491	default y
492	help
493	  This option adds an alternative code sequence to work around ARM
494	  erratum 845719 on Cortex-A53 parts up to r0p4.
495
496	  When running a compat (AArch32) userspace on an affected Cortex-A53
497	  part, a load at EL0 from a virtual address that matches the bottom 32
498	  bits of the virtual address used by a recent load at (AArch64) EL1
499	  might return incorrect data.
500
501	  The workaround is to write the contextidr_el1 register on exception
502	  return to a 32-bit task.
503	  Please note that this does not necessarily enable the workaround,
504	  as it depends on the alternative framework, which will only patch
505	  the kernel if an affected CPU is detected.
506
507	  If unsure, say Y.
508
509config ARM64_ERRATUM_843419
510	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
511	default y
512	select ARM64_MODULE_PLTS if MODULES
513	help
514	  This option links the kernel with '--fix-cortex-a53-843419' and
515	  enables PLT support to replace certain ADRP instructions, which can
516	  cause subsequent memory accesses to use an incorrect address on
517	  Cortex-A53 parts up to r0p4.
518
519	  If unsure, say Y.
520
521config ARM64_ERRATUM_1024718
522	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
523	default y
524	help
525	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
526
527	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
528	  update of the hardware dirty bit when the DBM/AP bits are updated
529	  without a break-before-make. The workaround is to disable the usage
530	  of hardware DBM locally on the affected cores. CPUs not affected by
531	  this erratum will continue to use the feature.
532
533	  If unsure, say Y.
534
535config ARM64_ERRATUM_1418040
536	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
537	default y
538	depends on COMPAT
539	help
540	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
541	  errata 1188873 and 1418040.
542
543	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
544	  cause register corruption when accessing the timer registers
545	  from AArch32 userspace.
546
547	  If unsure, say Y.
548
549config ARM64_WORKAROUND_SPECULATIVE_AT
550	bool
551
552config ARM64_ERRATUM_1165522
553	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
554	default y
555	select ARM64_WORKAROUND_SPECULATIVE_AT
556	help
557	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
558
559	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
560	  corrupted TLBs by speculating an AT instruction during a guest
561	  context switch.
562
563	  If unsure, say Y.
564
565config ARM64_ERRATUM_1319367
566	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
567	default y
568	select ARM64_WORKAROUND_SPECULATIVE_AT
569	help
570	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
571	  and A72 erratum 1319367
572
573	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
574	  speculating an AT instruction during a guest context switch.
575
576	  If unsure, say Y.
577
578config ARM64_ERRATUM_1530923
579	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
580	default y
581	select ARM64_WORKAROUND_SPECULATIVE_AT
582	help
583	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
584
585	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
586	  corrupted TLBs by speculating an AT instruction during a guest
587	  context switch.
588
589	  If unsure, say Y.
590
591config ARM64_WORKAROUND_REPEAT_TLBI
592	bool
593
594config ARM64_ERRATUM_1286807
595	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
596	default y
597	select ARM64_WORKAROUND_REPEAT_TLBI
598	help
599	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
600
601	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
602	  address for a cacheable mapping of a location is being
603	  accessed by a core while another core is remapping the virtual
604	  address to a new physical page using the recommended
605	  break-before-make sequence, then under very rare circumstances
606	  TLBI+DSB completes before a read using the translation being
607	  invalidated has been observed by other observers. The
608	  workaround repeats the TLBI+DSB operation.
609
610config ARM64_ERRATUM_1463225
611	bool "Cortex-A76: Software Step might prevent interrupt recognition"
612	default y
613	help
614	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
615
616	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
617	  of a system call instruction (SVC) can prevent recognition of
618	  subsequent interrupts when software stepping is disabled in the
619	  exception handler of the system call and either kernel debugging
620	  is enabled or VHE is in use.
621
622	  Work around the erratum by triggering a dummy step exception
623	  when handling a system call from a task that is being stepped
624	  in a VHE configuration of the kernel.
625
626	  If unsure, say Y.
627
628config ARM64_ERRATUM_1542419
629	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
630	default y
631	help
632	  This option adds a workaround for ARM Neoverse-N1 erratum
633	  1542419.
634
635	  Affected Neoverse-N1 cores could execute a stale instruction when
636	  modified by another CPU. The workaround depends on a firmware
637	  counterpart.
638
639	  Workaround the issue by hiding the DIC feature from EL0. This
640	  forces user-space to perform cache maintenance.
641
642	  If unsure, say Y.
643
644config ARM64_ERRATUM_1508412
645	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
646	default y
647	help
648	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
649
650	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
651	  of a store-exclusive or read of PAR_EL1 and a load with device or
652	  non-cacheable memory attributes. The workaround depends on a firmware
653	  counterpart.
654
655	  KVM guests must also have the workaround implemented or they can
656	  deadlock the system.
657
658	  Work around the issue by inserting DMB SY barriers around PAR_EL1
659	  register reads and warning KVM users. The DMB barrier is sufficient
660	  to prevent a speculative PAR_EL1 read.
661
662	  If unsure, say Y.
663
664config CAVIUM_ERRATUM_22375
665	bool "Cavium erratum 22375, 24313"
666	default y
667	help
668	  Enable workaround for errata 22375 and 24313.
669
670	  This implements two gicv3-its errata workarounds for ThunderX. Both
671	  with a small impact affecting only ITS table allocation.
672
673	    erratum 22375: only alloc 8MB table size
674	    erratum 24313: ignore memory access type
675
676	  The fixes are in ITS initialization and basically ignore memory access
677	  type and table size provided by the TYPER and BASER registers.
678
679	  If unsure, say Y.
680
681config CAVIUM_ERRATUM_23144
682	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
683	depends on NUMA
684	default y
685	help
686	  ITS SYNC command hang for cross node io and collections/cpu mapping.
687
688	  If unsure, say Y.
689
690config CAVIUM_ERRATUM_23154
691	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
692	default y
693	help
694	  The gicv3 of ThunderX requires a modified version for
695	  reading the IAR status to ensure data synchronization
696	  (access to icc_iar1_el1 is not sync'ed before and after).
697
698	  If unsure, say Y.
699
700config CAVIUM_ERRATUM_27456
701	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
702	default y
703	help
704	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
705	  instructions may cause the icache to become corrupted if it
706	  contains data for a non-current ASID.  The fix is to
707	  invalidate the icache when changing the mm context.
708
709	  If unsure, say Y.
710
711config CAVIUM_ERRATUM_30115
712	bool "Cavium erratum 30115: Guest may disable interrupts in host"
713	default y
714	help
715	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
716	  1.2, and T83 Pass 1.0, KVM guest execution may disable
717	  interrupts in host. Trapping both GICv3 group-0 and group-1
718	  accesses sidesteps the issue.
719
720	  If unsure, say Y.
721
722config CAVIUM_TX2_ERRATUM_219
723	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
724	default y
725	help
726	  On Cavium ThunderX2, a load, store or prefetch instruction between a
727	  TTBR update and the corresponding context synchronizing operation can
728	  cause a spurious Data Abort to be delivered to any hardware thread in
729	  the CPU core.
730
731	  Work around the issue by avoiding the problematic code sequence and
732	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
733	  trap handler performs the corresponding register access, skips the
734	  instruction and ensures context synchronization by virtue of the
735	  exception return.
736
737	  If unsure, say Y.
738
739config FUJITSU_ERRATUM_010001
740	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
741	default y
742	help
743	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
744	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
745	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
746	  This fault occurs under a specific hardware condition when a
747	  load/store instruction performs an address translation using:
748	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
749	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
750	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
751	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
752
753	  The workaround is to ensure these bits are clear in TCR_ELx.
754	  The workaround only affects the Fujitsu-A64FX.
755
756	  If unsure, say Y.
757
758config HISILICON_ERRATUM_161600802
759	bool "Hip07 161600802: Erroneous redistributor VLPI base"
760	default y
761	help
762	  The HiSilicon Hip07 SoC uses the wrong redistributor base
763	  when issued ITS commands such as VMOVP and VMAPP, and requires
764	  a 128kB offset to be applied to the target address in this commands.
765
766	  If unsure, say Y.
767
768config QCOM_FALKOR_ERRATUM_1003
769	bool "Falkor E1003: Incorrect translation due to ASID change"
770	default y
771	help
772	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
773	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
774	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
775	  then only for entries in the walk cache, since the leaf translation
776	  is unchanged. Work around the erratum by invalidating the walk cache
777	  entries for the trampoline before entering the kernel proper.
778
779config QCOM_FALKOR_ERRATUM_1009
780	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
781	default y
782	select ARM64_WORKAROUND_REPEAT_TLBI
783	help
784	  On Falkor v1, the CPU may prematurely complete a DSB following a
785	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
786	  one more time to fix the issue.
787
788	  If unsure, say Y.
789
790config QCOM_QDF2400_ERRATUM_0065
791	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
792	default y
793	help
794	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
795	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
796	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
797
798	  If unsure, say Y.
799
800config QCOM_FALKOR_ERRATUM_E1041
801	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
802	default y
803	help
804	  Falkor CPU may speculatively fetch instructions from an improper
805	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
806	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
807
808	  If unsure, say Y.
809
810config SOCIONEXT_SYNQUACER_PREITS
811	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
812	default y
813	help
814	  Socionext Synquacer SoCs implement a separate h/w block to generate
815	  MSI doorbell writes with non-zero values for the device ID.
816
817	  If unsure, say Y.
818
819endmenu
820
821
822choice
823	prompt "Page size"
824	default ARM64_4K_PAGES
825	help
826	  Page size (translation granule) configuration.
827
828config ARM64_4K_PAGES
829	bool "4KB"
830	help
831	  This feature enables 4KB pages support.
832
833config ARM64_16K_PAGES
834	bool "16KB"
835	help
836	  The system will use 16KB pages support. AArch32 emulation
837	  requires applications compiled with 16K (or a multiple of 16K)
838	  aligned segments.
839
840config ARM64_64K_PAGES
841	bool "64KB"
842	help
843	  This feature enables 64KB pages support (4KB by default)
844	  allowing only two levels of page tables and faster TLB
845	  look-up. AArch32 emulation requires applications compiled
846	  with 64K aligned segments.
847
848endchoice
849
850choice
851	prompt "Virtual address space size"
852	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
853	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
854	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
855	help
856	  Allows choosing one of multiple possible virtual address
857	  space sizes. The level of translation table is determined by
858	  a combination of page size and virtual address space size.
859
860config ARM64_VA_BITS_36
861	bool "36-bit" if EXPERT
862	depends on ARM64_16K_PAGES
863
864config ARM64_VA_BITS_39
865	bool "39-bit"
866	depends on ARM64_4K_PAGES
867
868config ARM64_VA_BITS_42
869	bool "42-bit"
870	depends on ARM64_64K_PAGES
871
872config ARM64_VA_BITS_47
873	bool "47-bit"
874	depends on ARM64_16K_PAGES
875
876config ARM64_VA_BITS_48
877	bool "48-bit"
878
879config ARM64_VA_BITS_52
880	bool "52-bit"
881	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
882	help
883	  Enable 52-bit virtual addressing for userspace when explicitly
884	  requested via a hint to mmap(). The kernel will also use 52-bit
885	  virtual addresses for its own mappings (provided HW support for
886	  this feature is available, otherwise it reverts to 48-bit).
887
888	  NOTE: Enabling 52-bit virtual addressing in conjunction with
889	  ARMv8.3 Pointer Authentication will result in the PAC being
890	  reduced from 7 bits to 3 bits, which may have a significant
891	  impact on its susceptibility to brute-force attacks.
892
893	  If unsure, select 48-bit virtual addressing instead.
894
895endchoice
896
897config ARM64_FORCE_52BIT
898	bool "Force 52-bit virtual addresses for userspace"
899	depends on ARM64_VA_BITS_52 && EXPERT
900	help
901	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
902	  to maintain compatibility with older software by providing 48-bit VAs
903	  unless a hint is supplied to mmap.
904
905	  This configuration option disables the 48-bit compatibility logic, and
906	  forces all userspace addresses to be 52-bit on HW that supports it. One
907	  should only enable this configuration option for stress testing userspace
908	  memory management code. If unsure say N here.
909
910config ARM64_VA_BITS
911	int
912	default 36 if ARM64_VA_BITS_36
913	default 39 if ARM64_VA_BITS_39
914	default 42 if ARM64_VA_BITS_42
915	default 47 if ARM64_VA_BITS_47
916	default 48 if ARM64_VA_BITS_48
917	default 52 if ARM64_VA_BITS_52
918
919choice
920	prompt "Physical address space size"
921	default ARM64_PA_BITS_48
922	help
923	  Choose the maximum physical address range that the kernel will
924	  support.
925
926config ARM64_PA_BITS_48
927	bool "48-bit"
928
929config ARM64_PA_BITS_52
930	bool "52-bit (ARMv8.2)"
931	depends on ARM64_64K_PAGES
932	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
933	help
934	  Enable support for a 52-bit physical address space, introduced as
935	  part of the ARMv8.2-LPA extension.
936
937	  With this enabled, the kernel will also continue to work on CPUs that
938	  do not support ARMv8.2-LPA, but with some added memory overhead (and
939	  minor performance overhead).
940
941endchoice
942
943config ARM64_PA_BITS
944	int
945	default 48 if ARM64_PA_BITS_48
946	default 52 if ARM64_PA_BITS_52
947
948choice
949	prompt "Endianness"
950	default CPU_LITTLE_ENDIAN
951	help
952	  Select the endianness of data accesses performed by the CPU. Userspace
953	  applications will need to be compiled and linked for the endianness
954	  that is selected here.
955
956config CPU_BIG_ENDIAN
957       bool "Build big-endian kernel"
958       help
959	  Say Y if you plan on running a kernel with a big-endian userspace.
960
961config CPU_LITTLE_ENDIAN
962	bool "Build little-endian kernel"
963	help
964	  Say Y if you plan on running a kernel with a little-endian userspace.
965	  This is usually the case for distributions targeting arm64.
966
967endchoice
968
969config SCHED_MC
970	bool "Multi-core scheduler support"
971	help
972	  Multi-core scheduler support improves the CPU scheduler's decision
973	  making when dealing with multi-core CPU chips at a cost of slightly
974	  increased overhead in some places. If unsure say N here.
975
976config SCHED_SMT
977	bool "SMT scheduler support"
978	help
979	  Improves the CPU scheduler's decision making when dealing with
980	  MultiThreading at a cost of slightly increased overhead in some
981	  places. If unsure say N here.
982
983config NR_CPUS
984	int "Maximum number of CPUs (2-4096)"
985	range 2 4096
986	default "256"
987
988config HOTPLUG_CPU
989	bool "Support for hot-pluggable CPUs"
990	select GENERIC_IRQ_MIGRATION
991	help
992	  Say Y here to experiment with turning CPUs off and on.  CPUs
993	  can be controlled through /sys/devices/system/cpu.
994
995# Common NUMA Features
996config NUMA
997	bool "NUMA Memory Allocation and Scheduler Support"
998	select ACPI_NUMA if ACPI
999	select OF_NUMA
1000	help
1001	  Enable NUMA (Non-Uniform Memory Access) support.
1002
1003	  The kernel will try to allocate memory used by a CPU on the
1004	  local memory of the CPU and add some more
1005	  NUMA awareness to the kernel.
1006
1007config NODES_SHIFT
1008	int "Maximum NUMA Nodes (as a power of 2)"
1009	range 1 10
1010	default "4"
1011	depends on NEED_MULTIPLE_NODES
1012	help
1013	  Specify the maximum number of NUMA Nodes available on the target
1014	  system.  Increases memory reserved to accommodate various tables.
1015
1016config USE_PERCPU_NUMA_NODE_ID
1017	def_bool y
1018	depends on NUMA
1019
1020config HAVE_SETUP_PER_CPU_AREA
1021	def_bool y
1022	depends on NUMA
1023
1024config NEED_PER_CPU_EMBED_FIRST_CHUNK
1025	def_bool y
1026	depends on NUMA
1027
1028config HOLES_IN_ZONE
1029	def_bool y
1030
1031source "kernel/Kconfig.hz"
1032
1033config ARCH_SPARSEMEM_ENABLE
1034	def_bool y
1035	select SPARSEMEM_VMEMMAP_ENABLE
1036
1037config ARCH_SPARSEMEM_DEFAULT
1038	def_bool ARCH_SPARSEMEM_ENABLE
1039
1040config ARCH_SELECT_MEMORY_MODEL
1041	def_bool ARCH_SPARSEMEM_ENABLE
1042
1043config ARCH_FLATMEM_ENABLE
1044	def_bool !NUMA
1045
1046config HW_PERF_EVENTS
1047	def_bool y
1048	depends on ARM_PMU
1049
1050config SYS_SUPPORTS_HUGETLBFS
1051	def_bool y
1052
1053config ARCH_WANT_HUGE_PMD_SHARE
1054
1055config ARCH_HAS_CACHE_LINE_SIZE
1056	def_bool y
1057
1058config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1059	def_bool y if PGTABLE_LEVELS > 2
1060
1061# Supported by clang >= 7.0
1062config CC_HAVE_SHADOW_CALL_STACK
1063	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1064
1065config PARAVIRT
1066	bool "Enable paravirtualization code"
1067	help
1068	  This changes the kernel so it can modify itself when it is run
1069	  under a hypervisor, potentially improving performance significantly
1070	  over full virtualization.
1071
1072config PARAVIRT_TIME_ACCOUNTING
1073	bool "Paravirtual steal time accounting"
1074	select PARAVIRT
1075	help
1076	  Select this option to enable fine granularity task steal time
1077	  accounting. Time spent executing other tasks in parallel with
1078	  the current vCPU is discounted from the vCPU power. To account for
1079	  that, there can be a small performance impact.
1080
1081	  If in doubt, say N here.
1082
1083config KEXEC
1084	depends on PM_SLEEP_SMP
1085	select KEXEC_CORE
1086	bool "kexec system call"
1087	help
1088	  kexec is a system call that implements the ability to shutdown your
1089	  current kernel, and to start another kernel.  It is like a reboot
1090	  but it is independent of the system firmware.   And like a reboot
1091	  you can start any kernel with it, not just Linux.
1092
1093config KEXEC_FILE
1094	bool "kexec file based system call"
1095	select KEXEC_CORE
1096	help
1097	  This is new version of kexec system call. This system call is
1098	  file based and takes file descriptors as system call argument
1099	  for kernel and initramfs as opposed to list of segments as
1100	  accepted by previous system call.
1101
1102config KEXEC_SIG
1103	bool "Verify kernel signature during kexec_file_load() syscall"
1104	depends on KEXEC_FILE
1105	help
1106	  Select this option to verify a signature with loaded kernel
1107	  image. If configured, any attempt of loading a image without
1108	  valid signature will fail.
1109
1110	  In addition to that option, you need to enable signature
1111	  verification for the corresponding kernel image type being
1112	  loaded in order for this to work.
1113
1114config KEXEC_IMAGE_VERIFY_SIG
1115	bool "Enable Image signature verification support"
1116	default y
1117	depends on KEXEC_SIG
1118	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1119	help
1120	  Enable Image signature verification support.
1121
1122comment "Support for PE file signature verification disabled"
1123	depends on KEXEC_SIG
1124	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1125
1126config CRASH_DUMP
1127	bool "Build kdump crash kernel"
1128	help
1129	  Generate crash dump after being started by kexec. This should
1130	  be normally only set in special crash dump kernels which are
1131	  loaded in the main kernel with kexec-tools into a specially
1132	  reserved region and then later executed after a crash by
1133	  kdump/kexec.
1134
1135	  For more details see Documentation/admin-guide/kdump/kdump.rst
1136
1137config XEN_DOM0
1138	def_bool y
1139	depends on XEN
1140
1141config XEN
1142	bool "Xen guest support on ARM64"
1143	depends on ARM64 && OF
1144	select SWIOTLB_XEN
1145	select PARAVIRT
1146	help
1147	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1148
1149config FORCE_MAX_ZONEORDER
1150	int
1151	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1152	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1153	default "11"
1154	help
1155	  The kernel memory allocator divides physically contiguous memory
1156	  blocks into "zones", where each zone is a power of two number of
1157	  pages.  This option selects the largest power of two that the kernel
1158	  keeps in the memory allocator.  If you need to allocate very large
1159	  blocks of physically contiguous memory, then you may need to
1160	  increase this value.
1161
1162	  This config option is actually maximum order plus one. For example,
1163	  a value of 11 means that the largest free memory block is 2^10 pages.
1164
1165	  We make sure that we can allocate upto a HugePage size for each configuration.
1166	  Hence we have :
1167		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1168
1169	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1170	  4M allocations matching the default size used by generic code.
1171
1172config UNMAP_KERNEL_AT_EL0
1173	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1174	default y
1175	help
1176	  Speculation attacks against some high-performance processors can
1177	  be used to bypass MMU permission checks and leak kernel data to
1178	  userspace. This can be defended against by unmapping the kernel
1179	  when running in userspace, mapping it back in on exception entry
1180	  via a trampoline page in the vector table.
1181
1182	  If unsure, say Y.
1183
1184config RODATA_FULL_DEFAULT_ENABLED
1185	bool "Apply r/o permissions of VM areas also to their linear aliases"
1186	default y
1187	help
1188	  Apply read-only attributes of VM areas to the linear alias of
1189	  the backing pages as well. This prevents code or read-only data
1190	  from being modified (inadvertently or intentionally) via another
1191	  mapping of the same memory page. This additional enhancement can
1192	  be turned off at runtime by passing rodata=[off|on] (and turned on
1193	  with rodata=full if this option is set to 'n')
1194
1195	  This requires the linear region to be mapped down to pages,
1196	  which may adversely affect performance in some cases.
1197
1198config ARM64_SW_TTBR0_PAN
1199	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1200	help
1201	  Enabling this option prevents the kernel from accessing
1202	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1203	  zeroed area and reserved ASID. The user access routines
1204	  restore the valid TTBR0_EL1 temporarily.
1205
1206config ARM64_TAGGED_ADDR_ABI
1207	bool "Enable the tagged user addresses syscall ABI"
1208	default y
1209	help
1210	  When this option is enabled, user applications can opt in to a
1211	  relaxed ABI via prctl() allowing tagged addresses to be passed
1212	  to system calls as pointer arguments. For details, see
1213	  Documentation/arm64/tagged-address-abi.rst.
1214
1215menuconfig COMPAT
1216	bool "Kernel support for 32-bit EL0"
1217	depends on ARM64_4K_PAGES || EXPERT
1218	select COMPAT_BINFMT_ELF if BINFMT_ELF
1219	select HAVE_UID16
1220	select OLD_SIGSUSPEND3
1221	select COMPAT_OLD_SIGACTION
1222	help
1223	  This option enables support for a 32-bit EL0 running under a 64-bit
1224	  kernel at EL1. AArch32-specific components such as system calls,
1225	  the user helper functions, VFP support and the ptrace interface are
1226	  handled appropriately by the kernel.
1227
1228	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1229	  that you will only be able to execute AArch32 binaries that were compiled
1230	  with page size aligned segments.
1231
1232	  If you want to execute 32-bit userspace applications, say Y.
1233
1234if COMPAT
1235
1236config KUSER_HELPERS
1237	bool "Enable kuser helpers page for 32-bit applications"
1238	default y
1239	help
1240	  Warning: disabling this option may break 32-bit user programs.
1241
1242	  Provide kuser helpers to compat tasks. The kernel provides
1243	  helper code to userspace in read only form at a fixed location
1244	  to allow userspace to be independent of the CPU type fitted to
1245	  the system. This permits binaries to be run on ARMv4 through
1246	  to ARMv8 without modification.
1247
1248	  See Documentation/arm/kernel_user_helpers.rst for details.
1249
1250	  However, the fixed address nature of these helpers can be used
1251	  by ROP (return orientated programming) authors when creating
1252	  exploits.
1253
1254	  If all of the binaries and libraries which run on your platform
1255	  are built specifically for your platform, and make no use of
1256	  these helpers, then you can turn this option off to hinder
1257	  such exploits. However, in that case, if a binary or library
1258	  relying on those helpers is run, it will not function correctly.
1259
1260	  Say N here only if you are absolutely certain that you do not
1261	  need these helpers; otherwise, the safe option is to say Y.
1262
1263config COMPAT_VDSO
1264	bool "Enable vDSO for 32-bit applications"
1265	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1266	select GENERIC_COMPAT_VDSO
1267	default y
1268	help
1269	  Place in the process address space of 32-bit applications an
1270	  ELF shared object providing fast implementations of gettimeofday
1271	  and clock_gettime.
1272
1273	  You must have a 32-bit build of glibc 2.22 or later for programs
1274	  to seamlessly take advantage of this.
1275
1276config THUMB2_COMPAT_VDSO
1277	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1278	depends on COMPAT_VDSO
1279	default y
1280	help
1281	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1282	  otherwise with '-marm'.
1283
1284menuconfig ARMV8_DEPRECATED
1285	bool "Emulate deprecated/obsolete ARMv8 instructions"
1286	depends on SYSCTL
1287	help
1288	  Legacy software support may require certain instructions
1289	  that have been deprecated or obsoleted in the architecture.
1290
1291	  Enable this config to enable selective emulation of these
1292	  features.
1293
1294	  If unsure, say Y
1295
1296if ARMV8_DEPRECATED
1297
1298config SWP_EMULATION
1299	bool "Emulate SWP/SWPB instructions"
1300	help
1301	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1302	  they are always undefined. Say Y here to enable software
1303	  emulation of these instructions for userspace using LDXR/STXR.
1304	  This feature can be controlled at runtime with the abi.swp
1305	  sysctl which is disabled by default.
1306
1307	  In some older versions of glibc [<=2.8] SWP is used during futex
1308	  trylock() operations with the assumption that the code will not
1309	  be preempted. This invalid assumption may be more likely to fail
1310	  with SWP emulation enabled, leading to deadlock of the user
1311	  application.
1312
1313	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1314	  on an external transaction monitoring block called a global
1315	  monitor to maintain update atomicity. If your system does not
1316	  implement a global monitor, this option can cause programs that
1317	  perform SWP operations to uncached memory to deadlock.
1318
1319	  If unsure, say Y
1320
1321config CP15_BARRIER_EMULATION
1322	bool "Emulate CP15 Barrier instructions"
1323	help
1324	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1325	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1326	  strongly recommended to use the ISB, DSB, and DMB
1327	  instructions instead.
1328
1329	  Say Y here to enable software emulation of these
1330	  instructions for AArch32 userspace code. When this option is
1331	  enabled, CP15 barrier usage is traced which can help
1332	  identify software that needs updating. This feature can be
1333	  controlled at runtime with the abi.cp15_barrier sysctl.
1334
1335	  If unsure, say Y
1336
1337config SETEND_EMULATION
1338	bool "Emulate SETEND instruction"
1339	help
1340	  The SETEND instruction alters the data-endianness of the
1341	  AArch32 EL0, and is deprecated in ARMv8.
1342
1343	  Say Y here to enable software emulation of the instruction
1344	  for AArch32 userspace code. This feature can be controlled
1345	  at runtime with the abi.setend sysctl.
1346
1347	  Note: All the cpus on the system must have mixed endian support at EL0
1348	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1349	  endian - is hotplugged in after this feature has been enabled, there could
1350	  be unexpected results in the applications.
1351
1352	  If unsure, say Y
1353endif
1354
1355endif
1356
1357menu "ARMv8.1 architectural features"
1358
1359config ARM64_HW_AFDBM
1360	bool "Support for hardware updates of the Access and Dirty page flags"
1361	default y
1362	help
1363	  The ARMv8.1 architecture extensions introduce support for
1364	  hardware updates of the access and dirty information in page
1365	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1366	  capable processors, accesses to pages with PTE_AF cleared will
1367	  set this bit instead of raising an access flag fault.
1368	  Similarly, writes to read-only pages with the DBM bit set will
1369	  clear the read-only bit (AP[2]) instead of raising a
1370	  permission fault.
1371
1372	  Kernels built with this configuration option enabled continue
1373	  to work on pre-ARMv8.1 hardware and the performance impact is
1374	  minimal. If unsure, say Y.
1375
1376config ARM64_PAN
1377	bool "Enable support for Privileged Access Never (PAN)"
1378	default y
1379	help
1380	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1381	 prevents the kernel or hypervisor from accessing user-space (EL0)
1382	 memory directly.
1383
1384	 Choosing this option will cause any unprotected (not using
1385	 copy_to_user et al) memory access to fail with a permission fault.
1386
1387	 The feature is detected at runtime, and will remain as a 'nop'
1388	 instruction if the cpu does not implement the feature.
1389
1390config AS_HAS_LDAPR
1391	def_bool $(as-instr,.arch_extension rcpc)
1392
1393config ARM64_LSE_ATOMICS
1394	bool
1395	default ARM64_USE_LSE_ATOMICS
1396	depends on $(as-instr,.arch_extension lse)
1397
1398config ARM64_USE_LSE_ATOMICS
1399	bool "Atomic instructions"
1400	depends on JUMP_LABEL
1401	default y
1402	help
1403	  As part of the Large System Extensions, ARMv8.1 introduces new
1404	  atomic instructions that are designed specifically to scale in
1405	  very large systems.
1406
1407	  Say Y here to make use of these instructions for the in-kernel
1408	  atomic routines. This incurs a small overhead on CPUs that do
1409	  not support these instructions and requires the kernel to be
1410	  built with binutils >= 2.25 in order for the new instructions
1411	  to be used.
1412
1413config ARM64_VHE
1414	bool "Enable support for Virtualization Host Extensions (VHE)"
1415	default y
1416	help
1417	  Virtualization Host Extensions (VHE) allow the kernel to run
1418	  directly at EL2 (instead of EL1) on processors that support
1419	  it. This leads to better performance for KVM, as they reduce
1420	  the cost of the world switch.
1421
1422	  Selecting this option allows the VHE feature to be detected
1423	  at runtime, and does not affect processors that do not
1424	  implement this feature.
1425
1426endmenu
1427
1428menu "ARMv8.2 architectural features"
1429
1430config ARM64_PMEM
1431	bool "Enable support for persistent memory"
1432	select ARCH_HAS_PMEM_API
1433	select ARCH_HAS_UACCESS_FLUSHCACHE
1434	help
1435	  Say Y to enable support for the persistent memory API based on the
1436	  ARMv8.2 DCPoP feature.
1437
1438	  The feature is detected at runtime, and the kernel will use DC CVAC
1439	  operations if DC CVAP is not supported (following the behaviour of
1440	  DC CVAP itself if the system does not define a point of persistence).
1441
1442config ARM64_RAS_EXTN
1443	bool "Enable support for RAS CPU Extensions"
1444	default y
1445	help
1446	  CPUs that support the Reliability, Availability and Serviceability
1447	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1448	  errors, classify them and report them to software.
1449
1450	  On CPUs with these extensions system software can use additional
1451	  barriers to determine if faults are pending and read the
1452	  classification from a new set of registers.
1453
1454	  Selecting this feature will allow the kernel to use these barriers
1455	  and access the new registers if the system supports the extension.
1456	  Platform RAS features may additionally depend on firmware support.
1457
1458config ARM64_CNP
1459	bool "Enable support for Common Not Private (CNP) translations"
1460	default y
1461	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1462	help
1463	  Common Not Private (CNP) allows translation table entries to
1464	  be shared between different PEs in the same inner shareable
1465	  domain, so the hardware can use this fact to optimise the
1466	  caching of such entries in the TLB.
1467
1468	  Selecting this option allows the CNP feature to be detected
1469	  at runtime, and does not affect PEs that do not implement
1470	  this feature.
1471
1472endmenu
1473
1474menu "ARMv8.3 architectural features"
1475
1476config ARM64_PTR_AUTH
1477	bool "Enable support for pointer authentication"
1478	default y
1479	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1480	# Modern compilers insert a .note.gnu.property section note for PAC
1481	# which is only understood by binutils starting with version 2.33.1.
1482	depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1483	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1484	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1485	help
1486	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1487	  instructions for signing and authenticating pointers against secret
1488	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1489	  and other attacks.
1490
1491	  This option enables these instructions at EL0 (i.e. for userspace).
1492	  Choosing this option will cause the kernel to initialise secret keys
1493	  for each process at exec() time, with these keys being
1494	  context-switched along with the process.
1495
1496	  If the compiler supports the -mbranch-protection or
1497	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1498	  will also cause the kernel itself to be compiled with return address
1499	  protection. In this case, and if the target hardware is known to
1500	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1501	  disabled with minimal loss of protection.
1502
1503	  The feature is detected at runtime. If the feature is not present in
1504	  hardware it will not be advertised to userspace/KVM guest nor will it
1505	  be enabled.
1506
1507	  If the feature is present on the boot CPU but not on a late CPU, then
1508	  the late CPU will be parked. Also, if the boot CPU does not have
1509	  address auth and the late CPU has then the late CPU will still boot
1510	  but with the feature disabled. On such a system, this option should
1511	  not be selected.
1512
1513	  This feature works with FUNCTION_GRAPH_TRACER option only if
1514	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1515
1516config CC_HAS_BRANCH_PROT_PAC_RET
1517	# GCC 9 or later, clang 8 or later
1518	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1519
1520config CC_HAS_SIGN_RETURN_ADDRESS
1521	# GCC 7, 8
1522	def_bool $(cc-option,-msign-return-address=all)
1523
1524config AS_HAS_PAC
1525	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1526
1527config AS_HAS_CFI_NEGATE_RA_STATE
1528	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1529
1530endmenu
1531
1532menu "ARMv8.4 architectural features"
1533
1534config ARM64_AMU_EXTN
1535	bool "Enable support for the Activity Monitors Unit CPU extension"
1536	default y
1537	help
1538	  The activity monitors extension is an optional extension introduced
1539	  by the ARMv8.4 CPU architecture. This enables support for version 1
1540	  of the activity monitors architecture, AMUv1.
1541
1542	  To enable the use of this extension on CPUs that implement it, say Y.
1543
1544	  Note that for architectural reasons, firmware _must_ implement AMU
1545	  support when running on CPUs that present the activity monitors
1546	  extension. The required support is present in:
1547	    * Version 1.5 and later of the ARM Trusted Firmware
1548
1549	  For kernels that have this configuration enabled but boot with broken
1550	  firmware, you may need to say N here until the firmware is fixed.
1551	  Otherwise you may experience firmware panics or lockups when
1552	  accessing the counter registers. Even if you are not observing these
1553	  symptoms, the values returned by the register reads might not
1554	  correctly reflect reality. Most commonly, the value read will be 0,
1555	  indicating that the counter is not enabled.
1556
1557config AS_HAS_ARMV8_4
1558	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1559
1560config ARM64_TLB_RANGE
1561	bool "Enable support for tlbi range feature"
1562	default y
1563	depends on AS_HAS_ARMV8_4
1564	help
1565	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1566	  range of input addresses.
1567
1568	  The feature introduces new assembly instructions, and they were
1569	  support when binutils >= 2.30.
1570
1571endmenu
1572
1573menu "ARMv8.5 architectural features"
1574
1575config ARM64_BTI
1576	bool "Branch Target Identification support"
1577	default y
1578	help
1579	  Branch Target Identification (part of the ARMv8.5 Extensions)
1580	  provides a mechanism to limit the set of locations to which computed
1581	  branch instructions such as BR or BLR can jump.
1582
1583	  To make use of BTI on CPUs that support it, say Y.
1584
1585	  BTI is intended to provide complementary protection to other control
1586	  flow integrity protection mechanisms, such as the Pointer
1587	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1588	  For this reason, it does not make sense to enable this option without
1589	  also enabling support for pointer authentication.  Thus, when
1590	  enabling this option you should also select ARM64_PTR_AUTH=y.
1591
1592	  Userspace binaries must also be specifically compiled to make use of
1593	  this mechanism.  If you say N here or the hardware does not support
1594	  BTI, such binaries can still run, but you get no additional
1595	  enforcement of branch destinations.
1596
1597config ARM64_BTI_KERNEL
1598	bool "Use Branch Target Identification for kernel"
1599	default y
1600	depends on ARM64_BTI
1601	depends on ARM64_PTR_AUTH
1602	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1603	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1604	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1605	depends on !(CC_IS_CLANG && GCOV_KERNEL)
1606	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1607	help
1608	  Build the kernel with Branch Target Identification annotations
1609	  and enable enforcement of this for kernel code. When this option
1610	  is enabled and the system supports BTI all kernel code including
1611	  modular code must have BTI enabled.
1612
1613config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1614	# GCC 9 or later, clang 8 or later
1615	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1616
1617config ARM64_E0PD
1618	bool "Enable support for E0PD"
1619	default y
1620	help
1621	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1622	  that EL0 accesses made via TTBR1 always fault in constant time,
1623	  providing similar benefits to KASLR as those provided by KPTI, but
1624	  with lower overhead and without disrupting legitimate access to
1625	  kernel memory such as SPE.
1626
1627	  This option enables E0PD for TTBR1 where available.
1628
1629config ARCH_RANDOM
1630	bool "Enable support for random number generation"
1631	default y
1632	help
1633	  Random number generation (part of the ARMv8.5 Extensions)
1634	  provides a high bandwidth, cryptographically secure
1635	  hardware random number generator.
1636
1637config ARM64_AS_HAS_MTE
1638	# Initial support for MTE went in binutils 2.32.0, checked with
1639	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1640	# as a late addition to the final architecture spec (LDGM/STGM)
1641	# is only supported in the newer 2.32.x and 2.33 binutils
1642	# versions, hence the extra "stgm" instruction check below.
1643	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1644
1645config ARM64_MTE
1646	bool "Memory Tagging Extension support"
1647	default y
1648	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1649	select ARCH_USES_HIGH_VMA_FLAGS
1650	help
1651	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1652	  architectural support for run-time, always-on detection of
1653	  various classes of memory error to aid with software debugging
1654	  to eliminate vulnerabilities arising from memory-unsafe
1655	  languages.
1656
1657	  This option enables the support for the Memory Tagging
1658	  Extension at EL0 (i.e. for userspace).
1659
1660	  Selecting this option allows the feature to be detected at
1661	  runtime. Any secondary CPU not implementing this feature will
1662	  not be allowed a late bring-up.
1663
1664	  Userspace binaries that want to use this feature must
1665	  explicitly opt in. The mechanism for the userspace is
1666	  described in:
1667
1668	  Documentation/arm64/memory-tagging-extension.rst.
1669
1670endmenu
1671
1672config ARM64_SVE
1673	bool "ARM Scalable Vector Extension support"
1674	default y
1675	depends on !KVM || ARM64_VHE
1676	help
1677	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1678	  execution state which complements and extends the SIMD functionality
1679	  of the base architecture to support much larger vectors and to enable
1680	  additional vectorisation opportunities.
1681
1682	  To enable use of this extension on CPUs that implement it, say Y.
1683
1684	  On CPUs that support the SVE2 extensions, this option will enable
1685	  those too.
1686
1687	  Note that for architectural reasons, firmware _must_ implement SVE
1688	  support when running on SVE capable hardware.  The required support
1689	  is present in:
1690
1691	    * version 1.5 and later of the ARM Trusted Firmware
1692	    * the AArch64 boot wrapper since commit 5e1261e08abf
1693	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1694
1695	  For other firmware implementations, consult the firmware documentation
1696	  or vendor.
1697
1698	  If you need the kernel to boot on SVE-capable hardware with broken
1699	  firmware, you may need to say N here until you get your firmware
1700	  fixed.  Otherwise, you may experience firmware panics or lockups when
1701	  booting the kernel.  If unsure and you are not observing these
1702	  symptoms, you should assume that it is safe to say Y.
1703
1704	  CPUs that support SVE are architecturally required to support the
1705	  Virtualization Host Extensions (VHE), so the kernel makes no
1706	  provision for supporting SVE alongside KVM without VHE enabled.
1707	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1708	  KVM in the same kernel image.
1709
1710config ARM64_MODULE_PLTS
1711	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1712	depends on MODULES
1713	select HAVE_MOD_ARCH_SPECIFIC
1714	help
1715	  Allocate PLTs when loading modules so that jumps and calls whose
1716	  targets are too far away for their relative offsets to be encoded
1717	  in the instructions themselves can be bounced via veneers in the
1718	  module's PLT. This allows modules to be allocated in the generic
1719	  vmalloc area after the dedicated module memory area has been
1720	  exhausted.
1721
1722	  When running with address space randomization (KASLR), the module
1723	  region itself may be too far away for ordinary relative jumps and
1724	  calls, and so in that case, module PLTs are required and cannot be
1725	  disabled.
1726
1727	  Specific errata workaround(s) might also force module PLTs to be
1728	  enabled (ARM64_ERRATUM_843419).
1729
1730config ARM64_PSEUDO_NMI
1731	bool "Support for NMI-like interrupts"
1732	select ARM_GIC_V3
1733	help
1734	  Adds support for mimicking Non-Maskable Interrupts through the use of
1735	  GIC interrupt priority. This support requires version 3 or later of
1736	  ARM GIC.
1737
1738	  This high priority configuration for interrupts needs to be
1739	  explicitly enabled by setting the kernel parameter
1740	  "irqchip.gicv3_pseudo_nmi" to 1.
1741
1742	  If unsure, say N
1743
1744if ARM64_PSEUDO_NMI
1745config ARM64_DEBUG_PRIORITY_MASKING
1746	bool "Debug interrupt priority masking"
1747	help
1748	  This adds runtime checks to functions enabling/disabling
1749	  interrupts when using priority masking. The additional checks verify
1750	  the validity of ICC_PMR_EL1 when calling concerned functions.
1751
1752	  If unsure, say N
1753endif
1754
1755config RELOCATABLE
1756	bool "Build a relocatable kernel image" if EXPERT
1757	select ARCH_HAS_RELR
1758	default y
1759	help
1760	  This builds the kernel as a Position Independent Executable (PIE),
1761	  which retains all relocation metadata required to relocate the
1762	  kernel binary at runtime to a different virtual address than the
1763	  address it was linked at.
1764	  Since AArch64 uses the RELA relocation format, this requires a
1765	  relocation pass at runtime even if the kernel is loaded at the
1766	  same address it was linked at.
1767
1768config RANDOMIZE_BASE
1769	bool "Randomize the address of the kernel image"
1770	select ARM64_MODULE_PLTS if MODULES
1771	select RELOCATABLE
1772	help
1773	  Randomizes the virtual address at which the kernel image is
1774	  loaded, as a security feature that deters exploit attempts
1775	  relying on knowledge of the location of kernel internals.
1776
1777	  It is the bootloader's job to provide entropy, by passing a
1778	  random u64 value in /chosen/kaslr-seed at kernel entry.
1779
1780	  When booting via the UEFI stub, it will invoke the firmware's
1781	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1782	  to the kernel proper. In addition, it will randomise the physical
1783	  location of the kernel Image as well.
1784
1785	  If unsure, say N.
1786
1787config RANDOMIZE_MODULE_REGION_FULL
1788	bool "Randomize the module region over a 4 GB range"
1789	depends on RANDOMIZE_BASE
1790	default y
1791	help
1792	  Randomizes the location of the module region inside a 4 GB window
1793	  covering the core kernel. This way, it is less likely for modules
1794	  to leak information about the location of core kernel data structures
1795	  but it does imply that function calls between modules and the core
1796	  kernel will need to be resolved via veneers in the module PLT.
1797
1798	  When this option is not set, the module region will be randomized over
1799	  a limited range that contains the [_stext, _etext] interval of the
1800	  core kernel, so branch relocations are always in range.
1801
1802config CC_HAVE_STACKPROTECTOR_SYSREG
1803	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1804
1805config STACKPROTECTOR_PER_TASK
1806	def_bool y
1807	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1808
1809endmenu
1810
1811menu "Boot options"
1812
1813config ARM64_ACPI_PARKING_PROTOCOL
1814	bool "Enable support for the ARM64 ACPI parking protocol"
1815	depends on ACPI
1816	help
1817	  Enable support for the ARM64 ACPI parking protocol. If disabled
1818	  the kernel will not allow booting through the ARM64 ACPI parking
1819	  protocol even if the corresponding data is present in the ACPI
1820	  MADT table.
1821
1822config CMDLINE
1823	string "Default kernel command string"
1824	default ""
1825	help
1826	  Provide a set of default command-line options at build time by
1827	  entering them here. As a minimum, you should specify the the
1828	  root device (e.g. root=/dev/nfs).
1829
1830choice
1831	prompt "Kernel command line type" if CMDLINE != ""
1832	default CMDLINE_FROM_BOOTLOADER
1833	help
1834	  Choose how the kernel will handle the provided default kernel
1835	  command line string.
1836
1837config CMDLINE_FROM_BOOTLOADER
1838	bool "Use bootloader kernel arguments if available"
1839	help
1840	  Uses the command-line options passed by the boot loader. If
1841	  the boot loader doesn't provide any, the default kernel command
1842	  string provided in CMDLINE will be used.
1843
1844config CMDLINE_EXTEND
1845	bool "Extend bootloader kernel arguments"
1846	help
1847	  The command-line arguments provided by the boot loader will be
1848	  appended to the default kernel command string.
1849
1850config CMDLINE_FORCE
1851	bool "Always use the default kernel command string"
1852	help
1853	  Always use the default kernel command string, even if the boot
1854	  loader passes other arguments to the kernel.
1855	  This is useful if you cannot or don't want to change the
1856	  command-line options your boot loader passes to the kernel.
1857
1858endchoice
1859
1860config EFI_STUB
1861	bool
1862
1863config EFI
1864	bool "UEFI runtime support"
1865	depends on OF && !CPU_BIG_ENDIAN
1866	depends on KERNEL_MODE_NEON
1867	select ARCH_SUPPORTS_ACPI
1868	select LIBFDT
1869	select UCS2_STRING
1870	select EFI_PARAMS_FROM_FDT
1871	select EFI_RUNTIME_WRAPPERS
1872	select EFI_STUB
1873	select EFI_GENERIC_STUB
1874	default y
1875	help
1876	  This option provides support for runtime services provided
1877	  by UEFI firmware (such as non-volatile variables, realtime
1878          clock, and platform reset). A UEFI stub is also provided to
1879	  allow the kernel to be booted as an EFI application. This
1880	  is only useful on systems that have UEFI firmware.
1881
1882config DMI
1883	bool "Enable support for SMBIOS (DMI) tables"
1884	depends on EFI
1885	default y
1886	help
1887	  This enables SMBIOS/DMI feature for systems.
1888
1889	  This option is only useful on systems that have UEFI firmware.
1890	  However, even with this option, the resultant kernel should
1891	  continue to boot on existing non-UEFI platforms.
1892
1893endmenu
1894
1895config SYSVIPC_COMPAT
1896	def_bool y
1897	depends on COMPAT && SYSVIPC
1898
1899config ARCH_ENABLE_HUGEPAGE_MIGRATION
1900	def_bool y
1901	depends on HUGETLB_PAGE && MIGRATION
1902
1903config ARCH_ENABLE_THP_MIGRATION
1904	def_bool y
1905	depends on TRANSPARENT_HUGEPAGE
1906
1907menu "Power management options"
1908
1909source "kernel/power/Kconfig"
1910
1911config ARCH_HIBERNATION_POSSIBLE
1912	def_bool y
1913	depends on CPU_PM
1914
1915config ARCH_HIBERNATION_HEADER
1916	def_bool y
1917	depends on HIBERNATION
1918
1919config ARCH_SUSPEND_POSSIBLE
1920	def_bool y
1921
1922endmenu
1923
1924menu "CPU Power Management"
1925
1926source "drivers/cpuidle/Kconfig"
1927
1928source "drivers/cpufreq/Kconfig"
1929
1930endmenu
1931
1932source "drivers/firmware/Kconfig"
1933
1934source "drivers/acpi/Kconfig"
1935
1936source "arch/arm64/kvm/Kconfig"
1937
1938if CRYPTO
1939source "arch/arm64/crypto/Kconfig"
1940endif
1941