1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_STATE 14 select ARCH_HAS_DEBUG_VIRTUAL 15 select ARCH_HAS_DEBUG_VM_PGTABLE 16 select ARCH_HAS_DEVMEM_IS_ALLOWED 17 select ARCH_HAS_DMA_PREP_COHERENT 18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 19 select ARCH_HAS_FAST_MULTIPLIER 20 select ARCH_HAS_FORTIFY_SOURCE 21 select ARCH_HAS_GCOV_PROFILE_ALL 22 select ARCH_HAS_GIGANTIC_PAGE 23 select ARCH_HAS_KCOV 24 select ARCH_HAS_KEEPINITRD 25 select ARCH_HAS_MEMBARRIER_SYNC_CORE 26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 27 select ARCH_HAS_PTE_DEVMAP 28 select ARCH_HAS_PTE_SPECIAL 29 select ARCH_HAS_SETUP_DMA_OPS 30 select ARCH_HAS_SET_DIRECT_MAP 31 select ARCH_HAS_SET_MEMORY 32 select ARCH_STACKWALK 33 select ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_HAS_STRICT_MODULE_RWX 35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 36 select ARCH_HAS_SYNC_DMA_FOR_CPU 37 select ARCH_HAS_SYSCALL_WRAPPER 38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 40 select ARCH_HAVE_ELF_PROT 41 select ARCH_HAVE_NMI_SAFE_CMPXCHG 42 select ARCH_INLINE_READ_LOCK if !PREEMPTION 43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_KEEP_MEMBLOCK 69 select ARCH_USE_CMPXCHG_LOCKREF 70 select ARCH_USE_GNU_PROPERTY 71 select ARCH_USE_QUEUED_RWLOCKS 72 select ARCH_USE_QUEUED_SPINLOCKS 73 select ARCH_USE_SYM_ANNOTATIONS 74 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 75 select ARCH_SUPPORTS_MEMORY_FAILURE 76 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 77 select ARCH_SUPPORTS_ATOMIC_RMW 78 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG) 79 select ARCH_SUPPORTS_NUMA_BALANCING 80 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 81 select ARCH_WANT_DEFAULT_BPF_JIT 82 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 83 select ARCH_WANT_FRAME_POINTERS 84 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 85 select ARCH_WANT_LD_ORPHAN_WARN 86 select ARCH_HAS_UBSAN_SANITIZE_ALL 87 select ARM_AMBA 88 select ARM_ARCH_TIMER 89 select ARM_GIC 90 select AUDIT_ARCH_COMPAT_GENERIC 91 select ARM_GIC_V2M if PCI 92 select ARM_GIC_V3 93 select ARM_GIC_V3_ITS if PCI 94 select ARM_PSCI_FW 95 select BUILDTIME_TABLE_SORT 96 select CLONE_BACKWARDS 97 select COMMON_CLK 98 select CPU_PM if (SUSPEND || CPU_IDLE) 99 select CRC32 100 select DCACHE_WORD_ACCESS 101 select DMA_DIRECT_REMAP 102 select EDAC_SUPPORT 103 select FRAME_POINTER 104 select GENERIC_ALLOCATOR 105 select GENERIC_ARCH_TOPOLOGY 106 select GENERIC_CLOCKEVENTS_BROADCAST 107 select GENERIC_CPU_AUTOPROBE 108 select GENERIC_CPU_VULNERABILITIES 109 select GENERIC_EARLY_IOREMAP 110 select GENERIC_IDLE_POLL_SETUP 111 select GENERIC_IRQ_IPI 112 select GENERIC_IRQ_MULTI_HANDLER 113 select GENERIC_IRQ_PROBE 114 select GENERIC_IRQ_SHOW 115 select GENERIC_IRQ_SHOW_LEVEL 116 select GENERIC_PCI_IOMAP 117 select GENERIC_PTDUMP 118 select GENERIC_SCHED_CLOCK 119 select GENERIC_SMP_IDLE_THREAD 120 select GENERIC_STRNCPY_FROM_USER 121 select GENERIC_STRNLEN_USER 122 select GENERIC_TIME_VSYSCALL 123 select GENERIC_GETTIMEOFDAY 124 select GENERIC_VDSO_TIME_NS 125 select HANDLE_DOMAIN_IRQ 126 select HARDIRQS_SW_RESEND 127 select HAVE_MOVE_PMD 128 select HAVE_MOVE_PUD 129 select HAVE_PCI 130 select HAVE_ACPI_APEI if (ACPI && EFI) 131 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 132 select HAVE_ARCH_AUDITSYSCALL 133 select HAVE_ARCH_BITREVERSE 134 select HAVE_ARCH_COMPILER_H 135 select HAVE_ARCH_HUGE_VMAP 136 select HAVE_ARCH_JUMP_LABEL 137 select HAVE_ARCH_JUMP_LABEL_RELATIVE 138 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 139 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 140 select HAVE_ARCH_KGDB 141 select HAVE_ARCH_MMAP_RND_BITS 142 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 143 select HAVE_ARCH_PFN_VALID 144 select HAVE_ARCH_PREL32_RELOCATIONS 145 select HAVE_ARCH_SECCOMP_FILTER 146 select HAVE_ARCH_STACKLEAK 147 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 148 select HAVE_ARCH_TRACEHOOK 149 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 150 select HAVE_ARCH_VMAP_STACK 151 select HAVE_ARM_SMCCC 152 select HAVE_ASM_MODVERSIONS 153 select HAVE_EBPF_JIT 154 select HAVE_C_RECORDMCOUNT 155 select HAVE_CMPXCHG_DOUBLE 156 select HAVE_CMPXCHG_LOCAL 157 select HAVE_CONTEXT_TRACKING 158 select HAVE_DEBUG_BUGVERBOSE 159 select HAVE_DEBUG_KMEMLEAK 160 select HAVE_DMA_CONTIGUOUS 161 select HAVE_DYNAMIC_FTRACE 162 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 163 if $(cc-option,-fpatchable-function-entry=2) 164 select HAVE_EFFICIENT_UNALIGNED_ACCESS 165 select HAVE_FAST_GUP 166 select HAVE_FTRACE_MCOUNT_RECORD 167 select HAVE_FUNCTION_TRACER 168 select HAVE_FUNCTION_ERROR_INJECTION 169 select HAVE_FUNCTION_GRAPH_TRACER 170 select HAVE_GCC_PLUGINS 171 select HAVE_HW_BREAKPOINT if PERF_EVENTS 172 select HAVE_IRQ_TIME_ACCOUNTING 173 select HAVE_NMI 174 select HAVE_PATA_PLATFORM 175 select HAVE_PERF_EVENTS 176 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS 177 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI 178 select HAVE_PERF_REGS 179 select HAVE_PERF_USER_STACK_DUMP 180 select HAVE_REGS_AND_STACK_ACCESS_API 181 select HAVE_FUNCTION_ARG_ACCESS_API 182 select HAVE_FUTEX_CMPXCHG if FUTEX 183 select MMU_GATHER_RCU_TABLE_FREE 184 select HAVE_RSEQ 185 select HAVE_STACKPROTECTOR 186 select HAVE_SYSCALL_TRACEPOINTS 187 select HAVE_KPROBES 188 select HAVE_KRETPROBES 189 select HAVE_GENERIC_VDSO 190 select IOMMU_DMA if IOMMU_SUPPORT 191 select IRQ_DOMAIN 192 select IRQ_FORCED_THREADING 193 select MODULES_USE_ELF_RELA 194 select NEED_DMA_MAP_STATE 195 select NEED_SG_DMA_LENGTH 196 select OF 197 select OF_EARLY_FLATTREE 198 select PCI_DOMAINS_GENERIC if PCI 199 select PCI_ECAM if (ACPI && PCI) 200 select PCI_SYSCALL if PCI 201 select POWER_RESET 202 select POWER_SUPPLY 203 select SPARSE_IRQ 204 select SWIOTLB 205 select SYSCTL_EXCEPTION_TRACE 206 select THREAD_INFO_IN_TASK 207 help 208 ARM 64-bit (AArch64) Linux support. 209 210config 64BIT 211 def_bool y 212 213config MMU 214 def_bool y 215 216config ARM64_PAGE_SHIFT 217 int 218 default 16 if ARM64_64K_PAGES 219 default 14 if ARM64_16K_PAGES 220 default 12 221 222config ARM64_CONT_PTE_SHIFT 223 int 224 default 5 if ARM64_64K_PAGES 225 default 7 if ARM64_16K_PAGES 226 default 4 227 228config ARM64_CONT_PMD_SHIFT 229 int 230 default 5 if ARM64_64K_PAGES 231 default 5 if ARM64_16K_PAGES 232 default 4 233 234config ARCH_MMAP_RND_BITS_MIN 235 default 14 if ARM64_64K_PAGES 236 default 16 if ARM64_16K_PAGES 237 default 18 238 239# max bits determined by the following formula: 240# VA_BITS - PAGE_SHIFT - 3 241config ARCH_MMAP_RND_BITS_MAX 242 default 19 if ARM64_VA_BITS=36 243 default 24 if ARM64_VA_BITS=39 244 default 27 if ARM64_VA_BITS=42 245 default 30 if ARM64_VA_BITS=47 246 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 247 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 248 default 33 if ARM64_VA_BITS=48 249 default 14 if ARM64_64K_PAGES 250 default 16 if ARM64_16K_PAGES 251 default 18 252 253config ARCH_MMAP_RND_COMPAT_BITS_MIN 254 default 7 if ARM64_64K_PAGES 255 default 9 if ARM64_16K_PAGES 256 default 11 257 258config ARCH_MMAP_RND_COMPAT_BITS_MAX 259 default 16 260 261config NO_IOPORT_MAP 262 def_bool y if !PCI 263 264config STACKTRACE_SUPPORT 265 def_bool y 266 267config ILLEGAL_POINTER_VALUE 268 hex 269 default 0xdead000000000000 270 271config LOCKDEP_SUPPORT 272 def_bool y 273 274config TRACE_IRQFLAGS_SUPPORT 275 def_bool y 276 277config GENERIC_BUG 278 def_bool y 279 depends on BUG 280 281config GENERIC_BUG_RELATIVE_POINTERS 282 def_bool y 283 depends on GENERIC_BUG 284 285config GENERIC_HWEIGHT 286 def_bool y 287 288config GENERIC_CSUM 289 def_bool y 290 291config GENERIC_CALIBRATE_DELAY 292 def_bool y 293 294config ZONE_DMA 295 bool "Support DMA zone" if EXPERT 296 default y 297 298config ZONE_DMA32 299 bool "Support DMA32 zone" if EXPERT 300 default y 301 302config ARCH_ENABLE_MEMORY_HOTPLUG 303 def_bool y 304 305config ARCH_ENABLE_MEMORY_HOTREMOVE 306 def_bool y 307 308config SMP 309 def_bool y 310 311config KERNEL_MODE_NEON 312 def_bool y 313 314config FIX_EARLYCON_MEM 315 def_bool y 316 317config PGTABLE_LEVELS 318 int 319 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 320 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 321 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 322 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 323 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 324 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 325 326config ARCH_SUPPORTS_UPROBES 327 def_bool y 328 329config ARCH_PROC_KCORE_TEXT 330 def_bool y 331 332config BROKEN_GAS_INST 333 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 334 335config KASAN_SHADOW_OFFSET 336 hex 337 depends on KASAN 338 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 339 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 340 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 341 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 342 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 343 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 344 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 345 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 346 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 347 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 348 default 0xffffffffffffffff 349 350source "arch/arm64/Kconfig.platforms" 351 352menu "Kernel Features" 353 354menu "ARM errata workarounds via the alternatives framework" 355 356config ARM64_WORKAROUND_CLEAN_CACHE 357 bool 358 359config ARM64_ERRATUM_826319 360 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 361 default y 362 select ARM64_WORKAROUND_CLEAN_CACHE 363 help 364 This option adds an alternative code sequence to work around ARM 365 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 366 AXI master interface and an L2 cache. 367 368 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 369 and is unable to accept a certain write via this interface, it will 370 not progress on read data presented on the read data channel and the 371 system can deadlock. 372 373 The workaround promotes data cache clean instructions to 374 data cache clean-and-invalidate. 375 Please note that this does not necessarily enable the workaround, 376 as it depends on the alternative framework, which will only patch 377 the kernel if an affected CPU is detected. 378 379 If unsure, say Y. 380 381config ARM64_ERRATUM_827319 382 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 383 default y 384 select ARM64_WORKAROUND_CLEAN_CACHE 385 help 386 This option adds an alternative code sequence to work around ARM 387 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 388 master interface and an L2 cache. 389 390 Under certain conditions this erratum can cause a clean line eviction 391 to occur at the same time as another transaction to the same address 392 on the AMBA 5 CHI interface, which can cause data corruption if the 393 interconnect reorders the two transactions. 394 395 The workaround promotes data cache clean instructions to 396 data cache clean-and-invalidate. 397 Please note that this does not necessarily enable the workaround, 398 as it depends on the alternative framework, which will only patch 399 the kernel if an affected CPU is detected. 400 401 If unsure, say Y. 402 403config ARM64_ERRATUM_824069 404 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 405 default y 406 select ARM64_WORKAROUND_CLEAN_CACHE 407 help 408 This option adds an alternative code sequence to work around ARM 409 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 410 to a coherent interconnect. 411 412 If a Cortex-A53 processor is executing a store or prefetch for 413 write instruction at the same time as a processor in another 414 cluster is executing a cache maintenance operation to the same 415 address, then this erratum might cause a clean cache line to be 416 incorrectly marked as dirty. 417 418 The workaround promotes data cache clean instructions to 419 data cache clean-and-invalidate. 420 Please note that this option does not necessarily enable the 421 workaround, as it depends on the alternative framework, which will 422 only patch the kernel if an affected CPU is detected. 423 424 If unsure, say Y. 425 426config ARM64_ERRATUM_819472 427 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 428 default y 429 select ARM64_WORKAROUND_CLEAN_CACHE 430 help 431 This option adds an alternative code sequence to work around ARM 432 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 433 present when it is connected to a coherent interconnect. 434 435 If the processor is executing a load and store exclusive sequence at 436 the same time as a processor in another cluster is executing a cache 437 maintenance operation to the same address, then this erratum might 438 cause data corruption. 439 440 The workaround promotes data cache clean instructions to 441 data cache clean-and-invalidate. 442 Please note that this does not necessarily enable the workaround, 443 as it depends on the alternative framework, which will only patch 444 the kernel if an affected CPU is detected. 445 446 If unsure, say Y. 447 448config ARM64_ERRATUM_832075 449 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 450 default y 451 help 452 This option adds an alternative code sequence to work around ARM 453 erratum 832075 on Cortex-A57 parts up to r1p2. 454 455 Affected Cortex-A57 parts might deadlock when exclusive load/store 456 instructions to Write-Back memory are mixed with Device loads. 457 458 The workaround is to promote device loads to use Load-Acquire 459 semantics. 460 Please note that this does not necessarily enable the workaround, 461 as it depends on the alternative framework, which will only patch 462 the kernel if an affected CPU is detected. 463 464 If unsure, say Y. 465 466config ARM64_ERRATUM_834220 467 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 468 depends on KVM 469 default y 470 help 471 This option adds an alternative code sequence to work around ARM 472 erratum 834220 on Cortex-A57 parts up to r1p2. 473 474 Affected Cortex-A57 parts might report a Stage 2 translation 475 fault as the result of a Stage 1 fault for load crossing a 476 page boundary when there is a permission or device memory 477 alignment fault at Stage 1 and a translation fault at Stage 2. 478 479 The workaround is to verify that the Stage 1 translation 480 doesn't generate a fault before handling the Stage 2 fault. 481 Please note that this does not necessarily enable the workaround, 482 as it depends on the alternative framework, which will only patch 483 the kernel if an affected CPU is detected. 484 485 If unsure, say Y. 486 487config ARM64_ERRATUM_845719 488 bool "Cortex-A53: 845719: a load might read incorrect data" 489 depends on COMPAT 490 default y 491 help 492 This option adds an alternative code sequence to work around ARM 493 erratum 845719 on Cortex-A53 parts up to r0p4. 494 495 When running a compat (AArch32) userspace on an affected Cortex-A53 496 part, a load at EL0 from a virtual address that matches the bottom 32 497 bits of the virtual address used by a recent load at (AArch64) EL1 498 might return incorrect data. 499 500 The workaround is to write the contextidr_el1 register on exception 501 return to a 32-bit task. 502 Please note that this does not necessarily enable the workaround, 503 as it depends on the alternative framework, which will only patch 504 the kernel if an affected CPU is detected. 505 506 If unsure, say Y. 507 508config ARM64_ERRATUM_843419 509 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 510 default y 511 select ARM64_MODULE_PLTS if MODULES 512 help 513 This option links the kernel with '--fix-cortex-a53-843419' and 514 enables PLT support to replace certain ADRP instructions, which can 515 cause subsequent memory accesses to use an incorrect address on 516 Cortex-A53 parts up to r0p4. 517 518 If unsure, say Y. 519 520config ARM64_ERRATUM_1024718 521 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 522 default y 523 help 524 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 525 526 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect 527 update of the hardware dirty bit when the DBM/AP bits are updated 528 without a break-before-make. The workaround is to disable the usage 529 of hardware DBM locally on the affected cores. CPUs not affected by 530 this erratum will continue to use the feature. 531 532 If unsure, say Y. 533 534config ARM64_ERRATUM_1418040 535 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 536 default y 537 depends on COMPAT 538 help 539 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 540 errata 1188873 and 1418040. 541 542 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 543 cause register corruption when accessing the timer registers 544 from AArch32 userspace. 545 546 If unsure, say Y. 547 548config ARM64_WORKAROUND_SPECULATIVE_AT 549 bool 550 551config ARM64_ERRATUM_1165522 552 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 553 default y 554 select ARM64_WORKAROUND_SPECULATIVE_AT 555 help 556 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 557 558 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 559 corrupted TLBs by speculating an AT instruction during a guest 560 context switch. 561 562 If unsure, say Y. 563 564config ARM64_ERRATUM_1319367 565 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 566 default y 567 select ARM64_WORKAROUND_SPECULATIVE_AT 568 help 569 This option adds work arounds for ARM Cortex-A57 erratum 1319537 570 and A72 erratum 1319367 571 572 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 573 speculating an AT instruction during a guest context switch. 574 575 If unsure, say Y. 576 577config ARM64_ERRATUM_1530923 578 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 579 default y 580 select ARM64_WORKAROUND_SPECULATIVE_AT 581 help 582 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 583 584 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 585 corrupted TLBs by speculating an AT instruction during a guest 586 context switch. 587 588 If unsure, say Y. 589 590config ARM64_WORKAROUND_REPEAT_TLBI 591 bool 592 593config ARM64_ERRATUM_1286807 594 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 595 default y 596 select ARM64_WORKAROUND_REPEAT_TLBI 597 help 598 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 599 600 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 601 address for a cacheable mapping of a location is being 602 accessed by a core while another core is remapping the virtual 603 address to a new physical page using the recommended 604 break-before-make sequence, then under very rare circumstances 605 TLBI+DSB completes before a read using the translation being 606 invalidated has been observed by other observers. The 607 workaround repeats the TLBI+DSB operation. 608 609config ARM64_ERRATUM_1463225 610 bool "Cortex-A76: Software Step might prevent interrupt recognition" 611 default y 612 help 613 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 614 615 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 616 of a system call instruction (SVC) can prevent recognition of 617 subsequent interrupts when software stepping is disabled in the 618 exception handler of the system call and either kernel debugging 619 is enabled or VHE is in use. 620 621 Work around the erratum by triggering a dummy step exception 622 when handling a system call from a task that is being stepped 623 in a VHE configuration of the kernel. 624 625 If unsure, say Y. 626 627config ARM64_ERRATUM_1542419 628 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 629 default y 630 help 631 This option adds a workaround for ARM Neoverse-N1 erratum 632 1542419. 633 634 Affected Neoverse-N1 cores could execute a stale instruction when 635 modified by another CPU. The workaround depends on a firmware 636 counterpart. 637 638 Workaround the issue by hiding the DIC feature from EL0. This 639 forces user-space to perform cache maintenance. 640 641 If unsure, say Y. 642 643config ARM64_ERRATUM_1508412 644 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 645 default y 646 help 647 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 648 649 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 650 of a store-exclusive or read of PAR_EL1 and a load with device or 651 non-cacheable memory attributes. The workaround depends on a firmware 652 counterpart. 653 654 KVM guests must also have the workaround implemented or they can 655 deadlock the system. 656 657 Work around the issue by inserting DMB SY barriers around PAR_EL1 658 register reads and warning KVM users. The DMB barrier is sufficient 659 to prevent a speculative PAR_EL1 read. 660 661 If unsure, say Y. 662 663config CAVIUM_ERRATUM_22375 664 bool "Cavium erratum 22375, 24313" 665 default y 666 help 667 Enable workaround for errata 22375 and 24313. 668 669 This implements two gicv3-its errata workarounds for ThunderX. Both 670 with a small impact affecting only ITS table allocation. 671 672 erratum 22375: only alloc 8MB table size 673 erratum 24313: ignore memory access type 674 675 The fixes are in ITS initialization and basically ignore memory access 676 type and table size provided by the TYPER and BASER registers. 677 678 If unsure, say Y. 679 680config CAVIUM_ERRATUM_23144 681 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 682 depends on NUMA 683 default y 684 help 685 ITS SYNC command hang for cross node io and collections/cpu mapping. 686 687 If unsure, say Y. 688 689config CAVIUM_ERRATUM_23154 690 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 691 default y 692 help 693 The gicv3 of ThunderX requires a modified version for 694 reading the IAR status to ensure data synchronization 695 (access to icc_iar1_el1 is not sync'ed before and after). 696 697 If unsure, say Y. 698 699config CAVIUM_ERRATUM_27456 700 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 701 default y 702 help 703 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 704 instructions may cause the icache to become corrupted if it 705 contains data for a non-current ASID. The fix is to 706 invalidate the icache when changing the mm context. 707 708 If unsure, say Y. 709 710config CAVIUM_ERRATUM_30115 711 bool "Cavium erratum 30115: Guest may disable interrupts in host" 712 default y 713 help 714 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 715 1.2, and T83 Pass 1.0, KVM guest execution may disable 716 interrupts in host. Trapping both GICv3 group-0 and group-1 717 accesses sidesteps the issue. 718 719 If unsure, say Y. 720 721config CAVIUM_TX2_ERRATUM_219 722 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 723 default y 724 help 725 On Cavium ThunderX2, a load, store or prefetch instruction between a 726 TTBR update and the corresponding context synchronizing operation can 727 cause a spurious Data Abort to be delivered to any hardware thread in 728 the CPU core. 729 730 Work around the issue by avoiding the problematic code sequence and 731 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 732 trap handler performs the corresponding register access, skips the 733 instruction and ensures context synchronization by virtue of the 734 exception return. 735 736 If unsure, say Y. 737 738config FUJITSU_ERRATUM_010001 739 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 740 default y 741 help 742 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 743 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 744 accesses may cause undefined fault (Data abort, DFSC=0b111111). 745 This fault occurs under a specific hardware condition when a 746 load/store instruction performs an address translation using: 747 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 748 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 749 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 750 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 751 752 The workaround is to ensure these bits are clear in TCR_ELx. 753 The workaround only affects the Fujitsu-A64FX. 754 755 If unsure, say Y. 756 757config HISILICON_ERRATUM_161600802 758 bool "Hip07 161600802: Erroneous redistributor VLPI base" 759 default y 760 help 761 The HiSilicon Hip07 SoC uses the wrong redistributor base 762 when issued ITS commands such as VMOVP and VMAPP, and requires 763 a 128kB offset to be applied to the target address in this commands. 764 765 If unsure, say Y. 766 767config QCOM_FALKOR_ERRATUM_1003 768 bool "Falkor E1003: Incorrect translation due to ASID change" 769 default y 770 help 771 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 772 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 773 in TTBR1_EL1, this situation only occurs in the entry trampoline and 774 then only for entries in the walk cache, since the leaf translation 775 is unchanged. Work around the erratum by invalidating the walk cache 776 entries for the trampoline before entering the kernel proper. 777 778config QCOM_FALKOR_ERRATUM_1009 779 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 780 default y 781 select ARM64_WORKAROUND_REPEAT_TLBI 782 help 783 On Falkor v1, the CPU may prematurely complete a DSB following a 784 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 785 one more time to fix the issue. 786 787 If unsure, say Y. 788 789config QCOM_QDF2400_ERRATUM_0065 790 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 791 default y 792 help 793 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 794 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 795 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 796 797 If unsure, say Y. 798 799config QCOM_FALKOR_ERRATUM_E1041 800 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 801 default y 802 help 803 Falkor CPU may speculatively fetch instructions from an improper 804 memory location when MMU translation is changed from SCTLR_ELn[M]=1 805 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 806 807 If unsure, say Y. 808 809config SOCIONEXT_SYNQUACER_PREITS 810 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 811 default y 812 help 813 Socionext Synquacer SoCs implement a separate h/w block to generate 814 MSI doorbell writes with non-zero values for the device ID. 815 816 If unsure, say Y. 817 818endmenu 819 820 821choice 822 prompt "Page size" 823 default ARM64_4K_PAGES 824 help 825 Page size (translation granule) configuration. 826 827config ARM64_4K_PAGES 828 bool "4KB" 829 help 830 This feature enables 4KB pages support. 831 832config ARM64_16K_PAGES 833 bool "16KB" 834 help 835 The system will use 16KB pages support. AArch32 emulation 836 requires applications compiled with 16K (or a multiple of 16K) 837 aligned segments. 838 839config ARM64_64K_PAGES 840 bool "64KB" 841 help 842 This feature enables 64KB pages support (4KB by default) 843 allowing only two levels of page tables and faster TLB 844 look-up. AArch32 emulation requires applications compiled 845 with 64K aligned segments. 846 847endchoice 848 849choice 850 prompt "Virtual address space size" 851 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 852 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 853 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 854 help 855 Allows choosing one of multiple possible virtual address 856 space sizes. The level of translation table is determined by 857 a combination of page size and virtual address space size. 858 859config ARM64_VA_BITS_36 860 bool "36-bit" if EXPERT 861 depends on ARM64_16K_PAGES 862 863config ARM64_VA_BITS_39 864 bool "39-bit" 865 depends on ARM64_4K_PAGES 866 867config ARM64_VA_BITS_42 868 bool "42-bit" 869 depends on ARM64_64K_PAGES 870 871config ARM64_VA_BITS_47 872 bool "47-bit" 873 depends on ARM64_16K_PAGES 874 875config ARM64_VA_BITS_48 876 bool "48-bit" 877 878config ARM64_VA_BITS_52 879 bool "52-bit" 880 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 881 help 882 Enable 52-bit virtual addressing for userspace when explicitly 883 requested via a hint to mmap(). The kernel will also use 52-bit 884 virtual addresses for its own mappings (provided HW support for 885 this feature is available, otherwise it reverts to 48-bit). 886 887 NOTE: Enabling 52-bit virtual addressing in conjunction with 888 ARMv8.3 Pointer Authentication will result in the PAC being 889 reduced from 7 bits to 3 bits, which may have a significant 890 impact on its susceptibility to brute-force attacks. 891 892 If unsure, select 48-bit virtual addressing instead. 893 894endchoice 895 896config ARM64_FORCE_52BIT 897 bool "Force 52-bit virtual addresses for userspace" 898 depends on ARM64_VA_BITS_52 && EXPERT 899 help 900 For systems with 52-bit userspace VAs enabled, the kernel will attempt 901 to maintain compatibility with older software by providing 48-bit VAs 902 unless a hint is supplied to mmap. 903 904 This configuration option disables the 48-bit compatibility logic, and 905 forces all userspace addresses to be 52-bit on HW that supports it. One 906 should only enable this configuration option for stress testing userspace 907 memory management code. If unsure say N here. 908 909config ARM64_VA_BITS 910 int 911 default 36 if ARM64_VA_BITS_36 912 default 39 if ARM64_VA_BITS_39 913 default 42 if ARM64_VA_BITS_42 914 default 47 if ARM64_VA_BITS_47 915 default 48 if ARM64_VA_BITS_48 916 default 52 if ARM64_VA_BITS_52 917 918choice 919 prompt "Physical address space size" 920 default ARM64_PA_BITS_48 921 help 922 Choose the maximum physical address range that the kernel will 923 support. 924 925config ARM64_PA_BITS_48 926 bool "48-bit" 927 928config ARM64_PA_BITS_52 929 bool "52-bit (ARMv8.2)" 930 depends on ARM64_64K_PAGES 931 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 932 help 933 Enable support for a 52-bit physical address space, introduced as 934 part of the ARMv8.2-LPA extension. 935 936 With this enabled, the kernel will also continue to work on CPUs that 937 do not support ARMv8.2-LPA, but with some added memory overhead (and 938 minor performance overhead). 939 940endchoice 941 942config ARM64_PA_BITS 943 int 944 default 48 if ARM64_PA_BITS_48 945 default 52 if ARM64_PA_BITS_52 946 947choice 948 prompt "Endianness" 949 default CPU_LITTLE_ENDIAN 950 help 951 Select the endianness of data accesses performed by the CPU. Userspace 952 applications will need to be compiled and linked for the endianness 953 that is selected here. 954 955config CPU_BIG_ENDIAN 956 bool "Build big-endian kernel" 957 help 958 Say Y if you plan on running a kernel with a big-endian userspace. 959 960config CPU_LITTLE_ENDIAN 961 bool "Build little-endian kernel" 962 help 963 Say Y if you plan on running a kernel with a little-endian userspace. 964 This is usually the case for distributions targeting arm64. 965 966endchoice 967 968config SCHED_MC 969 bool "Multi-core scheduler support" 970 help 971 Multi-core scheduler support improves the CPU scheduler's decision 972 making when dealing with multi-core CPU chips at a cost of slightly 973 increased overhead in some places. If unsure say N here. 974 975config SCHED_SMT 976 bool "SMT scheduler support" 977 help 978 Improves the CPU scheduler's decision making when dealing with 979 MultiThreading at a cost of slightly increased overhead in some 980 places. If unsure say N here. 981 982config NR_CPUS 983 int "Maximum number of CPUs (2-4096)" 984 range 2 4096 985 default "256" 986 987config HOTPLUG_CPU 988 bool "Support for hot-pluggable CPUs" 989 select GENERIC_IRQ_MIGRATION 990 help 991 Say Y here to experiment with turning CPUs off and on. CPUs 992 can be controlled through /sys/devices/system/cpu. 993 994# Common NUMA Features 995config NUMA 996 bool "NUMA Memory Allocation and Scheduler Support" 997 select ACPI_NUMA if ACPI 998 select OF_NUMA 999 help 1000 Enable NUMA (Non-Uniform Memory Access) support. 1001 1002 The kernel will try to allocate memory used by a CPU on the 1003 local memory of the CPU and add some more 1004 NUMA awareness to the kernel. 1005 1006config NODES_SHIFT 1007 int "Maximum NUMA Nodes (as a power of 2)" 1008 range 1 10 1009 default "4" 1010 depends on NEED_MULTIPLE_NODES 1011 help 1012 Specify the maximum number of NUMA Nodes available on the target 1013 system. Increases memory reserved to accommodate various tables. 1014 1015config USE_PERCPU_NUMA_NODE_ID 1016 def_bool y 1017 depends on NUMA 1018 1019config HAVE_SETUP_PER_CPU_AREA 1020 def_bool y 1021 depends on NUMA 1022 1023config NEED_PER_CPU_EMBED_FIRST_CHUNK 1024 def_bool y 1025 depends on NUMA 1026 1027config HOLES_IN_ZONE 1028 def_bool y 1029 1030source "kernel/Kconfig.hz" 1031 1032config ARCH_SPARSEMEM_ENABLE 1033 def_bool y 1034 select SPARSEMEM_VMEMMAP_ENABLE 1035 1036config ARCH_SPARSEMEM_DEFAULT 1037 def_bool ARCH_SPARSEMEM_ENABLE 1038 1039config ARCH_SELECT_MEMORY_MODEL 1040 def_bool ARCH_SPARSEMEM_ENABLE 1041 1042config ARCH_FLATMEM_ENABLE 1043 def_bool !NUMA 1044 1045config HW_PERF_EVENTS 1046 def_bool y 1047 depends on ARM_PMU 1048 1049config SYS_SUPPORTS_HUGETLBFS 1050 def_bool y 1051 1052config ARCH_WANT_HUGE_PMD_SHARE 1053 1054config ARCH_HAS_CACHE_LINE_SIZE 1055 def_bool y 1056 1057config ARCH_ENABLE_SPLIT_PMD_PTLOCK 1058 def_bool y if PGTABLE_LEVELS > 2 1059 1060# Supported by clang >= 7.0 1061config CC_HAVE_SHADOW_CALL_STACK 1062 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1063 1064config PARAVIRT 1065 bool "Enable paravirtualization code" 1066 help 1067 This changes the kernel so it can modify itself when it is run 1068 under a hypervisor, potentially improving performance significantly 1069 over full virtualization. 1070 1071config PARAVIRT_TIME_ACCOUNTING 1072 bool "Paravirtual steal time accounting" 1073 select PARAVIRT 1074 help 1075 Select this option to enable fine granularity task steal time 1076 accounting. Time spent executing other tasks in parallel with 1077 the current vCPU is discounted from the vCPU power. To account for 1078 that, there can be a small performance impact. 1079 1080 If in doubt, say N here. 1081 1082config KEXEC 1083 depends on PM_SLEEP_SMP 1084 select KEXEC_CORE 1085 bool "kexec system call" 1086 help 1087 kexec is a system call that implements the ability to shutdown your 1088 current kernel, and to start another kernel. It is like a reboot 1089 but it is independent of the system firmware. And like a reboot 1090 you can start any kernel with it, not just Linux. 1091 1092config KEXEC_FILE 1093 bool "kexec file based system call" 1094 select KEXEC_CORE 1095 help 1096 This is new version of kexec system call. This system call is 1097 file based and takes file descriptors as system call argument 1098 for kernel and initramfs as opposed to list of segments as 1099 accepted by previous system call. 1100 1101config KEXEC_SIG 1102 bool "Verify kernel signature during kexec_file_load() syscall" 1103 depends on KEXEC_FILE 1104 help 1105 Select this option to verify a signature with loaded kernel 1106 image. If configured, any attempt of loading a image without 1107 valid signature will fail. 1108 1109 In addition to that option, you need to enable signature 1110 verification for the corresponding kernel image type being 1111 loaded in order for this to work. 1112 1113config KEXEC_IMAGE_VERIFY_SIG 1114 bool "Enable Image signature verification support" 1115 default y 1116 depends on KEXEC_SIG 1117 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1118 help 1119 Enable Image signature verification support. 1120 1121comment "Support for PE file signature verification disabled" 1122 depends on KEXEC_SIG 1123 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1124 1125config CRASH_DUMP 1126 bool "Build kdump crash kernel" 1127 help 1128 Generate crash dump after being started by kexec. This should 1129 be normally only set in special crash dump kernels which are 1130 loaded in the main kernel with kexec-tools into a specially 1131 reserved region and then later executed after a crash by 1132 kdump/kexec. 1133 1134 For more details see Documentation/admin-guide/kdump/kdump.rst 1135 1136config XEN_DOM0 1137 def_bool y 1138 depends on XEN 1139 1140config XEN 1141 bool "Xen guest support on ARM64" 1142 depends on ARM64 && OF 1143 select SWIOTLB_XEN 1144 select PARAVIRT 1145 help 1146 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1147 1148config FORCE_MAX_ZONEORDER 1149 int 1150 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 1151 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 1152 default "11" 1153 help 1154 The kernel memory allocator divides physically contiguous memory 1155 blocks into "zones", where each zone is a power of two number of 1156 pages. This option selects the largest power of two that the kernel 1157 keeps in the memory allocator. If you need to allocate very large 1158 blocks of physically contiguous memory, then you may need to 1159 increase this value. 1160 1161 This config option is actually maximum order plus one. For example, 1162 a value of 11 means that the largest free memory block is 2^10 pages. 1163 1164 We make sure that we can allocate upto a HugePage size for each configuration. 1165 Hence we have : 1166 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1167 1168 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1169 4M allocations matching the default size used by generic code. 1170 1171config UNMAP_KERNEL_AT_EL0 1172 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1173 default y 1174 help 1175 Speculation attacks against some high-performance processors can 1176 be used to bypass MMU permission checks and leak kernel data to 1177 userspace. This can be defended against by unmapping the kernel 1178 when running in userspace, mapping it back in on exception entry 1179 via a trampoline page in the vector table. 1180 1181 If unsure, say Y. 1182 1183config RODATA_FULL_DEFAULT_ENABLED 1184 bool "Apply r/o permissions of VM areas also to their linear aliases" 1185 default y 1186 help 1187 Apply read-only attributes of VM areas to the linear alias of 1188 the backing pages as well. This prevents code or read-only data 1189 from being modified (inadvertently or intentionally) via another 1190 mapping of the same memory page. This additional enhancement can 1191 be turned off at runtime by passing rodata=[off|on] (and turned on 1192 with rodata=full if this option is set to 'n') 1193 1194 This requires the linear region to be mapped down to pages, 1195 which may adversely affect performance in some cases. 1196 1197config ARM64_SW_TTBR0_PAN 1198 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1199 help 1200 Enabling this option prevents the kernel from accessing 1201 user-space memory directly by pointing TTBR0_EL1 to a reserved 1202 zeroed area and reserved ASID. The user access routines 1203 restore the valid TTBR0_EL1 temporarily. 1204 1205config ARM64_TAGGED_ADDR_ABI 1206 bool "Enable the tagged user addresses syscall ABI" 1207 default y 1208 help 1209 When this option is enabled, user applications can opt in to a 1210 relaxed ABI via prctl() allowing tagged addresses to be passed 1211 to system calls as pointer arguments. For details, see 1212 Documentation/arm64/tagged-address-abi.rst. 1213 1214menuconfig COMPAT 1215 bool "Kernel support for 32-bit EL0" 1216 depends on ARM64_4K_PAGES || EXPERT 1217 select COMPAT_BINFMT_ELF if BINFMT_ELF 1218 select HAVE_UID16 1219 select OLD_SIGSUSPEND3 1220 select COMPAT_OLD_SIGACTION 1221 help 1222 This option enables support for a 32-bit EL0 running under a 64-bit 1223 kernel at EL1. AArch32-specific components such as system calls, 1224 the user helper functions, VFP support and the ptrace interface are 1225 handled appropriately by the kernel. 1226 1227 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1228 that you will only be able to execute AArch32 binaries that were compiled 1229 with page size aligned segments. 1230 1231 If you want to execute 32-bit userspace applications, say Y. 1232 1233if COMPAT 1234 1235config KUSER_HELPERS 1236 bool "Enable kuser helpers page for 32-bit applications" 1237 default y 1238 help 1239 Warning: disabling this option may break 32-bit user programs. 1240 1241 Provide kuser helpers to compat tasks. The kernel provides 1242 helper code to userspace in read only form at a fixed location 1243 to allow userspace to be independent of the CPU type fitted to 1244 the system. This permits binaries to be run on ARMv4 through 1245 to ARMv8 without modification. 1246 1247 See Documentation/arm/kernel_user_helpers.rst for details. 1248 1249 However, the fixed address nature of these helpers can be used 1250 by ROP (return orientated programming) authors when creating 1251 exploits. 1252 1253 If all of the binaries and libraries which run on your platform 1254 are built specifically for your platform, and make no use of 1255 these helpers, then you can turn this option off to hinder 1256 such exploits. However, in that case, if a binary or library 1257 relying on those helpers is run, it will not function correctly. 1258 1259 Say N here only if you are absolutely certain that you do not 1260 need these helpers; otherwise, the safe option is to say Y. 1261 1262config COMPAT_VDSO 1263 bool "Enable vDSO for 32-bit applications" 1264 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != "" 1265 select GENERIC_COMPAT_VDSO 1266 default y 1267 help 1268 Place in the process address space of 32-bit applications an 1269 ELF shared object providing fast implementations of gettimeofday 1270 and clock_gettime. 1271 1272 You must have a 32-bit build of glibc 2.22 or later for programs 1273 to seamlessly take advantage of this. 1274 1275config THUMB2_COMPAT_VDSO 1276 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1277 depends on COMPAT_VDSO 1278 default y 1279 help 1280 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1281 otherwise with '-marm'. 1282 1283menuconfig ARMV8_DEPRECATED 1284 bool "Emulate deprecated/obsolete ARMv8 instructions" 1285 depends on SYSCTL 1286 help 1287 Legacy software support may require certain instructions 1288 that have been deprecated or obsoleted in the architecture. 1289 1290 Enable this config to enable selective emulation of these 1291 features. 1292 1293 If unsure, say Y 1294 1295if ARMV8_DEPRECATED 1296 1297config SWP_EMULATION 1298 bool "Emulate SWP/SWPB instructions" 1299 help 1300 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1301 they are always undefined. Say Y here to enable software 1302 emulation of these instructions for userspace using LDXR/STXR. 1303 This feature can be controlled at runtime with the abi.swp 1304 sysctl which is disabled by default. 1305 1306 In some older versions of glibc [<=2.8] SWP is used during futex 1307 trylock() operations with the assumption that the code will not 1308 be preempted. This invalid assumption may be more likely to fail 1309 with SWP emulation enabled, leading to deadlock of the user 1310 application. 1311 1312 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1313 on an external transaction monitoring block called a global 1314 monitor to maintain update atomicity. If your system does not 1315 implement a global monitor, this option can cause programs that 1316 perform SWP operations to uncached memory to deadlock. 1317 1318 If unsure, say Y 1319 1320config CP15_BARRIER_EMULATION 1321 bool "Emulate CP15 Barrier instructions" 1322 help 1323 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1324 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1325 strongly recommended to use the ISB, DSB, and DMB 1326 instructions instead. 1327 1328 Say Y here to enable software emulation of these 1329 instructions for AArch32 userspace code. When this option is 1330 enabled, CP15 barrier usage is traced which can help 1331 identify software that needs updating. This feature can be 1332 controlled at runtime with the abi.cp15_barrier sysctl. 1333 1334 If unsure, say Y 1335 1336config SETEND_EMULATION 1337 bool "Emulate SETEND instruction" 1338 help 1339 The SETEND instruction alters the data-endianness of the 1340 AArch32 EL0, and is deprecated in ARMv8. 1341 1342 Say Y here to enable software emulation of the instruction 1343 for AArch32 userspace code. This feature can be controlled 1344 at runtime with the abi.setend sysctl. 1345 1346 Note: All the cpus on the system must have mixed endian support at EL0 1347 for this feature to be enabled. If a new CPU - which doesn't support mixed 1348 endian - is hotplugged in after this feature has been enabled, there could 1349 be unexpected results in the applications. 1350 1351 If unsure, say Y 1352endif 1353 1354endif 1355 1356menu "ARMv8.1 architectural features" 1357 1358config ARM64_HW_AFDBM 1359 bool "Support for hardware updates of the Access and Dirty page flags" 1360 default y 1361 help 1362 The ARMv8.1 architecture extensions introduce support for 1363 hardware updates of the access and dirty information in page 1364 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1365 capable processors, accesses to pages with PTE_AF cleared will 1366 set this bit instead of raising an access flag fault. 1367 Similarly, writes to read-only pages with the DBM bit set will 1368 clear the read-only bit (AP[2]) instead of raising a 1369 permission fault. 1370 1371 Kernels built with this configuration option enabled continue 1372 to work on pre-ARMv8.1 hardware and the performance impact is 1373 minimal. If unsure, say Y. 1374 1375config ARM64_PAN 1376 bool "Enable support for Privileged Access Never (PAN)" 1377 default y 1378 help 1379 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1380 prevents the kernel or hypervisor from accessing user-space (EL0) 1381 memory directly. 1382 1383 Choosing this option will cause any unprotected (not using 1384 copy_to_user et al) memory access to fail with a permission fault. 1385 1386 The feature is detected at runtime, and will remain as a 'nop' 1387 instruction if the cpu does not implement the feature. 1388 1389config AS_HAS_LDAPR 1390 def_bool $(as-instr,.arch_extension rcpc) 1391 1392config ARM64_LSE_ATOMICS 1393 bool 1394 default ARM64_USE_LSE_ATOMICS 1395 depends on $(as-instr,.arch_extension lse) 1396 1397config ARM64_USE_LSE_ATOMICS 1398 bool "Atomic instructions" 1399 depends on JUMP_LABEL 1400 default y 1401 help 1402 As part of the Large System Extensions, ARMv8.1 introduces new 1403 atomic instructions that are designed specifically to scale in 1404 very large systems. 1405 1406 Say Y here to make use of these instructions for the in-kernel 1407 atomic routines. This incurs a small overhead on CPUs that do 1408 not support these instructions and requires the kernel to be 1409 built with binutils >= 2.25 in order for the new instructions 1410 to be used. 1411 1412config ARM64_VHE 1413 bool "Enable support for Virtualization Host Extensions (VHE)" 1414 default y 1415 help 1416 Virtualization Host Extensions (VHE) allow the kernel to run 1417 directly at EL2 (instead of EL1) on processors that support 1418 it. This leads to better performance for KVM, as they reduce 1419 the cost of the world switch. 1420 1421 Selecting this option allows the VHE feature to be detected 1422 at runtime, and does not affect processors that do not 1423 implement this feature. 1424 1425endmenu 1426 1427menu "ARMv8.2 architectural features" 1428 1429config ARM64_PMEM 1430 bool "Enable support for persistent memory" 1431 select ARCH_HAS_PMEM_API 1432 select ARCH_HAS_UACCESS_FLUSHCACHE 1433 help 1434 Say Y to enable support for the persistent memory API based on the 1435 ARMv8.2 DCPoP feature. 1436 1437 The feature is detected at runtime, and the kernel will use DC CVAC 1438 operations if DC CVAP is not supported (following the behaviour of 1439 DC CVAP itself if the system does not define a point of persistence). 1440 1441config ARM64_RAS_EXTN 1442 bool "Enable support for RAS CPU Extensions" 1443 default y 1444 help 1445 CPUs that support the Reliability, Availability and Serviceability 1446 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1447 errors, classify them and report them to software. 1448 1449 On CPUs with these extensions system software can use additional 1450 barriers to determine if faults are pending and read the 1451 classification from a new set of registers. 1452 1453 Selecting this feature will allow the kernel to use these barriers 1454 and access the new registers if the system supports the extension. 1455 Platform RAS features may additionally depend on firmware support. 1456 1457config ARM64_CNP 1458 bool "Enable support for Common Not Private (CNP) translations" 1459 default y 1460 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1461 help 1462 Common Not Private (CNP) allows translation table entries to 1463 be shared between different PEs in the same inner shareable 1464 domain, so the hardware can use this fact to optimise the 1465 caching of such entries in the TLB. 1466 1467 Selecting this option allows the CNP feature to be detected 1468 at runtime, and does not affect PEs that do not implement 1469 this feature. 1470 1471endmenu 1472 1473menu "ARMv8.3 architectural features" 1474 1475config ARM64_PTR_AUTH 1476 bool "Enable support for pointer authentication" 1477 default y 1478 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1479 # Modern compilers insert a .note.gnu.property section note for PAC 1480 # which is only understood by binutils starting with version 2.33.1. 1481 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100) 1482 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1483 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1484 help 1485 Pointer authentication (part of the ARMv8.3 Extensions) provides 1486 instructions for signing and authenticating pointers against secret 1487 keys, which can be used to mitigate Return Oriented Programming (ROP) 1488 and other attacks. 1489 1490 This option enables these instructions at EL0 (i.e. for userspace). 1491 Choosing this option will cause the kernel to initialise secret keys 1492 for each process at exec() time, with these keys being 1493 context-switched along with the process. 1494 1495 If the compiler supports the -mbranch-protection or 1496 -msign-return-address flag (e.g. GCC 7 or later), then this option 1497 will also cause the kernel itself to be compiled with return address 1498 protection. In this case, and if the target hardware is known to 1499 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1500 disabled with minimal loss of protection. 1501 1502 The feature is detected at runtime. If the feature is not present in 1503 hardware it will not be advertised to userspace/KVM guest nor will it 1504 be enabled. 1505 1506 If the feature is present on the boot CPU but not on a late CPU, then 1507 the late CPU will be parked. Also, if the boot CPU does not have 1508 address auth and the late CPU has then the late CPU will still boot 1509 but with the feature disabled. On such a system, this option should 1510 not be selected. 1511 1512 This feature works with FUNCTION_GRAPH_TRACER option only if 1513 DYNAMIC_FTRACE_WITH_REGS is enabled. 1514 1515config CC_HAS_BRANCH_PROT_PAC_RET 1516 # GCC 9 or later, clang 8 or later 1517 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1518 1519config CC_HAS_SIGN_RETURN_ADDRESS 1520 # GCC 7, 8 1521 def_bool $(cc-option,-msign-return-address=all) 1522 1523config AS_HAS_PAC 1524 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1525 1526config AS_HAS_CFI_NEGATE_RA_STATE 1527 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1528 1529endmenu 1530 1531menu "ARMv8.4 architectural features" 1532 1533config ARM64_AMU_EXTN 1534 bool "Enable support for the Activity Monitors Unit CPU extension" 1535 default y 1536 help 1537 The activity monitors extension is an optional extension introduced 1538 by the ARMv8.4 CPU architecture. This enables support for version 1 1539 of the activity monitors architecture, AMUv1. 1540 1541 To enable the use of this extension on CPUs that implement it, say Y. 1542 1543 Note that for architectural reasons, firmware _must_ implement AMU 1544 support when running on CPUs that present the activity monitors 1545 extension. The required support is present in: 1546 * Version 1.5 and later of the ARM Trusted Firmware 1547 1548 For kernels that have this configuration enabled but boot with broken 1549 firmware, you may need to say N here until the firmware is fixed. 1550 Otherwise you may experience firmware panics or lockups when 1551 accessing the counter registers. Even if you are not observing these 1552 symptoms, the values returned by the register reads might not 1553 correctly reflect reality. Most commonly, the value read will be 0, 1554 indicating that the counter is not enabled. 1555 1556config AS_HAS_ARMV8_4 1557 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1558 1559config ARM64_TLB_RANGE 1560 bool "Enable support for tlbi range feature" 1561 default y 1562 depends on AS_HAS_ARMV8_4 1563 help 1564 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1565 range of input addresses. 1566 1567 The feature introduces new assembly instructions, and they were 1568 support when binutils >= 2.30. 1569 1570endmenu 1571 1572menu "ARMv8.5 architectural features" 1573 1574config ARM64_BTI 1575 bool "Branch Target Identification support" 1576 default y 1577 help 1578 Branch Target Identification (part of the ARMv8.5 Extensions) 1579 provides a mechanism to limit the set of locations to which computed 1580 branch instructions such as BR or BLR can jump. 1581 1582 To make use of BTI on CPUs that support it, say Y. 1583 1584 BTI is intended to provide complementary protection to other control 1585 flow integrity protection mechanisms, such as the Pointer 1586 authentication mechanism provided as part of the ARMv8.3 Extensions. 1587 For this reason, it does not make sense to enable this option without 1588 also enabling support for pointer authentication. Thus, when 1589 enabling this option you should also select ARM64_PTR_AUTH=y. 1590 1591 Userspace binaries must also be specifically compiled to make use of 1592 this mechanism. If you say N here or the hardware does not support 1593 BTI, such binaries can still run, but you get no additional 1594 enforcement of branch destinations. 1595 1596config ARM64_BTI_KERNEL 1597 bool "Use Branch Target Identification for kernel" 1598 default y 1599 depends on ARM64_BTI 1600 depends on ARM64_PTR_AUTH 1601 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1602 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1603 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1604 depends on !(CC_IS_CLANG && GCOV_KERNEL) 1605 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1606 help 1607 Build the kernel with Branch Target Identification annotations 1608 and enable enforcement of this for kernel code. When this option 1609 is enabled and the system supports BTI all kernel code including 1610 modular code must have BTI enabled. 1611 1612config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1613 # GCC 9 or later, clang 8 or later 1614 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1615 1616config ARM64_E0PD 1617 bool "Enable support for E0PD" 1618 default y 1619 help 1620 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1621 that EL0 accesses made via TTBR1 always fault in constant time, 1622 providing similar benefits to KASLR as those provided by KPTI, but 1623 with lower overhead and without disrupting legitimate access to 1624 kernel memory such as SPE. 1625 1626 This option enables E0PD for TTBR1 where available. 1627 1628config ARCH_RANDOM 1629 bool "Enable support for random number generation" 1630 default y 1631 help 1632 Random number generation (part of the ARMv8.5 Extensions) 1633 provides a high bandwidth, cryptographically secure 1634 hardware random number generator. 1635 1636config ARM64_AS_HAS_MTE 1637 # Initial support for MTE went in binutils 2.32.0, checked with 1638 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1639 # as a late addition to the final architecture spec (LDGM/STGM) 1640 # is only supported in the newer 2.32.x and 2.33 binutils 1641 # versions, hence the extra "stgm" instruction check below. 1642 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1643 1644config ARM64_MTE 1645 bool "Memory Tagging Extension support" 1646 default y 1647 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1648 select ARCH_USES_HIGH_VMA_FLAGS 1649 help 1650 Memory Tagging (part of the ARMv8.5 Extensions) provides 1651 architectural support for run-time, always-on detection of 1652 various classes of memory error to aid with software debugging 1653 to eliminate vulnerabilities arising from memory-unsafe 1654 languages. 1655 1656 This option enables the support for the Memory Tagging 1657 Extension at EL0 (i.e. for userspace). 1658 1659 Selecting this option allows the feature to be detected at 1660 runtime. Any secondary CPU not implementing this feature will 1661 not be allowed a late bring-up. 1662 1663 Userspace binaries that want to use this feature must 1664 explicitly opt in. The mechanism for the userspace is 1665 described in: 1666 1667 Documentation/arm64/memory-tagging-extension.rst. 1668 1669endmenu 1670 1671config ARM64_SVE 1672 bool "ARM Scalable Vector Extension support" 1673 default y 1674 depends on !KVM || ARM64_VHE 1675 help 1676 The Scalable Vector Extension (SVE) is an extension to the AArch64 1677 execution state which complements and extends the SIMD functionality 1678 of the base architecture to support much larger vectors and to enable 1679 additional vectorisation opportunities. 1680 1681 To enable use of this extension on CPUs that implement it, say Y. 1682 1683 On CPUs that support the SVE2 extensions, this option will enable 1684 those too. 1685 1686 Note that for architectural reasons, firmware _must_ implement SVE 1687 support when running on SVE capable hardware. The required support 1688 is present in: 1689 1690 * version 1.5 and later of the ARM Trusted Firmware 1691 * the AArch64 boot wrapper since commit 5e1261e08abf 1692 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1693 1694 For other firmware implementations, consult the firmware documentation 1695 or vendor. 1696 1697 If you need the kernel to boot on SVE-capable hardware with broken 1698 firmware, you may need to say N here until you get your firmware 1699 fixed. Otherwise, you may experience firmware panics or lockups when 1700 booting the kernel. If unsure and you are not observing these 1701 symptoms, you should assume that it is safe to say Y. 1702 1703 CPUs that support SVE are architecturally required to support the 1704 Virtualization Host Extensions (VHE), so the kernel makes no 1705 provision for supporting SVE alongside KVM without VHE enabled. 1706 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support 1707 KVM in the same kernel image. 1708 1709config ARM64_MODULE_PLTS 1710 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1711 depends on MODULES 1712 select HAVE_MOD_ARCH_SPECIFIC 1713 help 1714 Allocate PLTs when loading modules so that jumps and calls whose 1715 targets are too far away for their relative offsets to be encoded 1716 in the instructions themselves can be bounced via veneers in the 1717 module's PLT. This allows modules to be allocated in the generic 1718 vmalloc area after the dedicated module memory area has been 1719 exhausted. 1720 1721 When running with address space randomization (KASLR), the module 1722 region itself may be too far away for ordinary relative jumps and 1723 calls, and so in that case, module PLTs are required and cannot be 1724 disabled. 1725 1726 Specific errata workaround(s) might also force module PLTs to be 1727 enabled (ARM64_ERRATUM_843419). 1728 1729config ARM64_PSEUDO_NMI 1730 bool "Support for NMI-like interrupts" 1731 select ARM_GIC_V3 1732 help 1733 Adds support for mimicking Non-Maskable Interrupts through the use of 1734 GIC interrupt priority. This support requires version 3 or later of 1735 ARM GIC. 1736 1737 This high priority configuration for interrupts needs to be 1738 explicitly enabled by setting the kernel parameter 1739 "irqchip.gicv3_pseudo_nmi" to 1. 1740 1741 If unsure, say N 1742 1743if ARM64_PSEUDO_NMI 1744config ARM64_DEBUG_PRIORITY_MASKING 1745 bool "Debug interrupt priority masking" 1746 help 1747 This adds runtime checks to functions enabling/disabling 1748 interrupts when using priority masking. The additional checks verify 1749 the validity of ICC_PMR_EL1 when calling concerned functions. 1750 1751 If unsure, say N 1752endif 1753 1754config RELOCATABLE 1755 bool "Build a relocatable kernel image" if EXPERT 1756 select ARCH_HAS_RELR 1757 default y 1758 help 1759 This builds the kernel as a Position Independent Executable (PIE), 1760 which retains all relocation metadata required to relocate the 1761 kernel binary at runtime to a different virtual address than the 1762 address it was linked at. 1763 Since AArch64 uses the RELA relocation format, this requires a 1764 relocation pass at runtime even if the kernel is loaded at the 1765 same address it was linked at. 1766 1767config RANDOMIZE_BASE 1768 bool "Randomize the address of the kernel image" 1769 select ARM64_MODULE_PLTS if MODULES 1770 select RELOCATABLE 1771 help 1772 Randomizes the virtual address at which the kernel image is 1773 loaded, as a security feature that deters exploit attempts 1774 relying on knowledge of the location of kernel internals. 1775 1776 It is the bootloader's job to provide entropy, by passing a 1777 random u64 value in /chosen/kaslr-seed at kernel entry. 1778 1779 When booting via the UEFI stub, it will invoke the firmware's 1780 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1781 to the kernel proper. In addition, it will randomise the physical 1782 location of the kernel Image as well. 1783 1784 If unsure, say N. 1785 1786config RANDOMIZE_MODULE_REGION_FULL 1787 bool "Randomize the module region over a 4 GB range" 1788 depends on RANDOMIZE_BASE 1789 default y 1790 help 1791 Randomizes the location of the module region inside a 4 GB window 1792 covering the core kernel. This way, it is less likely for modules 1793 to leak information about the location of core kernel data structures 1794 but it does imply that function calls between modules and the core 1795 kernel will need to be resolved via veneers in the module PLT. 1796 1797 When this option is not set, the module region will be randomized over 1798 a limited range that contains the [_stext, _etext] interval of the 1799 core kernel, so branch relocations are always in range. 1800 1801config CC_HAVE_STACKPROTECTOR_SYSREG 1802 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 1803 1804config STACKPROTECTOR_PER_TASK 1805 def_bool y 1806 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 1807 1808endmenu 1809 1810menu "Boot options" 1811 1812config ARM64_ACPI_PARKING_PROTOCOL 1813 bool "Enable support for the ARM64 ACPI parking protocol" 1814 depends on ACPI 1815 help 1816 Enable support for the ARM64 ACPI parking protocol. If disabled 1817 the kernel will not allow booting through the ARM64 ACPI parking 1818 protocol even if the corresponding data is present in the ACPI 1819 MADT table. 1820 1821config CMDLINE 1822 string "Default kernel command string" 1823 default "" 1824 help 1825 Provide a set of default command-line options at build time by 1826 entering them here. As a minimum, you should specify the the 1827 root device (e.g. root=/dev/nfs). 1828 1829choice 1830 prompt "Kernel command line type" if CMDLINE != "" 1831 default CMDLINE_FROM_BOOTLOADER 1832 help 1833 Choose how the kernel will handle the provided default kernel 1834 command line string. 1835 1836config CMDLINE_FROM_BOOTLOADER 1837 bool "Use bootloader kernel arguments if available" 1838 help 1839 Uses the command-line options passed by the boot loader. If 1840 the boot loader doesn't provide any, the default kernel command 1841 string provided in CMDLINE will be used. 1842 1843config CMDLINE_EXTEND 1844 bool "Extend bootloader kernel arguments" 1845 help 1846 The command-line arguments provided by the boot loader will be 1847 appended to the default kernel command string. 1848 1849config CMDLINE_FORCE 1850 bool "Always use the default kernel command string" 1851 help 1852 Always use the default kernel command string, even if the boot 1853 loader passes other arguments to the kernel. 1854 This is useful if you cannot or don't want to change the 1855 command-line options your boot loader passes to the kernel. 1856 1857endchoice 1858 1859config EFI_STUB 1860 bool 1861 1862config EFI 1863 bool "UEFI runtime support" 1864 depends on OF && !CPU_BIG_ENDIAN 1865 depends on KERNEL_MODE_NEON 1866 select ARCH_SUPPORTS_ACPI 1867 select LIBFDT 1868 select UCS2_STRING 1869 select EFI_PARAMS_FROM_FDT 1870 select EFI_RUNTIME_WRAPPERS 1871 select EFI_STUB 1872 select EFI_GENERIC_STUB 1873 default y 1874 help 1875 This option provides support for runtime services provided 1876 by UEFI firmware (such as non-volatile variables, realtime 1877 clock, and platform reset). A UEFI stub is also provided to 1878 allow the kernel to be booted as an EFI application. This 1879 is only useful on systems that have UEFI firmware. 1880 1881config DMI 1882 bool "Enable support for SMBIOS (DMI) tables" 1883 depends on EFI 1884 default y 1885 help 1886 This enables SMBIOS/DMI feature for systems. 1887 1888 This option is only useful on systems that have UEFI firmware. 1889 However, even with this option, the resultant kernel should 1890 continue to boot on existing non-UEFI platforms. 1891 1892endmenu 1893 1894config SYSVIPC_COMPAT 1895 def_bool y 1896 depends on COMPAT && SYSVIPC 1897 1898config ARCH_ENABLE_HUGEPAGE_MIGRATION 1899 def_bool y 1900 depends on HUGETLB_PAGE && MIGRATION 1901 1902config ARCH_ENABLE_THP_MIGRATION 1903 def_bool y 1904 depends on TRANSPARENT_HUGEPAGE 1905 1906menu "Power management options" 1907 1908source "kernel/power/Kconfig" 1909 1910config ARCH_HIBERNATION_POSSIBLE 1911 def_bool y 1912 depends on CPU_PM 1913 1914config ARCH_HIBERNATION_HEADER 1915 def_bool y 1916 depends on HIBERNATION 1917 1918config ARCH_SUSPEND_POSSIBLE 1919 def_bool y 1920 1921endmenu 1922 1923menu "CPU Power Management" 1924 1925source "drivers/cpuidle/Kconfig" 1926 1927source "drivers/cpufreq/Kconfig" 1928 1929endmenu 1930 1931source "drivers/firmware/Kconfig" 1932 1933source "drivers/acpi/Kconfig" 1934 1935source "arch/arm64/kvm/Kconfig" 1936 1937if CRYPTO 1938source "arch/arm64/crypto/Kconfig" 1939endif 1940