1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 7 select ARCH_HAS_ELF_RANDOMIZE 8 select ARCH_HAS_GCOV_PROFILE_ALL 9 select ARCH_HAS_SG_CHAIN 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 11 select ARCH_USE_CMPXCHG_LOCKREF 12 select ARCH_SUPPORTS_ATOMIC_RMW 13 select ARCH_WANT_OPTIONAL_GPIOLIB 14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 15 select ARCH_WANT_FRAME_POINTERS 16 select ARM_AMBA 17 select ARM_ARCH_TIMER 18 select ARM_GIC 19 select AUDIT_ARCH_COMPAT_GENERIC 20 select ARM_GIC_V2M if PCI_MSI 21 select ARM_GIC_V3 22 select ARM_GIC_V3_ITS if PCI_MSI 23 select ARM_PSCI_FW 24 select BUILDTIME_EXTABLE_SORT 25 select CLONE_BACKWARDS 26 select COMMON_CLK 27 select CPU_PM if (SUSPEND || CPU_IDLE) 28 select DCACHE_WORD_ACCESS 29 select EDAC_SUPPORT 30 select GENERIC_ALLOCATOR 31 select GENERIC_CLOCKEVENTS 32 select GENERIC_CLOCKEVENTS_BROADCAST 33 select GENERIC_CPU_AUTOPROBE 34 select GENERIC_EARLY_IOREMAP 35 select GENERIC_IRQ_PROBE 36 select GENERIC_IRQ_SHOW 37 select GENERIC_IRQ_SHOW_LEVEL 38 select GENERIC_PCI_IOMAP 39 select GENERIC_SCHED_CLOCK 40 select GENERIC_SMP_IDLE_THREAD 41 select GENERIC_STRNCPY_FROM_USER 42 select GENERIC_STRNLEN_USER 43 select GENERIC_TIME_VSYSCALL 44 select HANDLE_DOMAIN_IRQ 45 select HARDIRQS_SW_RESEND 46 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 47 select HAVE_ARCH_AUDITSYSCALL 48 select HAVE_ARCH_BITREVERSE 49 select HAVE_ARCH_JUMP_LABEL 50 select HAVE_ARCH_KGDB 51 select HAVE_ARCH_SECCOMP_FILTER 52 select HAVE_ARCH_TRACEHOOK 53 select HAVE_BPF_JIT 54 select HAVE_C_RECORDMCOUNT 55 select HAVE_CC_STACKPROTECTOR 56 select HAVE_CMPXCHG_DOUBLE 57 select HAVE_CMPXCHG_LOCAL 58 select HAVE_DEBUG_BUGVERBOSE 59 select HAVE_DEBUG_KMEMLEAK 60 select HAVE_DMA_API_DEBUG 61 select HAVE_DMA_ATTRS 62 select HAVE_DMA_CONTIGUOUS 63 select HAVE_DYNAMIC_FTRACE 64 select HAVE_EFFICIENT_UNALIGNED_ACCESS 65 select HAVE_FTRACE_MCOUNT_RECORD 66 select HAVE_FUNCTION_TRACER 67 select HAVE_FUNCTION_GRAPH_TRACER 68 select HAVE_GENERIC_DMA_COHERENT 69 select HAVE_HW_BREAKPOINT if PERF_EVENTS 70 select HAVE_MEMBLOCK 71 select HAVE_PATA_PLATFORM 72 select HAVE_PERF_EVENTS 73 select HAVE_PERF_REGS 74 select HAVE_PERF_USER_STACK_DUMP 75 select HAVE_RCU_TABLE_FREE 76 select HAVE_SYSCALL_TRACEPOINTS 77 select IRQ_DOMAIN 78 select IRQ_FORCED_THREADING 79 select MODULES_USE_ELF_RELA 80 select NO_BOOTMEM 81 select OF 82 select OF_EARLY_FLATTREE 83 select OF_RESERVED_MEM 84 select PERF_USE_VMALLOC 85 select POWER_RESET 86 select POWER_SUPPLY 87 select RTC_LIB 88 select SPARSE_IRQ 89 select SYSCTL_EXCEPTION_TRACE 90 select HAVE_CONTEXT_TRACKING 91 help 92 ARM 64-bit (AArch64) Linux support. 93 94config 64BIT 95 def_bool y 96 97config ARCH_PHYS_ADDR_T_64BIT 98 def_bool y 99 100config MMU 101 def_bool y 102 103config NO_IOPORT_MAP 104 def_bool y if !PCI 105 106config STACKTRACE_SUPPORT 107 def_bool y 108 109config ILLEGAL_POINTER_VALUE 110 hex 111 default 0xdead000000000000 112 113config LOCKDEP_SUPPORT 114 def_bool y 115 116config TRACE_IRQFLAGS_SUPPORT 117 def_bool y 118 119config RWSEM_XCHGADD_ALGORITHM 120 def_bool y 121 122config GENERIC_BUG 123 def_bool y 124 depends on BUG 125 126config GENERIC_BUG_RELATIVE_POINTERS 127 def_bool y 128 depends on GENERIC_BUG 129 130config GENERIC_HWEIGHT 131 def_bool y 132 133config GENERIC_CSUM 134 def_bool y 135 136config GENERIC_CALIBRATE_DELAY 137 def_bool y 138 139config ZONE_DMA 140 def_bool y 141 142config HAVE_GENERIC_RCU_GUP 143 def_bool y 144 145config ARCH_DMA_ADDR_T_64BIT 146 def_bool y 147 148config NEED_DMA_MAP_STATE 149 def_bool y 150 151config NEED_SG_DMA_LENGTH 152 def_bool y 153 154config SMP 155 def_bool y 156 157config SWIOTLB 158 def_bool y 159 160config IOMMU_HELPER 161 def_bool SWIOTLB 162 163config KERNEL_MODE_NEON 164 def_bool y 165 166config FIX_EARLYCON_MEM 167 def_bool y 168 169config PGTABLE_LEVELS 170 int 171 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 172 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 173 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 174 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 175 176source "init/Kconfig" 177 178source "kernel/Kconfig.freezer" 179 180source "arch/arm64/Kconfig.platforms" 181 182menu "Bus support" 183 184config PCI 185 bool "PCI support" 186 help 187 This feature enables support for PCI bus system. If you say Y 188 here, the kernel will include drivers and infrastructure code 189 to support PCI bus devices. 190 191config PCI_DOMAINS 192 def_bool PCI 193 194config PCI_DOMAINS_GENERIC 195 def_bool PCI 196 197config PCI_SYSCALL 198 def_bool PCI 199 200source "drivers/pci/Kconfig" 201source "drivers/pci/pcie/Kconfig" 202source "drivers/pci/hotplug/Kconfig" 203 204endmenu 205 206menu "Kernel Features" 207 208menu "ARM errata workarounds via the alternatives framework" 209 210config ARM64_ERRATUM_826319 211 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 212 default y 213 help 214 This option adds an alternative code sequence to work around ARM 215 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 216 AXI master interface and an L2 cache. 217 218 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 219 and is unable to accept a certain write via this interface, it will 220 not progress on read data presented on the read data channel and the 221 system can deadlock. 222 223 The workaround promotes data cache clean instructions to 224 data cache clean-and-invalidate. 225 Please note that this does not necessarily enable the workaround, 226 as it depends on the alternative framework, which will only patch 227 the kernel if an affected CPU is detected. 228 229 If unsure, say Y. 230 231config ARM64_ERRATUM_827319 232 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 233 default y 234 help 235 This option adds an alternative code sequence to work around ARM 236 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 237 master interface and an L2 cache. 238 239 Under certain conditions this erratum can cause a clean line eviction 240 to occur at the same time as another transaction to the same address 241 on the AMBA 5 CHI interface, which can cause data corruption if the 242 interconnect reorders the two transactions. 243 244 The workaround promotes data cache clean instructions to 245 data cache clean-and-invalidate. 246 Please note that this does not necessarily enable the workaround, 247 as it depends on the alternative framework, which will only patch 248 the kernel if an affected CPU is detected. 249 250 If unsure, say Y. 251 252config ARM64_ERRATUM_824069 253 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 254 default y 255 help 256 This option adds an alternative code sequence to work around ARM 257 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 258 to a coherent interconnect. 259 260 If a Cortex-A53 processor is executing a store or prefetch for 261 write instruction at the same time as a processor in another 262 cluster is executing a cache maintenance operation to the same 263 address, then this erratum might cause a clean cache line to be 264 incorrectly marked as dirty. 265 266 The workaround promotes data cache clean instructions to 267 data cache clean-and-invalidate. 268 Please note that this option does not necessarily enable the 269 workaround, as it depends on the alternative framework, which will 270 only patch the kernel if an affected CPU is detected. 271 272 If unsure, say Y. 273 274config ARM64_ERRATUM_819472 275 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 276 default y 277 help 278 This option adds an alternative code sequence to work around ARM 279 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 280 present when it is connected to a coherent interconnect. 281 282 If the processor is executing a load and store exclusive sequence at 283 the same time as a processor in another cluster is executing a cache 284 maintenance operation to the same address, then this erratum might 285 cause data corruption. 286 287 The workaround promotes data cache clean instructions to 288 data cache clean-and-invalidate. 289 Please note that this does not necessarily enable the workaround, 290 as it depends on the alternative framework, which will only patch 291 the kernel if an affected CPU is detected. 292 293 If unsure, say Y. 294 295config ARM64_ERRATUM_832075 296 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 297 default y 298 help 299 This option adds an alternative code sequence to work around ARM 300 erratum 832075 on Cortex-A57 parts up to r1p2. 301 302 Affected Cortex-A57 parts might deadlock when exclusive load/store 303 instructions to Write-Back memory are mixed with Device loads. 304 305 The workaround is to promote device loads to use Load-Acquire 306 semantics. 307 Please note that this does not necessarily enable the workaround, 308 as it depends on the alternative framework, which will only patch 309 the kernel if an affected CPU is detected. 310 311 If unsure, say Y. 312 313config ARM64_ERRATUM_845719 314 bool "Cortex-A53: 845719: a load might read incorrect data" 315 depends on COMPAT 316 default y 317 help 318 This option adds an alternative code sequence to work around ARM 319 erratum 845719 on Cortex-A53 parts up to r0p4. 320 321 When running a compat (AArch32) userspace on an affected Cortex-A53 322 part, a load at EL0 from a virtual address that matches the bottom 32 323 bits of the virtual address used by a recent load at (AArch64) EL1 324 might return incorrect data. 325 326 The workaround is to write the contextidr_el1 register on exception 327 return to a 32-bit task. 328 Please note that this does not necessarily enable the workaround, 329 as it depends on the alternative framework, which will only patch 330 the kernel if an affected CPU is detected. 331 332 If unsure, say Y. 333 334endmenu 335 336 337choice 338 prompt "Page size" 339 default ARM64_4K_PAGES 340 help 341 Page size (translation granule) configuration. 342 343config ARM64_4K_PAGES 344 bool "4KB" 345 help 346 This feature enables 4KB pages support. 347 348config ARM64_64K_PAGES 349 bool "64KB" 350 help 351 This feature enables 64KB pages support (4KB by default) 352 allowing only two levels of page tables and faster TLB 353 look-up. AArch32 emulation is not available when this feature 354 is enabled. 355 356endchoice 357 358choice 359 prompt "Virtual address space size" 360 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 361 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 362 help 363 Allows choosing one of multiple possible virtual address 364 space sizes. The level of translation table is determined by 365 a combination of page size and virtual address space size. 366 367config ARM64_VA_BITS_39 368 bool "39-bit" 369 depends on ARM64_4K_PAGES 370 371config ARM64_VA_BITS_42 372 bool "42-bit" 373 depends on ARM64_64K_PAGES 374 375config ARM64_VA_BITS_48 376 bool "48-bit" 377 378endchoice 379 380config ARM64_VA_BITS 381 int 382 default 39 if ARM64_VA_BITS_39 383 default 42 if ARM64_VA_BITS_42 384 default 48 if ARM64_VA_BITS_48 385 386config CPU_BIG_ENDIAN 387 bool "Build big-endian kernel" 388 help 389 Say Y if you plan on running a kernel in big-endian mode. 390 391config SCHED_MC 392 bool "Multi-core scheduler support" 393 help 394 Multi-core scheduler support improves the CPU scheduler's decision 395 making when dealing with multi-core CPU chips at a cost of slightly 396 increased overhead in some places. If unsure say N here. 397 398config SCHED_SMT 399 bool "SMT scheduler support" 400 help 401 Improves the CPU scheduler's decision making when dealing with 402 MultiThreading at a cost of slightly increased overhead in some 403 places. If unsure say N here. 404 405config NR_CPUS 406 int "Maximum number of CPUs (2-4096)" 407 range 2 4096 408 # These have to remain sorted largest to smallest 409 default "64" 410 411config HOTPLUG_CPU 412 bool "Support for hot-pluggable CPUs" 413 help 414 Say Y here to experiment with turning CPUs off and on. CPUs 415 can be controlled through /sys/devices/system/cpu. 416 417source kernel/Kconfig.preempt 418 419config HZ 420 int 421 default 100 422 423config ARCH_HAS_HOLES_MEMORYMODEL 424 def_bool y if SPARSEMEM 425 426config ARCH_SPARSEMEM_ENABLE 427 def_bool y 428 select SPARSEMEM_VMEMMAP_ENABLE 429 430config ARCH_SPARSEMEM_DEFAULT 431 def_bool ARCH_SPARSEMEM_ENABLE 432 433config ARCH_SELECT_MEMORY_MODEL 434 def_bool ARCH_SPARSEMEM_ENABLE 435 436config HAVE_ARCH_PFN_VALID 437 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 438 439config HW_PERF_EVENTS 440 bool "Enable hardware performance counter support for perf events" 441 depends on PERF_EVENTS 442 default y 443 help 444 Enable hardware performance counter support for perf events. If 445 disabled, perf events will use software events only. 446 447config SYS_SUPPORTS_HUGETLBFS 448 def_bool y 449 450config ARCH_WANT_GENERAL_HUGETLB 451 def_bool y 452 453config ARCH_WANT_HUGE_PMD_SHARE 454 def_bool y if !ARM64_64K_PAGES 455 456config HAVE_ARCH_TRANSPARENT_HUGEPAGE 457 def_bool y 458 459config ARCH_HAS_CACHE_LINE_SIZE 460 def_bool y 461 462source "mm/Kconfig" 463 464config SECCOMP 465 bool "Enable seccomp to safely compute untrusted bytecode" 466 ---help--- 467 This kernel feature is useful for number crunching applications 468 that may need to compute untrusted bytecode during their 469 execution. By using pipes or other transports made available to 470 the process as file descriptors supporting the read/write 471 syscalls, it's possible to isolate those applications in 472 their own address space using seccomp. Once seccomp is 473 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 474 and the task is only allowed to execute a few safe syscalls 475 defined by each seccomp mode. 476 477config XEN_DOM0 478 def_bool y 479 depends on XEN 480 481config XEN 482 bool "Xen guest support on ARM64" 483 depends on ARM64 && OF 484 select SWIOTLB_XEN 485 help 486 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 487 488config FORCE_MAX_ZONEORDER 489 int 490 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 491 default "11" 492 493menuconfig ARMV8_DEPRECATED 494 bool "Emulate deprecated/obsolete ARMv8 instructions" 495 depends on COMPAT 496 help 497 Legacy software support may require certain instructions 498 that have been deprecated or obsoleted in the architecture. 499 500 Enable this config to enable selective emulation of these 501 features. 502 503 If unsure, say Y 504 505if ARMV8_DEPRECATED 506 507config SWP_EMULATION 508 bool "Emulate SWP/SWPB instructions" 509 help 510 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 511 they are always undefined. Say Y here to enable software 512 emulation of these instructions for userspace using LDXR/STXR. 513 514 In some older versions of glibc [<=2.8] SWP is used during futex 515 trylock() operations with the assumption that the code will not 516 be preempted. This invalid assumption may be more likely to fail 517 with SWP emulation enabled, leading to deadlock of the user 518 application. 519 520 NOTE: when accessing uncached shared regions, LDXR/STXR rely 521 on an external transaction monitoring block called a global 522 monitor to maintain update atomicity. If your system does not 523 implement a global monitor, this option can cause programs that 524 perform SWP operations to uncached memory to deadlock. 525 526 If unsure, say Y 527 528config CP15_BARRIER_EMULATION 529 bool "Emulate CP15 Barrier instructions" 530 help 531 The CP15 barrier instructions - CP15ISB, CP15DSB, and 532 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 533 strongly recommended to use the ISB, DSB, and DMB 534 instructions instead. 535 536 Say Y here to enable software emulation of these 537 instructions for AArch32 userspace code. When this option is 538 enabled, CP15 barrier usage is traced which can help 539 identify software that needs updating. 540 541 If unsure, say Y 542 543config SETEND_EMULATION 544 bool "Emulate SETEND instruction" 545 help 546 The SETEND instruction alters the data-endianness of the 547 AArch32 EL0, and is deprecated in ARMv8. 548 549 Say Y here to enable software emulation of the instruction 550 for AArch32 userspace code. 551 552 Note: All the cpus on the system must have mixed endian support at EL0 553 for this feature to be enabled. If a new CPU - which doesn't support mixed 554 endian - is hotplugged in after this feature has been enabled, there could 555 be unexpected results in the applications. 556 557 If unsure, say Y 558endif 559 560menu "ARMv8.1 architectural features" 561 562config ARM64_HW_AFDBM 563 bool "Support for hardware updates of the Access and Dirty page flags" 564 default y 565 help 566 The ARMv8.1 architecture extensions introduce support for 567 hardware updates of the access and dirty information in page 568 table entries. When enabled in TCR_EL1 (HA and HD bits) on 569 capable processors, accesses to pages with PTE_AF cleared will 570 set this bit instead of raising an access flag fault. 571 Similarly, writes to read-only pages with the DBM bit set will 572 clear the read-only bit (AP[2]) instead of raising a 573 permission fault. 574 575 Kernels built with this configuration option enabled continue 576 to work on pre-ARMv8.1 hardware and the performance impact is 577 minimal. If unsure, say Y. 578 579config ARM64_PAN 580 bool "Enable support for Privileged Access Never (PAN)" 581 default y 582 help 583 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 584 prevents the kernel or hypervisor from accessing user-space (EL0) 585 memory directly. 586 587 Choosing this option will cause any unprotected (not using 588 copy_to_user et al) memory access to fail with a permission fault. 589 590 The feature is detected at runtime, and will remain as a 'nop' 591 instruction if the cpu does not implement the feature. 592 593config ARM64_LSE_ATOMICS 594 bool "Atomic instructions" 595 help 596 As part of the Large System Extensions, ARMv8.1 introduces new 597 atomic instructions that are designed specifically to scale in 598 very large systems. 599 600 Say Y here to make use of these instructions for the in-kernel 601 atomic routines. This incurs a small overhead on CPUs that do 602 not support these instructions and requires the kernel to be 603 built with binutils >= 2.25. 604 605endmenu 606 607endmenu 608 609menu "Boot options" 610 611config CMDLINE 612 string "Default kernel command string" 613 default "" 614 help 615 Provide a set of default command-line options at build time by 616 entering them here. As a minimum, you should specify the the 617 root device (e.g. root=/dev/nfs). 618 619config CMDLINE_FORCE 620 bool "Always use the default kernel command string" 621 help 622 Always use the default kernel command string, even if the boot 623 loader passes other arguments to the kernel. 624 This is useful if you cannot or don't want to change the 625 command-line options your boot loader passes to the kernel. 626 627config EFI_STUB 628 bool 629 630config EFI 631 bool "UEFI runtime support" 632 depends on OF && !CPU_BIG_ENDIAN 633 select LIBFDT 634 select UCS2_STRING 635 select EFI_PARAMS_FROM_FDT 636 select EFI_RUNTIME_WRAPPERS 637 select EFI_STUB 638 select EFI_ARMSTUB 639 default y 640 help 641 This option provides support for runtime services provided 642 by UEFI firmware (such as non-volatile variables, realtime 643 clock, and platform reset). A UEFI stub is also provided to 644 allow the kernel to be booted as an EFI application. This 645 is only useful on systems that have UEFI firmware. 646 647config DMI 648 bool "Enable support for SMBIOS (DMI) tables" 649 depends on EFI 650 default y 651 help 652 This enables SMBIOS/DMI feature for systems. 653 654 This option is only useful on systems that have UEFI firmware. 655 However, even with this option, the resultant kernel should 656 continue to boot on existing non-UEFI platforms. 657 658endmenu 659 660menu "Userspace binary formats" 661 662source "fs/Kconfig.binfmt" 663 664config COMPAT 665 bool "Kernel support for 32-bit EL0" 666 depends on !ARM64_64K_PAGES || EXPERT 667 select COMPAT_BINFMT_ELF 668 select HAVE_UID16 669 select OLD_SIGSUSPEND3 670 select COMPAT_OLD_SIGACTION 671 help 672 This option enables support for a 32-bit EL0 running under a 64-bit 673 kernel at EL1. AArch32-specific components such as system calls, 674 the user helper functions, VFP support and the ptrace interface are 675 handled appropriately by the kernel. 676 677 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you 678 will only be able to execute AArch32 binaries that were compiled with 679 64k aligned segments. 680 681 If you want to execute 32-bit userspace applications, say Y. 682 683config SYSVIPC_COMPAT 684 def_bool y 685 depends on COMPAT && SYSVIPC 686 687endmenu 688 689menu "Power management options" 690 691source "kernel/power/Kconfig" 692 693config ARCH_SUSPEND_POSSIBLE 694 def_bool y 695 696endmenu 697 698menu "CPU Power Management" 699 700source "drivers/cpuidle/Kconfig" 701 702source "drivers/cpufreq/Kconfig" 703 704endmenu 705 706source "net/Kconfig" 707 708source "drivers/Kconfig" 709 710source "drivers/firmware/Kconfig" 711 712source "drivers/acpi/Kconfig" 713 714source "fs/Kconfig" 715 716source "arch/arm64/kvm/Kconfig" 717 718source "arch/arm64/Kconfig.debug" 719 720source "security/Kconfig" 721 722source "crypto/Kconfig" 723if CRYPTO 724source "arch/arm64/crypto/Kconfig" 725endif 726 727source "lib/Kconfig" 728