1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ACPI_MCFG if ACPI 7 select ACPI_SPCR_TABLE if ACPI 8 select ARCH_CLOCKSOURCE_DATA 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_GCOV_PROFILE_ALL 13 select ARCH_HAS_GIGANTIC_PAGE 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_SG_CHAIN 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 17 select ARCH_USE_CMPXCHG_LOCKREF 18 select ARCH_SUPPORTS_ATOMIC_RMW 19 select ARCH_SUPPORTS_NUMA_BALANCING 20 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 21 select ARCH_WANT_FRAME_POINTERS 22 select ARCH_HAS_UBSAN_SANITIZE_ALL 23 select ARM_AMBA 24 select ARM_ARCH_TIMER 25 select ARM_GIC 26 select AUDIT_ARCH_COMPAT_GENERIC 27 select ARM_GIC_V2M if PCI 28 select ARM_GIC_V3 29 select ARM_GIC_V3_ITS if PCI 30 select ARM_PSCI_FW 31 select BUILDTIME_EXTABLE_SORT 32 select CLONE_BACKWARDS 33 select COMMON_CLK 34 select CPU_PM if (SUSPEND || CPU_IDLE) 35 select DCACHE_WORD_ACCESS 36 select EDAC_SUPPORT 37 select FRAME_POINTER 38 select GENERIC_ALLOCATOR 39 select GENERIC_CLOCKEVENTS 40 select GENERIC_CLOCKEVENTS_BROADCAST 41 select GENERIC_CPU_AUTOPROBE 42 select GENERIC_EARLY_IOREMAP 43 select GENERIC_IDLE_POLL_SETUP 44 select GENERIC_IRQ_PROBE 45 select GENERIC_IRQ_SHOW 46 select GENERIC_IRQ_SHOW_LEVEL 47 select GENERIC_PCI_IOMAP 48 select GENERIC_SCHED_CLOCK 49 select GENERIC_SMP_IDLE_THREAD 50 select GENERIC_STRNCPY_FROM_USER 51 select GENERIC_STRNLEN_USER 52 select GENERIC_TIME_VSYSCALL 53 select HANDLE_DOMAIN_IRQ 54 select HARDIRQS_SW_RESEND 55 select HAVE_ACPI_APEI if (ACPI && EFI) 56 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 57 select HAVE_ARCH_AUDITSYSCALL 58 select HAVE_ARCH_BITREVERSE 59 select HAVE_ARCH_HARDENED_USERCOPY 60 select HAVE_ARCH_HUGE_VMAP 61 select HAVE_ARCH_JUMP_LABEL 62 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 63 select HAVE_ARCH_KGDB 64 select HAVE_ARCH_MMAP_RND_BITS 65 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 66 select HAVE_ARCH_SECCOMP_FILTER 67 select HAVE_ARCH_TRACEHOOK 68 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 69 select HAVE_ARM_SMCCC 70 select HAVE_EBPF_JIT 71 select HAVE_C_RECORDMCOUNT 72 select HAVE_CC_STACKPROTECTOR 73 select HAVE_CMPXCHG_DOUBLE 74 select HAVE_CMPXCHG_LOCAL 75 select HAVE_CONTEXT_TRACKING 76 select HAVE_DEBUG_BUGVERBOSE 77 select HAVE_DEBUG_KMEMLEAK 78 select HAVE_DMA_API_DEBUG 79 select HAVE_DMA_CONTIGUOUS 80 select HAVE_DYNAMIC_FTRACE 81 select HAVE_EFFICIENT_UNALIGNED_ACCESS 82 select HAVE_FTRACE_MCOUNT_RECORD 83 select HAVE_FUNCTION_TRACER 84 select HAVE_FUNCTION_GRAPH_TRACER 85 select HAVE_GCC_PLUGINS 86 select HAVE_GENERIC_DMA_COHERENT 87 select HAVE_HW_BREAKPOINT if PERF_EVENTS 88 select HAVE_IRQ_TIME_ACCOUNTING 89 select HAVE_MEMBLOCK 90 select HAVE_MEMBLOCK_NODE_MAP if NUMA 91 select HAVE_PATA_PLATFORM 92 select HAVE_PERF_EVENTS 93 select HAVE_PERF_REGS 94 select HAVE_PERF_USER_STACK_DUMP 95 select HAVE_REGS_AND_STACK_ACCESS_API 96 select HAVE_RCU_TABLE_FREE 97 select HAVE_SYSCALL_TRACEPOINTS 98 select HAVE_KPROBES 99 select HAVE_KRETPROBES if HAVE_KPROBES 100 select IOMMU_DMA if IOMMU_SUPPORT 101 select IRQ_DOMAIN 102 select IRQ_FORCED_THREADING 103 select MODULES_USE_ELF_RELA 104 select NO_BOOTMEM 105 select OF 106 select OF_EARLY_FLATTREE 107 select OF_RESERVED_MEM 108 select PCI_ECAM if ACPI 109 select POWER_RESET 110 select POWER_SUPPLY 111 select SPARSE_IRQ 112 select SYSCTL_EXCEPTION_TRACE 113 select THREAD_INFO_IN_TASK 114 help 115 ARM 64-bit (AArch64) Linux support. 116 117config 64BIT 118 def_bool y 119 120config ARCH_PHYS_ADDR_T_64BIT 121 def_bool y 122 123config MMU 124 def_bool y 125 126config DEBUG_RODATA 127 def_bool y 128 129config ARM64_PAGE_SHIFT 130 int 131 default 16 if ARM64_64K_PAGES 132 default 14 if ARM64_16K_PAGES 133 default 12 134 135config ARM64_CONT_SHIFT 136 int 137 default 5 if ARM64_64K_PAGES 138 default 7 if ARM64_16K_PAGES 139 default 4 140 141config ARCH_MMAP_RND_BITS_MIN 142 default 14 if ARM64_64K_PAGES 143 default 16 if ARM64_16K_PAGES 144 default 18 145 146# max bits determined by the following formula: 147# VA_BITS - PAGE_SHIFT - 3 148config ARCH_MMAP_RND_BITS_MAX 149 default 19 if ARM64_VA_BITS=36 150 default 24 if ARM64_VA_BITS=39 151 default 27 if ARM64_VA_BITS=42 152 default 30 if ARM64_VA_BITS=47 153 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 154 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 155 default 33 if ARM64_VA_BITS=48 156 default 14 if ARM64_64K_PAGES 157 default 16 if ARM64_16K_PAGES 158 default 18 159 160config ARCH_MMAP_RND_COMPAT_BITS_MIN 161 default 7 if ARM64_64K_PAGES 162 default 9 if ARM64_16K_PAGES 163 default 11 164 165config ARCH_MMAP_RND_COMPAT_BITS_MAX 166 default 16 167 168config NO_IOPORT_MAP 169 def_bool y if !PCI 170 171config STACKTRACE_SUPPORT 172 def_bool y 173 174config ILLEGAL_POINTER_VALUE 175 hex 176 default 0xdead000000000000 177 178config LOCKDEP_SUPPORT 179 def_bool y 180 181config TRACE_IRQFLAGS_SUPPORT 182 def_bool y 183 184config RWSEM_XCHGADD_ALGORITHM 185 def_bool y 186 187config GENERIC_BUG 188 def_bool y 189 depends on BUG 190 191config GENERIC_BUG_RELATIVE_POINTERS 192 def_bool y 193 depends on GENERIC_BUG 194 195config GENERIC_HWEIGHT 196 def_bool y 197 198config GENERIC_CSUM 199 def_bool y 200 201config GENERIC_CALIBRATE_DELAY 202 def_bool y 203 204config ZONE_DMA 205 def_bool y 206 207config HAVE_GENERIC_RCU_GUP 208 def_bool y 209 210config ARCH_DMA_ADDR_T_64BIT 211 def_bool y 212 213config NEED_DMA_MAP_STATE 214 def_bool y 215 216config NEED_SG_DMA_LENGTH 217 def_bool y 218 219config SMP 220 def_bool y 221 222config SWIOTLB 223 def_bool y 224 225config IOMMU_HELPER 226 def_bool SWIOTLB 227 228config KERNEL_MODE_NEON 229 def_bool y 230 231config FIX_EARLYCON_MEM 232 def_bool y 233 234config PGTABLE_LEVELS 235 int 236 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 237 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 238 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 239 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 240 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 241 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 242 243config ARCH_SUPPORTS_UPROBES 244 def_bool y 245 246source "init/Kconfig" 247 248source "kernel/Kconfig.freezer" 249 250source "arch/arm64/Kconfig.platforms" 251 252menu "Bus support" 253 254config PCI 255 bool "PCI support" 256 help 257 This feature enables support for PCI bus system. If you say Y 258 here, the kernel will include drivers and infrastructure code 259 to support PCI bus devices. 260 261config PCI_DOMAINS 262 def_bool PCI 263 264config PCI_DOMAINS_GENERIC 265 def_bool PCI 266 267config PCI_SYSCALL 268 def_bool PCI 269 270source "drivers/pci/Kconfig" 271 272endmenu 273 274menu "Kernel Features" 275 276menu "ARM errata workarounds via the alternatives framework" 277 278config ARM64_ERRATUM_826319 279 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 280 default y 281 help 282 This option adds an alternative code sequence to work around ARM 283 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 284 AXI master interface and an L2 cache. 285 286 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 287 and is unable to accept a certain write via this interface, it will 288 not progress on read data presented on the read data channel and the 289 system can deadlock. 290 291 The workaround promotes data cache clean instructions to 292 data cache clean-and-invalidate. 293 Please note that this does not necessarily enable the workaround, 294 as it depends on the alternative framework, which will only patch 295 the kernel if an affected CPU is detected. 296 297 If unsure, say Y. 298 299config ARM64_ERRATUM_827319 300 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 301 default y 302 help 303 This option adds an alternative code sequence to work around ARM 304 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 305 master interface and an L2 cache. 306 307 Under certain conditions this erratum can cause a clean line eviction 308 to occur at the same time as another transaction to the same address 309 on the AMBA 5 CHI interface, which can cause data corruption if the 310 interconnect reorders the two transactions. 311 312 The workaround promotes data cache clean instructions to 313 data cache clean-and-invalidate. 314 Please note that this does not necessarily enable the workaround, 315 as it depends on the alternative framework, which will only patch 316 the kernel if an affected CPU is detected. 317 318 If unsure, say Y. 319 320config ARM64_ERRATUM_824069 321 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 322 default y 323 help 324 This option adds an alternative code sequence to work around ARM 325 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 326 to a coherent interconnect. 327 328 If a Cortex-A53 processor is executing a store or prefetch for 329 write instruction at the same time as a processor in another 330 cluster is executing a cache maintenance operation to the same 331 address, then this erratum might cause a clean cache line to be 332 incorrectly marked as dirty. 333 334 The workaround promotes data cache clean instructions to 335 data cache clean-and-invalidate. 336 Please note that this option does not necessarily enable the 337 workaround, as it depends on the alternative framework, which will 338 only patch the kernel if an affected CPU is detected. 339 340 If unsure, say Y. 341 342config ARM64_ERRATUM_819472 343 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 344 default y 345 help 346 This option adds an alternative code sequence to work around ARM 347 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 348 present when it is connected to a coherent interconnect. 349 350 If the processor is executing a load and store exclusive sequence at 351 the same time as a processor in another cluster is executing a cache 352 maintenance operation to the same address, then this erratum might 353 cause data corruption. 354 355 The workaround promotes data cache clean instructions to 356 data cache clean-and-invalidate. 357 Please note that this does not necessarily enable the workaround, 358 as it depends on the alternative framework, which will only patch 359 the kernel if an affected CPU is detected. 360 361 If unsure, say Y. 362 363config ARM64_ERRATUM_832075 364 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 365 default y 366 help 367 This option adds an alternative code sequence to work around ARM 368 erratum 832075 on Cortex-A57 parts up to r1p2. 369 370 Affected Cortex-A57 parts might deadlock when exclusive load/store 371 instructions to Write-Back memory are mixed with Device loads. 372 373 The workaround is to promote device loads to use Load-Acquire 374 semantics. 375 Please note that this does not necessarily enable the workaround, 376 as it depends on the alternative framework, which will only patch 377 the kernel if an affected CPU is detected. 378 379 If unsure, say Y. 380 381config ARM64_ERRATUM_834220 382 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 383 depends on KVM 384 default y 385 help 386 This option adds an alternative code sequence to work around ARM 387 erratum 834220 on Cortex-A57 parts up to r1p2. 388 389 Affected Cortex-A57 parts might report a Stage 2 translation 390 fault as the result of a Stage 1 fault for load crossing a 391 page boundary when there is a permission or device memory 392 alignment fault at Stage 1 and a translation fault at Stage 2. 393 394 The workaround is to verify that the Stage 1 translation 395 doesn't generate a fault before handling the Stage 2 fault. 396 Please note that this does not necessarily enable the workaround, 397 as it depends on the alternative framework, which will only patch 398 the kernel if an affected CPU is detected. 399 400 If unsure, say Y. 401 402config ARM64_ERRATUM_845719 403 bool "Cortex-A53: 845719: a load might read incorrect data" 404 depends on COMPAT 405 default y 406 help 407 This option adds an alternative code sequence to work around ARM 408 erratum 845719 on Cortex-A53 parts up to r0p4. 409 410 When running a compat (AArch32) userspace on an affected Cortex-A53 411 part, a load at EL0 from a virtual address that matches the bottom 32 412 bits of the virtual address used by a recent load at (AArch64) EL1 413 might return incorrect data. 414 415 The workaround is to write the contextidr_el1 register on exception 416 return to a 32-bit task. 417 Please note that this does not necessarily enable the workaround, 418 as it depends on the alternative framework, which will only patch 419 the kernel if an affected CPU is detected. 420 421 If unsure, say Y. 422 423config ARM64_ERRATUM_843419 424 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 425 default y 426 select ARM64_MODULE_CMODEL_LARGE if MODULES 427 help 428 This option links the kernel with '--fix-cortex-a53-843419' and 429 builds modules using the large memory model in order to avoid the use 430 of the ADRP instruction, which can cause a subsequent memory access 431 to use an incorrect address on Cortex-A53 parts up to r0p4. 432 433 If unsure, say Y. 434 435config CAVIUM_ERRATUM_22375 436 bool "Cavium erratum 22375, 24313" 437 default y 438 help 439 Enable workaround for erratum 22375, 24313. 440 441 This implements two gicv3-its errata workarounds for ThunderX. Both 442 with small impact affecting only ITS table allocation. 443 444 erratum 22375: only alloc 8MB table size 445 erratum 24313: ignore memory access type 446 447 The fixes are in ITS initialization and basically ignore memory access 448 type and table size provided by the TYPER and BASER registers. 449 450 If unsure, say Y. 451 452config CAVIUM_ERRATUM_23144 453 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 454 depends on NUMA 455 default y 456 help 457 ITS SYNC command hang for cross node io and collections/cpu mapping. 458 459 If unsure, say Y. 460 461config CAVIUM_ERRATUM_23154 462 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 463 default y 464 help 465 The gicv3 of ThunderX requires a modified version for 466 reading the IAR status to ensure data synchronization 467 (access to icc_iar1_el1 is not sync'ed before and after). 468 469 If unsure, say Y. 470 471config CAVIUM_ERRATUM_27456 472 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 473 default y 474 help 475 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 476 instructions may cause the icache to become corrupted if it 477 contains data for a non-current ASID. The fix is to 478 invalidate the icache when changing the mm context. 479 480 If unsure, say Y. 481 482endmenu 483 484 485choice 486 prompt "Page size" 487 default ARM64_4K_PAGES 488 help 489 Page size (translation granule) configuration. 490 491config ARM64_4K_PAGES 492 bool "4KB" 493 help 494 This feature enables 4KB pages support. 495 496config ARM64_16K_PAGES 497 bool "16KB" 498 help 499 The system will use 16KB pages support. AArch32 emulation 500 requires applications compiled with 16K (or a multiple of 16K) 501 aligned segments. 502 503config ARM64_64K_PAGES 504 bool "64KB" 505 help 506 This feature enables 64KB pages support (4KB by default) 507 allowing only two levels of page tables and faster TLB 508 look-up. AArch32 emulation requires applications compiled 509 with 64K aligned segments. 510 511endchoice 512 513choice 514 prompt "Virtual address space size" 515 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 516 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 517 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 518 help 519 Allows choosing one of multiple possible virtual address 520 space sizes. The level of translation table is determined by 521 a combination of page size and virtual address space size. 522 523config ARM64_VA_BITS_36 524 bool "36-bit" if EXPERT 525 depends on ARM64_16K_PAGES 526 527config ARM64_VA_BITS_39 528 bool "39-bit" 529 depends on ARM64_4K_PAGES 530 531config ARM64_VA_BITS_42 532 bool "42-bit" 533 depends on ARM64_64K_PAGES 534 535config ARM64_VA_BITS_47 536 bool "47-bit" 537 depends on ARM64_16K_PAGES 538 539config ARM64_VA_BITS_48 540 bool "48-bit" 541 542endchoice 543 544config ARM64_VA_BITS 545 int 546 default 36 if ARM64_VA_BITS_36 547 default 39 if ARM64_VA_BITS_39 548 default 42 if ARM64_VA_BITS_42 549 default 47 if ARM64_VA_BITS_47 550 default 48 if ARM64_VA_BITS_48 551 552config CPU_BIG_ENDIAN 553 bool "Build big-endian kernel" 554 help 555 Say Y if you plan on running a kernel in big-endian mode. 556 557config SCHED_MC 558 bool "Multi-core scheduler support" 559 help 560 Multi-core scheduler support improves the CPU scheduler's decision 561 making when dealing with multi-core CPU chips at a cost of slightly 562 increased overhead in some places. If unsure say N here. 563 564config SCHED_SMT 565 bool "SMT scheduler support" 566 help 567 Improves the CPU scheduler's decision making when dealing with 568 MultiThreading at a cost of slightly increased overhead in some 569 places. If unsure say N here. 570 571config NR_CPUS 572 int "Maximum number of CPUs (2-4096)" 573 range 2 4096 574 # These have to remain sorted largest to smallest 575 default "64" 576 577config HOTPLUG_CPU 578 bool "Support for hot-pluggable CPUs" 579 select GENERIC_IRQ_MIGRATION 580 help 581 Say Y here to experiment with turning CPUs off and on. CPUs 582 can be controlled through /sys/devices/system/cpu. 583 584# Common NUMA Features 585config NUMA 586 bool "Numa Memory Allocation and Scheduler Support" 587 select ACPI_NUMA if ACPI 588 select OF_NUMA 589 help 590 Enable NUMA (Non Uniform Memory Access) support. 591 592 The kernel will try to allocate memory used by a CPU on the 593 local memory of the CPU and add some more 594 NUMA awareness to the kernel. 595 596config NODES_SHIFT 597 int "Maximum NUMA Nodes (as a power of 2)" 598 range 1 10 599 default "2" 600 depends on NEED_MULTIPLE_NODES 601 help 602 Specify the maximum number of NUMA Nodes available on the target 603 system. Increases memory reserved to accommodate various tables. 604 605config USE_PERCPU_NUMA_NODE_ID 606 def_bool y 607 depends on NUMA 608 609config HAVE_SETUP_PER_CPU_AREA 610 def_bool y 611 depends on NUMA 612 613config NEED_PER_CPU_EMBED_FIRST_CHUNK 614 def_bool y 615 depends on NUMA 616 617source kernel/Kconfig.preempt 618source kernel/Kconfig.hz 619 620config ARCH_SUPPORTS_DEBUG_PAGEALLOC 621 def_bool y 622 623config ARCH_HAS_HOLES_MEMORYMODEL 624 def_bool y if SPARSEMEM 625 626config ARCH_SPARSEMEM_ENABLE 627 def_bool y 628 select SPARSEMEM_VMEMMAP_ENABLE 629 630config ARCH_SPARSEMEM_DEFAULT 631 def_bool ARCH_SPARSEMEM_ENABLE 632 633config ARCH_SELECT_MEMORY_MODEL 634 def_bool ARCH_SPARSEMEM_ENABLE 635 636config HAVE_ARCH_PFN_VALID 637 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 638 639config HW_PERF_EVENTS 640 def_bool y 641 depends on ARM_PMU 642 643config SYS_SUPPORTS_HUGETLBFS 644 def_bool y 645 646config ARCH_WANT_HUGE_PMD_SHARE 647 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 648 649config ARCH_HAS_CACHE_LINE_SIZE 650 def_bool y 651 652source "mm/Kconfig" 653 654config SECCOMP 655 bool "Enable seccomp to safely compute untrusted bytecode" 656 ---help--- 657 This kernel feature is useful for number crunching applications 658 that may need to compute untrusted bytecode during their 659 execution. By using pipes or other transports made available to 660 the process as file descriptors supporting the read/write 661 syscalls, it's possible to isolate those applications in 662 their own address space using seccomp. Once seccomp is 663 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 664 and the task is only allowed to execute a few safe syscalls 665 defined by each seccomp mode. 666 667config PARAVIRT 668 bool "Enable paravirtualization code" 669 help 670 This changes the kernel so it can modify itself when it is run 671 under a hypervisor, potentially improving performance significantly 672 over full virtualization. 673 674config PARAVIRT_TIME_ACCOUNTING 675 bool "Paravirtual steal time accounting" 676 select PARAVIRT 677 default n 678 help 679 Select this option to enable fine granularity task steal time 680 accounting. Time spent executing other tasks in parallel with 681 the current vCPU is discounted from the vCPU power. To account for 682 that, there can be a small performance impact. 683 684 If in doubt, say N here. 685 686config KEXEC 687 depends on PM_SLEEP_SMP 688 select KEXEC_CORE 689 bool "kexec system call" 690 ---help--- 691 kexec is a system call that implements the ability to shutdown your 692 current kernel, and to start another kernel. It is like a reboot 693 but it is independent of the system firmware. And like a reboot 694 you can start any kernel with it, not just Linux. 695 696config XEN_DOM0 697 def_bool y 698 depends on XEN 699 700config XEN 701 bool "Xen guest support on ARM64" 702 depends on ARM64 && OF 703 select SWIOTLB_XEN 704 select PARAVIRT 705 help 706 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 707 708config FORCE_MAX_ZONEORDER 709 int 710 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 711 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 712 default "11" 713 help 714 The kernel memory allocator divides physically contiguous memory 715 blocks into "zones", where each zone is a power of two number of 716 pages. This option selects the largest power of two that the kernel 717 keeps in the memory allocator. If you need to allocate very large 718 blocks of physically contiguous memory, then you may need to 719 increase this value. 720 721 This config option is actually maximum order plus one. For example, 722 a value of 11 means that the largest free memory block is 2^10 pages. 723 724 We make sure that we can allocate upto a HugePage size for each configuration. 725 Hence we have : 726 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 727 728 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 729 4M allocations matching the default size used by generic code. 730 731menuconfig ARMV8_DEPRECATED 732 bool "Emulate deprecated/obsolete ARMv8 instructions" 733 depends on COMPAT 734 help 735 Legacy software support may require certain instructions 736 that have been deprecated or obsoleted in the architecture. 737 738 Enable this config to enable selective emulation of these 739 features. 740 741 If unsure, say Y 742 743if ARMV8_DEPRECATED 744 745config SWP_EMULATION 746 bool "Emulate SWP/SWPB instructions" 747 help 748 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 749 they are always undefined. Say Y here to enable software 750 emulation of these instructions for userspace using LDXR/STXR. 751 752 In some older versions of glibc [<=2.8] SWP is used during futex 753 trylock() operations with the assumption that the code will not 754 be preempted. This invalid assumption may be more likely to fail 755 with SWP emulation enabled, leading to deadlock of the user 756 application. 757 758 NOTE: when accessing uncached shared regions, LDXR/STXR rely 759 on an external transaction monitoring block called a global 760 monitor to maintain update atomicity. If your system does not 761 implement a global monitor, this option can cause programs that 762 perform SWP operations to uncached memory to deadlock. 763 764 If unsure, say Y 765 766config CP15_BARRIER_EMULATION 767 bool "Emulate CP15 Barrier instructions" 768 help 769 The CP15 barrier instructions - CP15ISB, CP15DSB, and 770 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 771 strongly recommended to use the ISB, DSB, and DMB 772 instructions instead. 773 774 Say Y here to enable software emulation of these 775 instructions for AArch32 userspace code. When this option is 776 enabled, CP15 barrier usage is traced which can help 777 identify software that needs updating. 778 779 If unsure, say Y 780 781config SETEND_EMULATION 782 bool "Emulate SETEND instruction" 783 help 784 The SETEND instruction alters the data-endianness of the 785 AArch32 EL0, and is deprecated in ARMv8. 786 787 Say Y here to enable software emulation of the instruction 788 for AArch32 userspace code. 789 790 Note: All the cpus on the system must have mixed endian support at EL0 791 for this feature to be enabled. If a new CPU - which doesn't support mixed 792 endian - is hotplugged in after this feature has been enabled, there could 793 be unexpected results in the applications. 794 795 If unsure, say Y 796endif 797 798config ARM64_SW_TTBR0_PAN 799 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 800 help 801 Enabling this option prevents the kernel from accessing 802 user-space memory directly by pointing TTBR0_EL1 to a reserved 803 zeroed area and reserved ASID. The user access routines 804 restore the valid TTBR0_EL1 temporarily. 805 806menu "ARMv8.1 architectural features" 807 808config ARM64_HW_AFDBM 809 bool "Support for hardware updates of the Access and Dirty page flags" 810 default y 811 help 812 The ARMv8.1 architecture extensions introduce support for 813 hardware updates of the access and dirty information in page 814 table entries. When enabled in TCR_EL1 (HA and HD bits) on 815 capable processors, accesses to pages with PTE_AF cleared will 816 set this bit instead of raising an access flag fault. 817 Similarly, writes to read-only pages with the DBM bit set will 818 clear the read-only bit (AP[2]) instead of raising a 819 permission fault. 820 821 Kernels built with this configuration option enabled continue 822 to work on pre-ARMv8.1 hardware and the performance impact is 823 minimal. If unsure, say Y. 824 825config ARM64_PAN 826 bool "Enable support for Privileged Access Never (PAN)" 827 default y 828 help 829 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 830 prevents the kernel or hypervisor from accessing user-space (EL0) 831 memory directly. 832 833 Choosing this option will cause any unprotected (not using 834 copy_to_user et al) memory access to fail with a permission fault. 835 836 The feature is detected at runtime, and will remain as a 'nop' 837 instruction if the cpu does not implement the feature. 838 839config ARM64_LSE_ATOMICS 840 bool "Atomic instructions" 841 help 842 As part of the Large System Extensions, ARMv8.1 introduces new 843 atomic instructions that are designed specifically to scale in 844 very large systems. 845 846 Say Y here to make use of these instructions for the in-kernel 847 atomic routines. This incurs a small overhead on CPUs that do 848 not support these instructions and requires the kernel to be 849 built with binutils >= 2.25. 850 851config ARM64_VHE 852 bool "Enable support for Virtualization Host Extensions (VHE)" 853 default y 854 help 855 Virtualization Host Extensions (VHE) allow the kernel to run 856 directly at EL2 (instead of EL1) on processors that support 857 it. This leads to better performance for KVM, as they reduce 858 the cost of the world switch. 859 860 Selecting this option allows the VHE feature to be detected 861 at runtime, and does not affect processors that do not 862 implement this feature. 863 864endmenu 865 866menu "ARMv8.2 architectural features" 867 868config ARM64_UAO 869 bool "Enable support for User Access Override (UAO)" 870 default y 871 help 872 User Access Override (UAO; part of the ARMv8.2 Extensions) 873 causes the 'unprivileged' variant of the load/store instructions to 874 be overriden to be privileged. 875 876 This option changes get_user() and friends to use the 'unprivileged' 877 variant of the load/store instructions. This ensures that user-space 878 really did have access to the supplied memory. When addr_limit is 879 set to kernel memory the UAO bit will be set, allowing privileged 880 access to kernel memory. 881 882 Choosing this option will cause copy_to_user() et al to use user-space 883 memory permissions. 884 885 The feature is detected at runtime, the kernel will use the 886 regular load/store instructions if the cpu does not implement the 887 feature. 888 889endmenu 890 891config ARM64_MODULE_CMODEL_LARGE 892 bool 893 894config ARM64_MODULE_PLTS 895 bool 896 select ARM64_MODULE_CMODEL_LARGE 897 select HAVE_MOD_ARCH_SPECIFIC 898 899config RELOCATABLE 900 bool 901 help 902 This builds the kernel as a Position Independent Executable (PIE), 903 which retains all relocation metadata required to relocate the 904 kernel binary at runtime to a different virtual address than the 905 address it was linked at. 906 Since AArch64 uses the RELA relocation format, this requires a 907 relocation pass at runtime even if the kernel is loaded at the 908 same address it was linked at. 909 910config RANDOMIZE_BASE 911 bool "Randomize the address of the kernel image" 912 select ARM64_MODULE_PLTS if MODULES 913 select RELOCATABLE 914 help 915 Randomizes the virtual address at which the kernel image is 916 loaded, as a security feature that deters exploit attempts 917 relying on knowledge of the location of kernel internals. 918 919 It is the bootloader's job to provide entropy, by passing a 920 random u64 value in /chosen/kaslr-seed at kernel entry. 921 922 When booting via the UEFI stub, it will invoke the firmware's 923 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 924 to the kernel proper. In addition, it will randomise the physical 925 location of the kernel Image as well. 926 927 If unsure, say N. 928 929config RANDOMIZE_MODULE_REGION_FULL 930 bool "Randomize the module region independently from the core kernel" 931 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE 932 default y 933 help 934 Randomizes the location of the module region without considering the 935 location of the core kernel. This way, it is impossible for modules 936 to leak information about the location of core kernel data structures 937 but it does imply that function calls between modules and the core 938 kernel will need to be resolved via veneers in the module PLT. 939 940 When this option is not set, the module region will be randomized over 941 a limited range that contains the [_stext, _etext] interval of the 942 core kernel, so branch relocations are always in range. 943 944endmenu 945 946menu "Boot options" 947 948config ARM64_ACPI_PARKING_PROTOCOL 949 bool "Enable support for the ARM64 ACPI parking protocol" 950 depends on ACPI 951 help 952 Enable support for the ARM64 ACPI parking protocol. If disabled 953 the kernel will not allow booting through the ARM64 ACPI parking 954 protocol even if the corresponding data is present in the ACPI 955 MADT table. 956 957config CMDLINE 958 string "Default kernel command string" 959 default "" 960 help 961 Provide a set of default command-line options at build time by 962 entering them here. As a minimum, you should specify the the 963 root device (e.g. root=/dev/nfs). 964 965config CMDLINE_FORCE 966 bool "Always use the default kernel command string" 967 help 968 Always use the default kernel command string, even if the boot 969 loader passes other arguments to the kernel. 970 This is useful if you cannot or don't want to change the 971 command-line options your boot loader passes to the kernel. 972 973config EFI_STUB 974 bool 975 976config EFI 977 bool "UEFI runtime support" 978 depends on OF && !CPU_BIG_ENDIAN 979 select LIBFDT 980 select UCS2_STRING 981 select EFI_PARAMS_FROM_FDT 982 select EFI_RUNTIME_WRAPPERS 983 select EFI_STUB 984 select EFI_ARMSTUB 985 default y 986 help 987 This option provides support for runtime services provided 988 by UEFI firmware (such as non-volatile variables, realtime 989 clock, and platform reset). A UEFI stub is also provided to 990 allow the kernel to be booted as an EFI application. This 991 is only useful on systems that have UEFI firmware. 992 993config DMI 994 bool "Enable support for SMBIOS (DMI) tables" 995 depends on EFI 996 default y 997 help 998 This enables SMBIOS/DMI feature for systems. 999 1000 This option is only useful on systems that have UEFI firmware. 1001 However, even with this option, the resultant kernel should 1002 continue to boot on existing non-UEFI platforms. 1003 1004endmenu 1005 1006menu "Userspace binary formats" 1007 1008source "fs/Kconfig.binfmt" 1009 1010config COMPAT 1011 bool "Kernel support for 32-bit EL0" 1012 depends on ARM64_4K_PAGES || EXPERT 1013 select COMPAT_BINFMT_ELF 1014 select HAVE_UID16 1015 select OLD_SIGSUSPEND3 1016 select COMPAT_OLD_SIGACTION 1017 help 1018 This option enables support for a 32-bit EL0 running under a 64-bit 1019 kernel at EL1. AArch32-specific components such as system calls, 1020 the user helper functions, VFP support and the ptrace interface are 1021 handled appropriately by the kernel. 1022 1023 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1024 that you will only be able to execute AArch32 binaries that were compiled 1025 with page size aligned segments. 1026 1027 If you want to execute 32-bit userspace applications, say Y. 1028 1029config SYSVIPC_COMPAT 1030 def_bool y 1031 depends on COMPAT && SYSVIPC 1032 1033endmenu 1034 1035menu "Power management options" 1036 1037source "kernel/power/Kconfig" 1038 1039config ARCH_HIBERNATION_POSSIBLE 1040 def_bool y 1041 depends on CPU_PM 1042 1043config ARCH_HIBERNATION_HEADER 1044 def_bool y 1045 depends on HIBERNATION 1046 1047config ARCH_SUSPEND_POSSIBLE 1048 def_bool y 1049 1050endmenu 1051 1052menu "CPU Power Management" 1053 1054source "drivers/cpuidle/Kconfig" 1055 1056source "drivers/cpufreq/Kconfig" 1057 1058endmenu 1059 1060source "net/Kconfig" 1061 1062source "drivers/Kconfig" 1063 1064source "drivers/firmware/Kconfig" 1065 1066source "drivers/acpi/Kconfig" 1067 1068source "fs/Kconfig" 1069 1070source "arch/arm64/kvm/Kconfig" 1071 1072source "arch/arm64/Kconfig.debug" 1073 1074source "security/Kconfig" 1075 1076source "crypto/Kconfig" 1077if CRYPTO 1078source "arch/arm64/crypto/Kconfig" 1079endif 1080 1081source "lib/Kconfig" 1082