xref: /openbmc/linux/arch/arm64/Kconfig (revision a5575df5)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_CCA_REQUIRED if ACPI
5	select ACPI_GENERIC_GSI if ACPI
6	select ACPI_GTDT if ACPI
7	select ACPI_IORT if ACPI
8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9	select ACPI_MCFG if (ACPI && PCI)
10	select ACPI_SPCR_TABLE if ACPI
11	select ACPI_PPTT if ACPI
12	select ARCH_HAS_DEBUG_WX
13	select ARCH_BINFMT_ELF_STATE
14	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
15	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
16	select ARCH_ENABLE_MEMORY_HOTPLUG
17	select ARCH_ENABLE_MEMORY_HOTREMOVE
18	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
19	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
20	select ARCH_HAS_CACHE_LINE_SIZE
21	select ARCH_HAS_DEBUG_VIRTUAL
22	select ARCH_HAS_DEBUG_VM_PGTABLE
23	select ARCH_HAS_DMA_PREP_COHERENT
24	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
25	select ARCH_HAS_FAST_MULTIPLIER
26	select ARCH_HAS_FORTIFY_SOURCE
27	select ARCH_HAS_GCOV_PROFILE_ALL
28	select ARCH_HAS_GIGANTIC_PAGE
29	select ARCH_HAS_KCOV
30	select ARCH_HAS_KEEPINITRD
31	select ARCH_HAS_MEMBARRIER_SYNC_CORE
32	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
33	select ARCH_HAS_PTE_DEVMAP
34	select ARCH_HAS_PTE_SPECIAL
35	select ARCH_HAS_SETUP_DMA_OPS
36	select ARCH_HAS_SET_DIRECT_MAP
37	select ARCH_HAS_SET_MEMORY
38	select ARCH_STACKWALK
39	select ARCH_HAS_STRICT_KERNEL_RWX
40	select ARCH_HAS_STRICT_MODULE_RWX
41	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
42	select ARCH_HAS_SYNC_DMA_FOR_CPU
43	select ARCH_HAS_SYSCALL_WRAPPER
44	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
45	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
46	select ARCH_HAS_ZONE_DMA_SET if EXPERT
47	select ARCH_HAVE_ELF_PROT
48	select ARCH_HAVE_NMI_SAFE_CMPXCHG
49	select ARCH_INLINE_READ_LOCK if !PREEMPTION
50	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
51	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
52	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
53	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
54	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
55	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
56	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
57	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
58	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
59	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
60	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
61	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
62	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
63	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
64	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
65	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
66	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
67	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
68	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
69	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
70	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
71	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
72	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
73	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
74	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
75	select ARCH_KEEP_MEMBLOCK
76	select ARCH_USE_CMPXCHG_LOCKREF
77	select ARCH_USE_GNU_PROPERTY
78	select ARCH_USE_MEMTEST
79	select ARCH_USE_QUEUED_RWLOCKS
80	select ARCH_USE_QUEUED_SPINLOCKS
81	select ARCH_USE_SYM_ANNOTATIONS
82	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
83	select ARCH_SUPPORTS_HUGETLBFS
84	select ARCH_SUPPORTS_MEMORY_FAILURE
85	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
86	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
87	select ARCH_SUPPORTS_LTO_CLANG_THIN
88	select ARCH_SUPPORTS_CFI_CLANG
89	select ARCH_SUPPORTS_ATOMIC_RMW
90	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
91	select ARCH_SUPPORTS_NUMA_BALANCING
92	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
93	select ARCH_WANT_DEFAULT_BPF_JIT
94	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
95	select ARCH_WANT_FRAME_POINTERS
96	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
97	select ARCH_WANT_LD_ORPHAN_WARN
98	select ARCH_WANTS_NO_INSTR
99	select ARCH_HAS_UBSAN_SANITIZE_ALL
100	select ARM_AMBA
101	select ARM_ARCH_TIMER
102	select ARM_GIC
103	select AUDIT_ARCH_COMPAT_GENERIC
104	select ARM_GIC_V2M if PCI
105	select ARM_GIC_V3
106	select ARM_GIC_V3_ITS if PCI
107	select ARM_PSCI_FW
108	select BUILDTIME_TABLE_SORT
109	select CLONE_BACKWARDS
110	select COMMON_CLK
111	select CPU_PM if (SUSPEND || CPU_IDLE)
112	select CRC32
113	select DCACHE_WORD_ACCESS
114	select DMA_DIRECT_REMAP
115	select EDAC_SUPPORT
116	select FRAME_POINTER
117	select GENERIC_ALLOCATOR
118	select GENERIC_ARCH_TOPOLOGY
119	select GENERIC_CLOCKEVENTS_BROADCAST
120	select GENERIC_CPU_AUTOPROBE
121	select GENERIC_CPU_VULNERABILITIES
122	select GENERIC_EARLY_IOREMAP
123	select GENERIC_IDLE_POLL_SETUP
124	select GENERIC_IRQ_IPI
125	select GENERIC_IRQ_PROBE
126	select GENERIC_IRQ_SHOW
127	select GENERIC_IRQ_SHOW_LEVEL
128	select GENERIC_LIB_DEVMEM_IS_ALLOWED
129	select GENERIC_PCI_IOMAP
130	select GENERIC_PTDUMP
131	select GENERIC_SCHED_CLOCK
132	select GENERIC_SMP_IDLE_THREAD
133	select GENERIC_TIME_VSYSCALL
134	select GENERIC_GETTIMEOFDAY
135	select GENERIC_VDSO_TIME_NS
136	select HARDIRQS_SW_RESEND
137	select HAVE_MOVE_PMD
138	select HAVE_MOVE_PUD
139	select HAVE_PCI
140	select HAVE_ACPI_APEI if (ACPI && EFI)
141	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
142	select HAVE_ARCH_AUDITSYSCALL
143	select HAVE_ARCH_BITREVERSE
144	select HAVE_ARCH_COMPILER_H
145	select HAVE_ARCH_HUGE_VMAP
146	select HAVE_ARCH_JUMP_LABEL
147	select HAVE_ARCH_JUMP_LABEL_RELATIVE
148	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
149	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
150	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
151	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
152	# Some instrumentation may be unsound, hence EXPERT
153	select HAVE_ARCH_KCSAN if EXPERT
154	select HAVE_ARCH_KFENCE
155	select HAVE_ARCH_KGDB
156	select HAVE_ARCH_MMAP_RND_BITS
157	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
158	select HAVE_ARCH_PREL32_RELOCATIONS
159	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
160	select HAVE_ARCH_SECCOMP_FILTER
161	select HAVE_ARCH_STACKLEAK
162	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
163	select HAVE_ARCH_TRACEHOOK
164	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
165	select HAVE_ARCH_VMAP_STACK
166	select HAVE_ARM_SMCCC
167	select HAVE_ASM_MODVERSIONS
168	select HAVE_EBPF_JIT
169	select HAVE_C_RECORDMCOUNT
170	select HAVE_CMPXCHG_DOUBLE
171	select HAVE_CMPXCHG_LOCAL
172	select HAVE_CONTEXT_TRACKING
173	select HAVE_DEBUG_KMEMLEAK
174	select HAVE_DMA_CONTIGUOUS
175	select HAVE_DYNAMIC_FTRACE
176	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
177		if $(cc-option,-fpatchable-function-entry=2)
178	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
179		if DYNAMIC_FTRACE_WITH_REGS
180	select HAVE_EFFICIENT_UNALIGNED_ACCESS
181	select HAVE_FAST_GUP
182	select HAVE_FTRACE_MCOUNT_RECORD
183	select HAVE_FUNCTION_TRACER
184	select HAVE_FUNCTION_ERROR_INJECTION
185	select HAVE_FUNCTION_GRAPH_TRACER
186	select HAVE_GCC_PLUGINS
187	select HAVE_HW_BREAKPOINT if PERF_EVENTS
188	select HAVE_IRQ_TIME_ACCOUNTING
189	select HAVE_KVM
190	select HAVE_NMI
191	select HAVE_PATA_PLATFORM
192	select HAVE_PERF_EVENTS
193	select HAVE_PERF_REGS
194	select HAVE_PERF_USER_STACK_DUMP
195	select HAVE_REGS_AND_STACK_ACCESS_API
196	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
197	select HAVE_FUNCTION_ARG_ACCESS_API
198	select MMU_GATHER_RCU_TABLE_FREE
199	select HAVE_RSEQ
200	select HAVE_STACKPROTECTOR
201	select HAVE_SYSCALL_TRACEPOINTS
202	select HAVE_KPROBES
203	select HAVE_KRETPROBES
204	select HAVE_GENERIC_VDSO
205	select IOMMU_DMA if IOMMU_SUPPORT
206	select IRQ_DOMAIN
207	select IRQ_FORCED_THREADING
208	select KASAN_VMALLOC if KASAN_GENERIC
209	select MODULES_USE_ELF_RELA
210	select NEED_DMA_MAP_STATE
211	select NEED_SG_DMA_LENGTH
212	select OF
213	select OF_EARLY_FLATTREE
214	select PCI_DOMAINS_GENERIC if PCI
215	select PCI_ECAM if (ACPI && PCI)
216	select PCI_SYSCALL if PCI
217	select POWER_RESET
218	select POWER_SUPPLY
219	select SPARSE_IRQ
220	select SWIOTLB
221	select SYSCTL_EXCEPTION_TRACE
222	select THREAD_INFO_IN_TASK
223	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
224	select TRACE_IRQFLAGS_SUPPORT
225	help
226	  ARM 64-bit (AArch64) Linux support.
227
228config 64BIT
229	def_bool y
230
231config MMU
232	def_bool y
233
234config ARM64_PAGE_SHIFT
235	int
236	default 16 if ARM64_64K_PAGES
237	default 14 if ARM64_16K_PAGES
238	default 12
239
240config ARM64_CONT_PTE_SHIFT
241	int
242	default 5 if ARM64_64K_PAGES
243	default 7 if ARM64_16K_PAGES
244	default 4
245
246config ARM64_CONT_PMD_SHIFT
247	int
248	default 5 if ARM64_64K_PAGES
249	default 5 if ARM64_16K_PAGES
250	default 4
251
252config ARCH_MMAP_RND_BITS_MIN
253       default 14 if ARM64_64K_PAGES
254       default 16 if ARM64_16K_PAGES
255       default 18
256
257# max bits determined by the following formula:
258#  VA_BITS - PAGE_SHIFT - 3
259config ARCH_MMAP_RND_BITS_MAX
260       default 19 if ARM64_VA_BITS=36
261       default 24 if ARM64_VA_BITS=39
262       default 27 if ARM64_VA_BITS=42
263       default 30 if ARM64_VA_BITS=47
264       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
265       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
266       default 33 if ARM64_VA_BITS=48
267       default 14 if ARM64_64K_PAGES
268       default 16 if ARM64_16K_PAGES
269       default 18
270
271config ARCH_MMAP_RND_COMPAT_BITS_MIN
272       default 7 if ARM64_64K_PAGES
273       default 9 if ARM64_16K_PAGES
274       default 11
275
276config ARCH_MMAP_RND_COMPAT_BITS_MAX
277       default 16
278
279config NO_IOPORT_MAP
280	def_bool y if !PCI
281
282config STACKTRACE_SUPPORT
283	def_bool y
284
285config ILLEGAL_POINTER_VALUE
286	hex
287	default 0xdead000000000000
288
289config LOCKDEP_SUPPORT
290	def_bool y
291
292config GENERIC_BUG
293	def_bool y
294	depends on BUG
295
296config GENERIC_BUG_RELATIVE_POINTERS
297	def_bool y
298	depends on GENERIC_BUG
299
300config GENERIC_HWEIGHT
301	def_bool y
302
303config GENERIC_CSUM
304        def_bool y
305
306config GENERIC_CALIBRATE_DELAY
307	def_bool y
308
309config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
310	def_bool y
311
312config SMP
313	def_bool y
314
315config KERNEL_MODE_NEON
316	def_bool y
317
318config FIX_EARLYCON_MEM
319	def_bool y
320
321config PGTABLE_LEVELS
322	int
323	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
324	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
325	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
326	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
327	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
328	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329
330config ARCH_SUPPORTS_UPROBES
331	def_bool y
332
333config ARCH_PROC_KCORE_TEXT
334	def_bool y
335
336config BROKEN_GAS_INST
337	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338
339config KASAN_SHADOW_OFFSET
340	hex
341	depends on KASAN_GENERIC || KASAN_SW_TAGS
342	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
343	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
344	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
345	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
346	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
347	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
348	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
349	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
350	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
351	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
352	default 0xffffffffffffffff
353
354source "arch/arm64/Kconfig.platforms"
355
356menu "Kernel Features"
357
358menu "ARM errata workarounds via the alternatives framework"
359
360config ARM64_WORKAROUND_CLEAN_CACHE
361	bool
362
363config ARM64_ERRATUM_826319
364	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365	default y
366	select ARM64_WORKAROUND_CLEAN_CACHE
367	help
368	  This option adds an alternative code sequence to work around ARM
369	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
370	  AXI master interface and an L2 cache.
371
372	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
373	  and is unable to accept a certain write via this interface, it will
374	  not progress on read data presented on the read data channel and the
375	  system can deadlock.
376
377	  The workaround promotes data cache clean instructions to
378	  data cache clean-and-invalidate.
379	  Please note that this does not necessarily enable the workaround,
380	  as it depends on the alternative framework, which will only patch
381	  the kernel if an affected CPU is detected.
382
383	  If unsure, say Y.
384
385config ARM64_ERRATUM_827319
386	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387	default y
388	select ARM64_WORKAROUND_CLEAN_CACHE
389	help
390	  This option adds an alternative code sequence to work around ARM
391	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
392	  master interface and an L2 cache.
393
394	  Under certain conditions this erratum can cause a clean line eviction
395	  to occur at the same time as another transaction to the same address
396	  on the AMBA 5 CHI interface, which can cause data corruption if the
397	  interconnect reorders the two transactions.
398
399	  The workaround promotes data cache clean instructions to
400	  data cache clean-and-invalidate.
401	  Please note that this does not necessarily enable the workaround,
402	  as it depends on the alternative framework, which will only patch
403	  the kernel if an affected CPU is detected.
404
405	  If unsure, say Y.
406
407config ARM64_ERRATUM_824069
408	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409	default y
410	select ARM64_WORKAROUND_CLEAN_CACHE
411	help
412	  This option adds an alternative code sequence to work around ARM
413	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
414	  to a coherent interconnect.
415
416	  If a Cortex-A53 processor is executing a store or prefetch for
417	  write instruction at the same time as a processor in another
418	  cluster is executing a cache maintenance operation to the same
419	  address, then this erratum might cause a clean cache line to be
420	  incorrectly marked as dirty.
421
422	  The workaround promotes data cache clean instructions to
423	  data cache clean-and-invalidate.
424	  Please note that this option does not necessarily enable the
425	  workaround, as it depends on the alternative framework, which will
426	  only patch the kernel if an affected CPU is detected.
427
428	  If unsure, say Y.
429
430config ARM64_ERRATUM_819472
431	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432	default y
433	select ARM64_WORKAROUND_CLEAN_CACHE
434	help
435	  This option adds an alternative code sequence to work around ARM
436	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
437	  present when it is connected to a coherent interconnect.
438
439	  If the processor is executing a load and store exclusive sequence at
440	  the same time as a processor in another cluster is executing a cache
441	  maintenance operation to the same address, then this erratum might
442	  cause data corruption.
443
444	  The workaround promotes data cache clean instructions to
445	  data cache clean-and-invalidate.
446	  Please note that this does not necessarily enable the workaround,
447	  as it depends on the alternative framework, which will only patch
448	  the kernel if an affected CPU is detected.
449
450	  If unsure, say Y.
451
452config ARM64_ERRATUM_832075
453	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
454	default y
455	help
456	  This option adds an alternative code sequence to work around ARM
457	  erratum 832075 on Cortex-A57 parts up to r1p2.
458
459	  Affected Cortex-A57 parts might deadlock when exclusive load/store
460	  instructions to Write-Back memory are mixed with Device loads.
461
462	  The workaround is to promote device loads to use Load-Acquire
463	  semantics.
464	  Please note that this does not necessarily enable the workaround,
465	  as it depends on the alternative framework, which will only patch
466	  the kernel if an affected CPU is detected.
467
468	  If unsure, say Y.
469
470config ARM64_ERRATUM_834220
471	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
472	depends on KVM
473	default y
474	help
475	  This option adds an alternative code sequence to work around ARM
476	  erratum 834220 on Cortex-A57 parts up to r1p2.
477
478	  Affected Cortex-A57 parts might report a Stage 2 translation
479	  fault as the result of a Stage 1 fault for load crossing a
480	  page boundary when there is a permission or device memory
481	  alignment fault at Stage 1 and a translation fault at Stage 2.
482
483	  The workaround is to verify that the Stage 1 translation
484	  doesn't generate a fault before handling the Stage 2 fault.
485	  Please note that this does not necessarily enable the workaround,
486	  as it depends on the alternative framework, which will only patch
487	  the kernel if an affected CPU is detected.
488
489	  If unsure, say Y.
490
491config ARM64_ERRATUM_845719
492	bool "Cortex-A53: 845719: a load might read incorrect data"
493	depends on COMPAT
494	default y
495	help
496	  This option adds an alternative code sequence to work around ARM
497	  erratum 845719 on Cortex-A53 parts up to r0p4.
498
499	  When running a compat (AArch32) userspace on an affected Cortex-A53
500	  part, a load at EL0 from a virtual address that matches the bottom 32
501	  bits of the virtual address used by a recent load at (AArch64) EL1
502	  might return incorrect data.
503
504	  The workaround is to write the contextidr_el1 register on exception
505	  return to a 32-bit task.
506	  Please note that this does not necessarily enable the workaround,
507	  as it depends on the alternative framework, which will only patch
508	  the kernel if an affected CPU is detected.
509
510	  If unsure, say Y.
511
512config ARM64_ERRATUM_843419
513	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
514	default y
515	select ARM64_MODULE_PLTS if MODULES
516	help
517	  This option links the kernel with '--fix-cortex-a53-843419' and
518	  enables PLT support to replace certain ADRP instructions, which can
519	  cause subsequent memory accesses to use an incorrect address on
520	  Cortex-A53 parts up to r0p4.
521
522	  If unsure, say Y.
523
524config ARM64_LD_HAS_FIX_ERRATUM_843419
525	def_bool $(ld-option,--fix-cortex-a53-843419)
526
527config ARM64_ERRATUM_1024718
528	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
529	default y
530	help
531	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
532
533	  Affected Cortex-A55 cores (all revisions) could cause incorrect
534	  update of the hardware dirty bit when the DBM/AP bits are updated
535	  without a break-before-make. The workaround is to disable the usage
536	  of hardware DBM locally on the affected cores. CPUs not affected by
537	  this erratum will continue to use the feature.
538
539	  If unsure, say Y.
540
541config ARM64_ERRATUM_1418040
542	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
543	default y
544	depends on COMPAT
545	help
546	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
547	  errata 1188873 and 1418040.
548
549	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
550	  cause register corruption when accessing the timer registers
551	  from AArch32 userspace.
552
553	  If unsure, say Y.
554
555config ARM64_WORKAROUND_SPECULATIVE_AT
556	bool
557
558config ARM64_ERRATUM_1165522
559	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
560	default y
561	select ARM64_WORKAROUND_SPECULATIVE_AT
562	help
563	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
564
565	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
566	  corrupted TLBs by speculating an AT instruction during a guest
567	  context switch.
568
569	  If unsure, say Y.
570
571config ARM64_ERRATUM_1319367
572	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573	default y
574	select ARM64_WORKAROUND_SPECULATIVE_AT
575	help
576	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
577	  and A72 erratum 1319367
578
579	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
580	  speculating an AT instruction during a guest context switch.
581
582	  If unsure, say Y.
583
584config ARM64_ERRATUM_1530923
585	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586	default y
587	select ARM64_WORKAROUND_SPECULATIVE_AT
588	help
589	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590
591	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
592	  corrupted TLBs by speculating an AT instruction during a guest
593	  context switch.
594
595	  If unsure, say Y.
596
597config ARM64_WORKAROUND_REPEAT_TLBI
598	bool
599
600config ARM64_ERRATUM_1286807
601	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
602	default y
603	select ARM64_WORKAROUND_REPEAT_TLBI
604	help
605	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
606
607	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
608	  address for a cacheable mapping of a location is being
609	  accessed by a core while another core is remapping the virtual
610	  address to a new physical page using the recommended
611	  break-before-make sequence, then under very rare circumstances
612	  TLBI+DSB completes before a read using the translation being
613	  invalidated has been observed by other observers. The
614	  workaround repeats the TLBI+DSB operation.
615
616config ARM64_ERRATUM_1463225
617	bool "Cortex-A76: Software Step might prevent interrupt recognition"
618	default y
619	help
620	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
621
622	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
623	  of a system call instruction (SVC) can prevent recognition of
624	  subsequent interrupts when software stepping is disabled in the
625	  exception handler of the system call and either kernel debugging
626	  is enabled or VHE is in use.
627
628	  Work around the erratum by triggering a dummy step exception
629	  when handling a system call from a task that is being stepped
630	  in a VHE configuration of the kernel.
631
632	  If unsure, say Y.
633
634config ARM64_ERRATUM_1542419
635	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
636	default y
637	help
638	  This option adds a workaround for ARM Neoverse-N1 erratum
639	  1542419.
640
641	  Affected Neoverse-N1 cores could execute a stale instruction when
642	  modified by another CPU. The workaround depends on a firmware
643	  counterpart.
644
645	  Workaround the issue by hiding the DIC feature from EL0. This
646	  forces user-space to perform cache maintenance.
647
648	  If unsure, say Y.
649
650config ARM64_ERRATUM_1508412
651	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
652	default y
653	help
654	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
655
656	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
657	  of a store-exclusive or read of PAR_EL1 and a load with device or
658	  non-cacheable memory attributes. The workaround depends on a firmware
659	  counterpart.
660
661	  KVM guests must also have the workaround implemented or they can
662	  deadlock the system.
663
664	  Work around the issue by inserting DMB SY barriers around PAR_EL1
665	  register reads and warning KVM users. The DMB barrier is sufficient
666	  to prevent a speculative PAR_EL1 read.
667
668	  If unsure, say Y.
669
670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
671	bool
672
673config ARM64_ERRATUM_2051678
674	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
675	default y
676	help
677	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
678	  Affected Coretex-A510 might not respect the ordering rules for
679	  hardware update of the page table's dirty bit. The workaround
680	  is to not enable the feature on affected CPUs.
681
682	  If unsure, say Y.
683
684config ARM64_ERRATUM_2077057
685	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
686	help
687	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.
688	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
689	  expected, but a Pointer Authentication trap is taken instead. The
690	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
691	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
692
693	  This can only happen when EL2 is stepping EL1.
694
695	  When these conditions occur, the SPSR_EL2 value is unchanged from the
696	  previous guest entry, and can be restored from the in-memory copy.
697
698	  If unsure, say Y.
699
700config ARM64_ERRATUM_2119858
701	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
702	default y
703	depends on CORESIGHT_TRBE
704	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
705	help
706	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
707
708	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
709	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
710	  the event of a WRAP event.
711
712	  Work around the issue by always making sure we move the TRBPTR_EL1 by
713	  256 bytes before enabling the buffer and filling the first 256 bytes of
714	  the buffer with ETM ignore packets upon disabling.
715
716	  If unsure, say Y.
717
718config ARM64_ERRATUM_2139208
719	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
720	default y
721	depends on CORESIGHT_TRBE
722	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
723	help
724	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
725
726	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
727	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
728	  the event of a WRAP event.
729
730	  Work around the issue by always making sure we move the TRBPTR_EL1 by
731	  256 bytes before enabling the buffer and filling the first 256 bytes of
732	  the buffer with ETM ignore packets upon disabling.
733
734	  If unsure, say Y.
735
736config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
737	bool
738
739config ARM64_ERRATUM_2054223
740	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
741	default y
742	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
743	help
744	  Enable workaround for ARM Cortex-A710 erratum 2054223
745
746	  Affected cores may fail to flush the trace data on a TSB instruction, when
747	  the PE is in trace prohibited state. This will cause losing a few bytes
748	  of the trace cached.
749
750	  Workaround is to issue two TSB consecutively on affected cores.
751
752	  If unsure, say Y.
753
754config ARM64_ERRATUM_2067961
755	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
756	default y
757	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
758	help
759	  Enable workaround for ARM Neoverse-N2 erratum 2067961
760
761	  Affected cores may fail to flush the trace data on a TSB instruction, when
762	  the PE is in trace prohibited state. This will cause losing a few bytes
763	  of the trace cached.
764
765	  Workaround is to issue two TSB consecutively on affected cores.
766
767	  If unsure, say Y.
768
769config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
770	bool
771
772config ARM64_ERRATUM_2253138
773	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
774	depends on CORESIGHT_TRBE
775	default y
776	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
777	help
778	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
779
780	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
781	  for TRBE. Under some conditions, the TRBE might generate a write to the next
782	  virtually addressed page following the last page of the TRBE address space
783	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
784
785	  Work around this in the driver by always making sure that there is a
786	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
787
788	  If unsure, say Y.
789
790config ARM64_ERRATUM_2224489
791	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
792	depends on CORESIGHT_TRBE
793	default y
794	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
795	help
796	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
797
798	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
799	  for TRBE. Under some conditions, the TRBE might generate a write to the next
800	  virtually addressed page following the last page of the TRBE address space
801	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
802
803	  Work around this in the driver by always making sure that there is a
804	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
805
806	  If unsure, say Y.
807
808config ARM64_ERRATUM_2064142
809	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
810	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
811	default y
812	help
813	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
814
815	  Affected Cortex-A510 core might fail to write into system registers after the
816	  TRBE has been disabled. Under some conditions after the TRBE has been disabled
817	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
818	  and TRBTRG_EL1 will be ignored and will not be effected.
819
820	  Work around this in the driver by executing TSB CSYNC and DSB after collection
821	  is stopped and before performing a system register write to one of the affected
822	  registers.
823
824	  If unsure, say Y.
825
826config ARM64_ERRATUM_2038923
827	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
828	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
829	default y
830	help
831	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
832
833	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
834	  prohibited within the CPU. As a result, the trace buffer or trace buffer state
835	  might be corrupted. This happens after TRBE buffer has been enabled by setting
836	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before
837	  execution changes from a context, in which trace is prohibited to one where it
838	  isn't, or vice versa. In these mentioned conditions, the view of whether trace
839	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or
840	  the trace buffer state might be corrupted.
841
842	  Work around this in the driver by preventing an inconsistent view of whether the
843	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
844	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
845	  two ISB instructions if no ERET is to take place.
846
847	  If unsure, say Y.
848
849config ARM64_ERRATUM_1902691
850	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
851	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
852	default y
853	help
854	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
855
856	  Affected Cortex-A510 core might cause trace data corruption, when being written
857	  into the memory. Effectively TRBE is broken and hence cannot be used to capture
858	  trace data.
859
860	  Work around this problem in the driver by just preventing TRBE initialization on
861	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
862	  on such implementations. This will cover the kernel for any firmware that doesn't
863	  do this already.
864
865	  If unsure, say Y.
866
867config CAVIUM_ERRATUM_22375
868	bool "Cavium erratum 22375, 24313"
869	default y
870	help
871	  Enable workaround for errata 22375 and 24313.
872
873	  This implements two gicv3-its errata workarounds for ThunderX. Both
874	  with a small impact affecting only ITS table allocation.
875
876	    erratum 22375: only alloc 8MB table size
877	    erratum 24313: ignore memory access type
878
879	  The fixes are in ITS initialization and basically ignore memory access
880	  type and table size provided by the TYPER and BASER registers.
881
882	  If unsure, say Y.
883
884config CAVIUM_ERRATUM_23144
885	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
886	depends on NUMA
887	default y
888	help
889	  ITS SYNC command hang for cross node io and collections/cpu mapping.
890
891	  If unsure, say Y.
892
893config CAVIUM_ERRATUM_23154
894	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
895	default y
896	help
897	  The gicv3 of ThunderX requires a modified version for
898	  reading the IAR status to ensure data synchronization
899	  (access to icc_iar1_el1 is not sync'ed before and after).
900
901	  If unsure, say Y.
902
903config CAVIUM_ERRATUM_27456
904	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
905	default y
906	help
907	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
908	  instructions may cause the icache to become corrupted if it
909	  contains data for a non-current ASID.  The fix is to
910	  invalidate the icache when changing the mm context.
911
912	  If unsure, say Y.
913
914config CAVIUM_ERRATUM_30115
915	bool "Cavium erratum 30115: Guest may disable interrupts in host"
916	default y
917	help
918	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
919	  1.2, and T83 Pass 1.0, KVM guest execution may disable
920	  interrupts in host. Trapping both GICv3 group-0 and group-1
921	  accesses sidesteps the issue.
922
923	  If unsure, say Y.
924
925config CAVIUM_TX2_ERRATUM_219
926	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
927	default y
928	help
929	  On Cavium ThunderX2, a load, store or prefetch instruction between a
930	  TTBR update and the corresponding context synchronizing operation can
931	  cause a spurious Data Abort to be delivered to any hardware thread in
932	  the CPU core.
933
934	  Work around the issue by avoiding the problematic code sequence and
935	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
936	  trap handler performs the corresponding register access, skips the
937	  instruction and ensures context synchronization by virtue of the
938	  exception return.
939
940	  If unsure, say Y.
941
942config FUJITSU_ERRATUM_010001
943	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
944	default y
945	help
946	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
947	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
948	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
949	  This fault occurs under a specific hardware condition when a
950	  load/store instruction performs an address translation using:
951	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
952	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
953	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
954	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
955
956	  The workaround is to ensure these bits are clear in TCR_ELx.
957	  The workaround only affects the Fujitsu-A64FX.
958
959	  If unsure, say Y.
960
961config HISILICON_ERRATUM_161600802
962	bool "Hip07 161600802: Erroneous redistributor VLPI base"
963	default y
964	help
965	  The HiSilicon Hip07 SoC uses the wrong redistributor base
966	  when issued ITS commands such as VMOVP and VMAPP, and requires
967	  a 128kB offset to be applied to the target address in this commands.
968
969	  If unsure, say Y.
970
971config QCOM_FALKOR_ERRATUM_1003
972	bool "Falkor E1003: Incorrect translation due to ASID change"
973	default y
974	help
975	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
976	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
977	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
978	  then only for entries in the walk cache, since the leaf translation
979	  is unchanged. Work around the erratum by invalidating the walk cache
980	  entries for the trampoline before entering the kernel proper.
981
982config QCOM_FALKOR_ERRATUM_1009
983	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
984	default y
985	select ARM64_WORKAROUND_REPEAT_TLBI
986	help
987	  On Falkor v1, the CPU may prematurely complete a DSB following a
988	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
989	  one more time to fix the issue.
990
991	  If unsure, say Y.
992
993config QCOM_QDF2400_ERRATUM_0065
994	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
995	default y
996	help
997	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
998	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
999	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1000
1001	  If unsure, say Y.
1002
1003config QCOM_FALKOR_ERRATUM_E1041
1004	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1005	default y
1006	help
1007	  Falkor CPU may speculatively fetch instructions from an improper
1008	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
1009	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1010
1011	  If unsure, say Y.
1012
1013config NVIDIA_CARMEL_CNP_ERRATUM
1014	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1015	default y
1016	help
1017	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1018	  invalidate shared TLB entries installed by a different core, as it would
1019	  on standard ARM cores.
1020
1021	  If unsure, say Y.
1022
1023config SOCIONEXT_SYNQUACER_PREITS
1024	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1025	default y
1026	help
1027	  Socionext Synquacer SoCs implement a separate h/w block to generate
1028	  MSI doorbell writes with non-zero values for the device ID.
1029
1030	  If unsure, say Y.
1031
1032endmenu
1033
1034
1035choice
1036	prompt "Page size"
1037	default ARM64_4K_PAGES
1038	help
1039	  Page size (translation granule) configuration.
1040
1041config ARM64_4K_PAGES
1042	bool "4KB"
1043	help
1044	  This feature enables 4KB pages support.
1045
1046config ARM64_16K_PAGES
1047	bool "16KB"
1048	help
1049	  The system will use 16KB pages support. AArch32 emulation
1050	  requires applications compiled with 16K (or a multiple of 16K)
1051	  aligned segments.
1052
1053config ARM64_64K_PAGES
1054	bool "64KB"
1055	help
1056	  This feature enables 64KB pages support (4KB by default)
1057	  allowing only two levels of page tables and faster TLB
1058	  look-up. AArch32 emulation requires applications compiled
1059	  with 64K aligned segments.
1060
1061endchoice
1062
1063choice
1064	prompt "Virtual address space size"
1065	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1066	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1067	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1068	help
1069	  Allows choosing one of multiple possible virtual address
1070	  space sizes. The level of translation table is determined by
1071	  a combination of page size and virtual address space size.
1072
1073config ARM64_VA_BITS_36
1074	bool "36-bit" if EXPERT
1075	depends on ARM64_16K_PAGES
1076
1077config ARM64_VA_BITS_39
1078	bool "39-bit"
1079	depends on ARM64_4K_PAGES
1080
1081config ARM64_VA_BITS_42
1082	bool "42-bit"
1083	depends on ARM64_64K_PAGES
1084
1085config ARM64_VA_BITS_47
1086	bool "47-bit"
1087	depends on ARM64_16K_PAGES
1088
1089config ARM64_VA_BITS_48
1090	bool "48-bit"
1091
1092config ARM64_VA_BITS_52
1093	bool "52-bit"
1094	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1095	help
1096	  Enable 52-bit virtual addressing for userspace when explicitly
1097	  requested via a hint to mmap(). The kernel will also use 52-bit
1098	  virtual addresses for its own mappings (provided HW support for
1099	  this feature is available, otherwise it reverts to 48-bit).
1100
1101	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1102	  ARMv8.3 Pointer Authentication will result in the PAC being
1103	  reduced from 7 bits to 3 bits, which may have a significant
1104	  impact on its susceptibility to brute-force attacks.
1105
1106	  If unsure, select 48-bit virtual addressing instead.
1107
1108endchoice
1109
1110config ARM64_FORCE_52BIT
1111	bool "Force 52-bit virtual addresses for userspace"
1112	depends on ARM64_VA_BITS_52 && EXPERT
1113	help
1114	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1115	  to maintain compatibility with older software by providing 48-bit VAs
1116	  unless a hint is supplied to mmap.
1117
1118	  This configuration option disables the 48-bit compatibility logic, and
1119	  forces all userspace addresses to be 52-bit on HW that supports it. One
1120	  should only enable this configuration option for stress testing userspace
1121	  memory management code. If unsure say N here.
1122
1123config ARM64_VA_BITS
1124	int
1125	default 36 if ARM64_VA_BITS_36
1126	default 39 if ARM64_VA_BITS_39
1127	default 42 if ARM64_VA_BITS_42
1128	default 47 if ARM64_VA_BITS_47
1129	default 48 if ARM64_VA_BITS_48
1130	default 52 if ARM64_VA_BITS_52
1131
1132choice
1133	prompt "Physical address space size"
1134	default ARM64_PA_BITS_48
1135	help
1136	  Choose the maximum physical address range that the kernel will
1137	  support.
1138
1139config ARM64_PA_BITS_48
1140	bool "48-bit"
1141
1142config ARM64_PA_BITS_52
1143	bool "52-bit (ARMv8.2)"
1144	depends on ARM64_64K_PAGES
1145	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1146	help
1147	  Enable support for a 52-bit physical address space, introduced as
1148	  part of the ARMv8.2-LPA extension.
1149
1150	  With this enabled, the kernel will also continue to work on CPUs that
1151	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1152	  minor performance overhead).
1153
1154endchoice
1155
1156config ARM64_PA_BITS
1157	int
1158	default 48 if ARM64_PA_BITS_48
1159	default 52 if ARM64_PA_BITS_52
1160
1161choice
1162	prompt "Endianness"
1163	default CPU_LITTLE_ENDIAN
1164	help
1165	  Select the endianness of data accesses performed by the CPU. Userspace
1166	  applications will need to be compiled and linked for the endianness
1167	  that is selected here.
1168
1169config CPU_BIG_ENDIAN
1170	bool "Build big-endian kernel"
1171	depends on !LD_IS_LLD || LLD_VERSION >= 130000
1172	help
1173	  Say Y if you plan on running a kernel with a big-endian userspace.
1174
1175config CPU_LITTLE_ENDIAN
1176	bool "Build little-endian kernel"
1177	help
1178	  Say Y if you plan on running a kernel with a little-endian userspace.
1179	  This is usually the case for distributions targeting arm64.
1180
1181endchoice
1182
1183config SCHED_MC
1184	bool "Multi-core scheduler support"
1185	help
1186	  Multi-core scheduler support improves the CPU scheduler's decision
1187	  making when dealing with multi-core CPU chips at a cost of slightly
1188	  increased overhead in some places. If unsure say N here.
1189
1190config SCHED_CLUSTER
1191	bool "Cluster scheduler support"
1192	help
1193	  Cluster scheduler support improves the CPU scheduler's decision
1194	  making when dealing with machines that have clusters of CPUs.
1195	  Cluster usually means a couple of CPUs which are placed closely
1196	  by sharing mid-level caches, last-level cache tags or internal
1197	  busses.
1198
1199config SCHED_SMT
1200	bool "SMT scheduler support"
1201	help
1202	  Improves the CPU scheduler's decision making when dealing with
1203	  MultiThreading at a cost of slightly increased overhead in some
1204	  places. If unsure say N here.
1205
1206config NR_CPUS
1207	int "Maximum number of CPUs (2-4096)"
1208	range 2 4096
1209	default "256"
1210
1211config HOTPLUG_CPU
1212	bool "Support for hot-pluggable CPUs"
1213	select GENERIC_IRQ_MIGRATION
1214	help
1215	  Say Y here to experiment with turning CPUs off and on.  CPUs
1216	  can be controlled through /sys/devices/system/cpu.
1217
1218# Common NUMA Features
1219config NUMA
1220	bool "NUMA Memory Allocation and Scheduler Support"
1221	select GENERIC_ARCH_NUMA
1222	select ACPI_NUMA if ACPI
1223	select OF_NUMA
1224	select HAVE_SETUP_PER_CPU_AREA
1225	select NEED_PER_CPU_EMBED_FIRST_CHUNK
1226	select NEED_PER_CPU_PAGE_FIRST_CHUNK
1227	select USE_PERCPU_NUMA_NODE_ID
1228	help
1229	  Enable NUMA (Non-Uniform Memory Access) support.
1230
1231	  The kernel will try to allocate memory used by a CPU on the
1232	  local memory of the CPU and add some more
1233	  NUMA awareness to the kernel.
1234
1235config NODES_SHIFT
1236	int "Maximum NUMA Nodes (as a power of 2)"
1237	range 1 10
1238	default "4"
1239	depends on NUMA
1240	help
1241	  Specify the maximum number of NUMA Nodes available on the target
1242	  system.  Increases memory reserved to accommodate various tables.
1243
1244source "kernel/Kconfig.hz"
1245
1246config ARCH_SPARSEMEM_ENABLE
1247	def_bool y
1248	select SPARSEMEM_VMEMMAP_ENABLE
1249	select SPARSEMEM_VMEMMAP
1250
1251config HW_PERF_EVENTS
1252	def_bool y
1253	depends on ARM_PMU
1254
1255config ARCH_HAS_FILTER_PGPROT
1256	def_bool y
1257
1258# Supported by clang >= 7.0
1259config CC_HAVE_SHADOW_CALL_STACK
1260	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1261
1262config PARAVIRT
1263	bool "Enable paravirtualization code"
1264	help
1265	  This changes the kernel so it can modify itself when it is run
1266	  under a hypervisor, potentially improving performance significantly
1267	  over full virtualization.
1268
1269config PARAVIRT_TIME_ACCOUNTING
1270	bool "Paravirtual steal time accounting"
1271	select PARAVIRT
1272	help
1273	  Select this option to enable fine granularity task steal time
1274	  accounting. Time spent executing other tasks in parallel with
1275	  the current vCPU is discounted from the vCPU power. To account for
1276	  that, there can be a small performance impact.
1277
1278	  If in doubt, say N here.
1279
1280config KEXEC
1281	depends on PM_SLEEP_SMP
1282	select KEXEC_CORE
1283	bool "kexec system call"
1284	help
1285	  kexec is a system call that implements the ability to shutdown your
1286	  current kernel, and to start another kernel.  It is like a reboot
1287	  but it is independent of the system firmware.   And like a reboot
1288	  you can start any kernel with it, not just Linux.
1289
1290config KEXEC_FILE
1291	bool "kexec file based system call"
1292	select KEXEC_CORE
1293	select HAVE_IMA_KEXEC if IMA
1294	help
1295	  This is new version of kexec system call. This system call is
1296	  file based and takes file descriptors as system call argument
1297	  for kernel and initramfs as opposed to list of segments as
1298	  accepted by previous system call.
1299
1300config KEXEC_SIG
1301	bool "Verify kernel signature during kexec_file_load() syscall"
1302	depends on KEXEC_FILE
1303	help
1304	  Select this option to verify a signature with loaded kernel
1305	  image. If configured, any attempt of loading a image without
1306	  valid signature will fail.
1307
1308	  In addition to that option, you need to enable signature
1309	  verification for the corresponding kernel image type being
1310	  loaded in order for this to work.
1311
1312config KEXEC_IMAGE_VERIFY_SIG
1313	bool "Enable Image signature verification support"
1314	default y
1315	depends on KEXEC_SIG
1316	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1317	help
1318	  Enable Image signature verification support.
1319
1320comment "Support for PE file signature verification disabled"
1321	depends on KEXEC_SIG
1322	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1323
1324config CRASH_DUMP
1325	bool "Build kdump crash kernel"
1326	help
1327	  Generate crash dump after being started by kexec. This should
1328	  be normally only set in special crash dump kernels which are
1329	  loaded in the main kernel with kexec-tools into a specially
1330	  reserved region and then later executed after a crash by
1331	  kdump/kexec.
1332
1333	  For more details see Documentation/admin-guide/kdump/kdump.rst
1334
1335config TRANS_TABLE
1336	def_bool y
1337	depends on HIBERNATION || KEXEC_CORE
1338
1339config XEN_DOM0
1340	def_bool y
1341	depends on XEN
1342
1343config XEN
1344	bool "Xen guest support on ARM64"
1345	depends on ARM64 && OF
1346	select SWIOTLB_XEN
1347	select PARAVIRT
1348	help
1349	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1350
1351config FORCE_MAX_ZONEORDER
1352	int
1353	default "14" if ARM64_64K_PAGES
1354	default "12" if ARM64_16K_PAGES
1355	default "11"
1356	help
1357	  The kernel memory allocator divides physically contiguous memory
1358	  blocks into "zones", where each zone is a power of two number of
1359	  pages.  This option selects the largest power of two that the kernel
1360	  keeps in the memory allocator.  If you need to allocate very large
1361	  blocks of physically contiguous memory, then you may need to
1362	  increase this value.
1363
1364	  This config option is actually maximum order plus one. For example,
1365	  a value of 11 means that the largest free memory block is 2^10 pages.
1366
1367	  We make sure that we can allocate upto a HugePage size for each configuration.
1368	  Hence we have :
1369		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1370
1371	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1372	  4M allocations matching the default size used by generic code.
1373
1374config UNMAP_KERNEL_AT_EL0
1375	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1376	default y
1377	help
1378	  Speculation attacks against some high-performance processors can
1379	  be used to bypass MMU permission checks and leak kernel data to
1380	  userspace. This can be defended against by unmapping the kernel
1381	  when running in userspace, mapping it back in on exception entry
1382	  via a trampoline page in the vector table.
1383
1384	  If unsure, say Y.
1385
1386config RODATA_FULL_DEFAULT_ENABLED
1387	bool "Apply r/o permissions of VM areas also to their linear aliases"
1388	default y
1389	help
1390	  Apply read-only attributes of VM areas to the linear alias of
1391	  the backing pages as well. This prevents code or read-only data
1392	  from being modified (inadvertently or intentionally) via another
1393	  mapping of the same memory page. This additional enhancement can
1394	  be turned off at runtime by passing rodata=[off|on] (and turned on
1395	  with rodata=full if this option is set to 'n')
1396
1397	  This requires the linear region to be mapped down to pages,
1398	  which may adversely affect performance in some cases.
1399
1400config ARM64_SW_TTBR0_PAN
1401	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1402	help
1403	  Enabling this option prevents the kernel from accessing
1404	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1405	  zeroed area and reserved ASID. The user access routines
1406	  restore the valid TTBR0_EL1 temporarily.
1407
1408config ARM64_TAGGED_ADDR_ABI
1409	bool "Enable the tagged user addresses syscall ABI"
1410	default y
1411	help
1412	  When this option is enabled, user applications can opt in to a
1413	  relaxed ABI via prctl() allowing tagged addresses to be passed
1414	  to system calls as pointer arguments. For details, see
1415	  Documentation/arm64/tagged-address-abi.rst.
1416
1417menuconfig COMPAT
1418	bool "Kernel support for 32-bit EL0"
1419	depends on ARM64_4K_PAGES || EXPERT
1420	select HAVE_UID16
1421	select OLD_SIGSUSPEND3
1422	select COMPAT_OLD_SIGACTION
1423	help
1424	  This option enables support for a 32-bit EL0 running under a 64-bit
1425	  kernel at EL1. AArch32-specific components such as system calls,
1426	  the user helper functions, VFP support and the ptrace interface are
1427	  handled appropriately by the kernel.
1428
1429	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1430	  that you will only be able to execute AArch32 binaries that were compiled
1431	  with page size aligned segments.
1432
1433	  If you want to execute 32-bit userspace applications, say Y.
1434
1435if COMPAT
1436
1437config KUSER_HELPERS
1438	bool "Enable kuser helpers page for 32-bit applications"
1439	default y
1440	help
1441	  Warning: disabling this option may break 32-bit user programs.
1442
1443	  Provide kuser helpers to compat tasks. The kernel provides
1444	  helper code to userspace in read only form at a fixed location
1445	  to allow userspace to be independent of the CPU type fitted to
1446	  the system. This permits binaries to be run on ARMv4 through
1447	  to ARMv8 without modification.
1448
1449	  See Documentation/arm/kernel_user_helpers.rst for details.
1450
1451	  However, the fixed address nature of these helpers can be used
1452	  by ROP (return orientated programming) authors when creating
1453	  exploits.
1454
1455	  If all of the binaries and libraries which run on your platform
1456	  are built specifically for your platform, and make no use of
1457	  these helpers, then you can turn this option off to hinder
1458	  such exploits. However, in that case, if a binary or library
1459	  relying on those helpers is run, it will not function correctly.
1460
1461	  Say N here only if you are absolutely certain that you do not
1462	  need these helpers; otherwise, the safe option is to say Y.
1463
1464config COMPAT_VDSO
1465	bool "Enable vDSO for 32-bit applications"
1466	depends on !CPU_BIG_ENDIAN
1467	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1468	select GENERIC_COMPAT_VDSO
1469	default y
1470	help
1471	  Place in the process address space of 32-bit applications an
1472	  ELF shared object providing fast implementations of gettimeofday
1473	  and clock_gettime.
1474
1475	  You must have a 32-bit build of glibc 2.22 or later for programs
1476	  to seamlessly take advantage of this.
1477
1478config THUMB2_COMPAT_VDSO
1479	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1480	depends on COMPAT_VDSO
1481	default y
1482	help
1483	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1484	  otherwise with '-marm'.
1485
1486menuconfig ARMV8_DEPRECATED
1487	bool "Emulate deprecated/obsolete ARMv8 instructions"
1488	depends on SYSCTL
1489	help
1490	  Legacy software support may require certain instructions
1491	  that have been deprecated or obsoleted in the architecture.
1492
1493	  Enable this config to enable selective emulation of these
1494	  features.
1495
1496	  If unsure, say Y
1497
1498if ARMV8_DEPRECATED
1499
1500config SWP_EMULATION
1501	bool "Emulate SWP/SWPB instructions"
1502	help
1503	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1504	  they are always undefined. Say Y here to enable software
1505	  emulation of these instructions for userspace using LDXR/STXR.
1506	  This feature can be controlled at runtime with the abi.swp
1507	  sysctl which is disabled by default.
1508
1509	  In some older versions of glibc [<=2.8] SWP is used during futex
1510	  trylock() operations with the assumption that the code will not
1511	  be preempted. This invalid assumption may be more likely to fail
1512	  with SWP emulation enabled, leading to deadlock of the user
1513	  application.
1514
1515	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1516	  on an external transaction monitoring block called a global
1517	  monitor to maintain update atomicity. If your system does not
1518	  implement a global monitor, this option can cause programs that
1519	  perform SWP operations to uncached memory to deadlock.
1520
1521	  If unsure, say Y
1522
1523config CP15_BARRIER_EMULATION
1524	bool "Emulate CP15 Barrier instructions"
1525	help
1526	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1527	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1528	  strongly recommended to use the ISB, DSB, and DMB
1529	  instructions instead.
1530
1531	  Say Y here to enable software emulation of these
1532	  instructions for AArch32 userspace code. When this option is
1533	  enabled, CP15 barrier usage is traced which can help
1534	  identify software that needs updating. This feature can be
1535	  controlled at runtime with the abi.cp15_barrier sysctl.
1536
1537	  If unsure, say Y
1538
1539config SETEND_EMULATION
1540	bool "Emulate SETEND instruction"
1541	help
1542	  The SETEND instruction alters the data-endianness of the
1543	  AArch32 EL0, and is deprecated in ARMv8.
1544
1545	  Say Y here to enable software emulation of the instruction
1546	  for AArch32 userspace code. This feature can be controlled
1547	  at runtime with the abi.setend sysctl.
1548
1549	  Note: All the cpus on the system must have mixed endian support at EL0
1550	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1551	  endian - is hotplugged in after this feature has been enabled, there could
1552	  be unexpected results in the applications.
1553
1554	  If unsure, say Y
1555endif
1556
1557endif
1558
1559menu "ARMv8.1 architectural features"
1560
1561config ARM64_HW_AFDBM
1562	bool "Support for hardware updates of the Access and Dirty page flags"
1563	default y
1564	help
1565	  The ARMv8.1 architecture extensions introduce support for
1566	  hardware updates of the access and dirty information in page
1567	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1568	  capable processors, accesses to pages with PTE_AF cleared will
1569	  set this bit instead of raising an access flag fault.
1570	  Similarly, writes to read-only pages with the DBM bit set will
1571	  clear the read-only bit (AP[2]) instead of raising a
1572	  permission fault.
1573
1574	  Kernels built with this configuration option enabled continue
1575	  to work on pre-ARMv8.1 hardware and the performance impact is
1576	  minimal. If unsure, say Y.
1577
1578config ARM64_PAN
1579	bool "Enable support for Privileged Access Never (PAN)"
1580	default y
1581	help
1582	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1583	 prevents the kernel or hypervisor from accessing user-space (EL0)
1584	 memory directly.
1585
1586	 Choosing this option will cause any unprotected (not using
1587	 copy_to_user et al) memory access to fail with a permission fault.
1588
1589	 The feature is detected at runtime, and will remain as a 'nop'
1590	 instruction if the cpu does not implement the feature.
1591
1592config AS_HAS_LDAPR
1593	def_bool $(as-instr,.arch_extension rcpc)
1594
1595config AS_HAS_LSE_ATOMICS
1596	def_bool $(as-instr,.arch_extension lse)
1597
1598config ARM64_LSE_ATOMICS
1599	bool
1600	default ARM64_USE_LSE_ATOMICS
1601	depends on AS_HAS_LSE_ATOMICS
1602
1603config ARM64_USE_LSE_ATOMICS
1604	bool "Atomic instructions"
1605	depends on JUMP_LABEL
1606	default y
1607	help
1608	  As part of the Large System Extensions, ARMv8.1 introduces new
1609	  atomic instructions that are designed specifically to scale in
1610	  very large systems.
1611
1612	  Say Y here to make use of these instructions for the in-kernel
1613	  atomic routines. This incurs a small overhead on CPUs that do
1614	  not support these instructions and requires the kernel to be
1615	  built with binutils >= 2.25 in order for the new instructions
1616	  to be used.
1617
1618endmenu
1619
1620menu "ARMv8.2 architectural features"
1621
1622config AS_HAS_ARMV8_2
1623       def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1624
1625config AS_HAS_SHA3
1626       def_bool $(as-instr,.arch armv8.2-a+sha3)
1627
1628config ARM64_PMEM
1629	bool "Enable support for persistent memory"
1630	select ARCH_HAS_PMEM_API
1631	select ARCH_HAS_UACCESS_FLUSHCACHE
1632	help
1633	  Say Y to enable support for the persistent memory API based on the
1634	  ARMv8.2 DCPoP feature.
1635
1636	  The feature is detected at runtime, and the kernel will use DC CVAC
1637	  operations if DC CVAP is not supported (following the behaviour of
1638	  DC CVAP itself if the system does not define a point of persistence).
1639
1640config ARM64_RAS_EXTN
1641	bool "Enable support for RAS CPU Extensions"
1642	default y
1643	help
1644	  CPUs that support the Reliability, Availability and Serviceability
1645	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1646	  errors, classify them and report them to software.
1647
1648	  On CPUs with these extensions system software can use additional
1649	  barriers to determine if faults are pending and read the
1650	  classification from a new set of registers.
1651
1652	  Selecting this feature will allow the kernel to use these barriers
1653	  and access the new registers if the system supports the extension.
1654	  Platform RAS features may additionally depend on firmware support.
1655
1656config ARM64_CNP
1657	bool "Enable support for Common Not Private (CNP) translations"
1658	default y
1659	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1660	help
1661	  Common Not Private (CNP) allows translation table entries to
1662	  be shared between different PEs in the same inner shareable
1663	  domain, so the hardware can use this fact to optimise the
1664	  caching of such entries in the TLB.
1665
1666	  Selecting this option allows the CNP feature to be detected
1667	  at runtime, and does not affect PEs that do not implement
1668	  this feature.
1669
1670endmenu
1671
1672menu "ARMv8.3 architectural features"
1673
1674config ARM64_PTR_AUTH
1675	bool "Enable support for pointer authentication"
1676	default y
1677	help
1678	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1679	  instructions for signing and authenticating pointers against secret
1680	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1681	  and other attacks.
1682
1683	  This option enables these instructions at EL0 (i.e. for userspace).
1684	  Choosing this option will cause the kernel to initialise secret keys
1685	  for each process at exec() time, with these keys being
1686	  context-switched along with the process.
1687
1688	  The feature is detected at runtime. If the feature is not present in
1689	  hardware it will not be advertised to userspace/KVM guest nor will it
1690	  be enabled.
1691
1692	  If the feature is present on the boot CPU but not on a late CPU, then
1693	  the late CPU will be parked. Also, if the boot CPU does not have
1694	  address auth and the late CPU has then the late CPU will still boot
1695	  but with the feature disabled. On such a system, this option should
1696	  not be selected.
1697
1698config ARM64_PTR_AUTH_KERNEL
1699	bool "Use pointer authentication for kernel"
1700	default y
1701	depends on ARM64_PTR_AUTH
1702	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1703	# Modern compilers insert a .note.gnu.property section note for PAC
1704	# which is only understood by binutils starting with version 2.33.1.
1705	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1706	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1707	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1708	help
1709	  If the compiler supports the -mbranch-protection or
1710	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1711	  will cause the kernel itself to be compiled with return address
1712	  protection. In this case, and if the target hardware is known to
1713	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1714	  disabled with minimal loss of protection.
1715
1716	  This feature works with FUNCTION_GRAPH_TRACER option only if
1717	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1718
1719config CC_HAS_BRANCH_PROT_PAC_RET
1720	# GCC 9 or later, clang 8 or later
1721	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1722
1723config CC_HAS_SIGN_RETURN_ADDRESS
1724	# GCC 7, 8
1725	def_bool $(cc-option,-msign-return-address=all)
1726
1727config AS_HAS_PAC
1728	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1729
1730config AS_HAS_CFI_NEGATE_RA_STATE
1731	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1732
1733endmenu
1734
1735menu "ARMv8.4 architectural features"
1736
1737config ARM64_AMU_EXTN
1738	bool "Enable support for the Activity Monitors Unit CPU extension"
1739	default y
1740	help
1741	  The activity monitors extension is an optional extension introduced
1742	  by the ARMv8.4 CPU architecture. This enables support for version 1
1743	  of the activity monitors architecture, AMUv1.
1744
1745	  To enable the use of this extension on CPUs that implement it, say Y.
1746
1747	  Note that for architectural reasons, firmware _must_ implement AMU
1748	  support when running on CPUs that present the activity monitors
1749	  extension. The required support is present in:
1750	    * Version 1.5 and later of the ARM Trusted Firmware
1751
1752	  For kernels that have this configuration enabled but boot with broken
1753	  firmware, you may need to say N here until the firmware is fixed.
1754	  Otherwise you may experience firmware panics or lockups when
1755	  accessing the counter registers. Even if you are not observing these
1756	  symptoms, the values returned by the register reads might not
1757	  correctly reflect reality. Most commonly, the value read will be 0,
1758	  indicating that the counter is not enabled.
1759
1760config AS_HAS_ARMV8_4
1761	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1762
1763config ARM64_TLB_RANGE
1764	bool "Enable support for tlbi range feature"
1765	default y
1766	depends on AS_HAS_ARMV8_4
1767	help
1768	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1769	  range of input addresses.
1770
1771	  The feature introduces new assembly instructions, and they were
1772	  support when binutils >= 2.30.
1773
1774endmenu
1775
1776menu "ARMv8.5 architectural features"
1777
1778config AS_HAS_ARMV8_5
1779	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1780
1781config ARM64_BTI
1782	bool "Branch Target Identification support"
1783	default y
1784	help
1785	  Branch Target Identification (part of the ARMv8.5 Extensions)
1786	  provides a mechanism to limit the set of locations to which computed
1787	  branch instructions such as BR or BLR can jump.
1788
1789	  To make use of BTI on CPUs that support it, say Y.
1790
1791	  BTI is intended to provide complementary protection to other control
1792	  flow integrity protection mechanisms, such as the Pointer
1793	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1794	  For this reason, it does not make sense to enable this option without
1795	  also enabling support for pointer authentication.  Thus, when
1796	  enabling this option you should also select ARM64_PTR_AUTH=y.
1797
1798	  Userspace binaries must also be specifically compiled to make use of
1799	  this mechanism.  If you say N here or the hardware does not support
1800	  BTI, such binaries can still run, but you get no additional
1801	  enforcement of branch destinations.
1802
1803config ARM64_BTI_KERNEL
1804	bool "Use Branch Target Identification for kernel"
1805	default y
1806	depends on ARM64_BTI
1807	depends on ARM64_PTR_AUTH_KERNEL
1808	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1809	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1810	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1811	# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1812	depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1813	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1814	help
1815	  Build the kernel with Branch Target Identification annotations
1816	  and enable enforcement of this for kernel code. When this option
1817	  is enabled and the system supports BTI all kernel code including
1818	  modular code must have BTI enabled.
1819
1820config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1821	# GCC 9 or later, clang 8 or later
1822	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1823
1824config ARM64_E0PD
1825	bool "Enable support for E0PD"
1826	default y
1827	help
1828	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1829	  that EL0 accesses made via TTBR1 always fault in constant time,
1830	  providing similar benefits to KASLR as those provided by KPTI, but
1831	  with lower overhead and without disrupting legitimate access to
1832	  kernel memory such as SPE.
1833
1834	  This option enables E0PD for TTBR1 where available.
1835
1836config ARCH_RANDOM
1837	bool "Enable support for random number generation"
1838	default y
1839	help
1840	  Random number generation (part of the ARMv8.5 Extensions)
1841	  provides a high bandwidth, cryptographically secure
1842	  hardware random number generator.
1843
1844config ARM64_AS_HAS_MTE
1845	# Initial support for MTE went in binutils 2.32.0, checked with
1846	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1847	# as a late addition to the final architecture spec (LDGM/STGM)
1848	# is only supported in the newer 2.32.x and 2.33 binutils
1849	# versions, hence the extra "stgm" instruction check below.
1850	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1851
1852config ARM64_MTE
1853	bool "Memory Tagging Extension support"
1854	default y
1855	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1856	depends on AS_HAS_ARMV8_5
1857	depends on AS_HAS_LSE_ATOMICS
1858	# Required for tag checking in the uaccess routines
1859	depends on ARM64_PAN
1860	select ARCH_USES_HIGH_VMA_FLAGS
1861	help
1862	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1863	  architectural support for run-time, always-on detection of
1864	  various classes of memory error to aid with software debugging
1865	  to eliminate vulnerabilities arising from memory-unsafe
1866	  languages.
1867
1868	  This option enables the support for the Memory Tagging
1869	  Extension at EL0 (i.e. for userspace).
1870
1871	  Selecting this option allows the feature to be detected at
1872	  runtime. Any secondary CPU not implementing this feature will
1873	  not be allowed a late bring-up.
1874
1875	  Userspace binaries that want to use this feature must
1876	  explicitly opt in. The mechanism for the userspace is
1877	  described in:
1878
1879	  Documentation/arm64/memory-tagging-extension.rst.
1880
1881endmenu
1882
1883menu "ARMv8.7 architectural features"
1884
1885config ARM64_EPAN
1886	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1887	default y
1888	depends on ARM64_PAN
1889	help
1890	 Enhanced Privileged Access Never (EPAN) allows Privileged
1891	 Access Never to be used with Execute-only mappings.
1892
1893	 The feature is detected at runtime, and will remain disabled
1894	 if the cpu does not implement the feature.
1895endmenu
1896
1897config ARM64_SVE
1898	bool "ARM Scalable Vector Extension support"
1899	default y
1900	help
1901	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1902	  execution state which complements and extends the SIMD functionality
1903	  of the base architecture to support much larger vectors and to enable
1904	  additional vectorisation opportunities.
1905
1906	  To enable use of this extension on CPUs that implement it, say Y.
1907
1908	  On CPUs that support the SVE2 extensions, this option will enable
1909	  those too.
1910
1911	  Note that for architectural reasons, firmware _must_ implement SVE
1912	  support when running on SVE capable hardware.  The required support
1913	  is present in:
1914
1915	    * version 1.5 and later of the ARM Trusted Firmware
1916	    * the AArch64 boot wrapper since commit 5e1261e08abf
1917	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1918
1919	  For other firmware implementations, consult the firmware documentation
1920	  or vendor.
1921
1922	  If you need the kernel to boot on SVE-capable hardware with broken
1923	  firmware, you may need to say N here until you get your firmware
1924	  fixed.  Otherwise, you may experience firmware panics or lockups when
1925	  booting the kernel.  If unsure and you are not observing these
1926	  symptoms, you should assume that it is safe to say Y.
1927
1928config ARM64_MODULE_PLTS
1929	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1930	depends on MODULES
1931	select HAVE_MOD_ARCH_SPECIFIC
1932	help
1933	  Allocate PLTs when loading modules so that jumps and calls whose
1934	  targets are too far away for their relative offsets to be encoded
1935	  in the instructions themselves can be bounced via veneers in the
1936	  module's PLT. This allows modules to be allocated in the generic
1937	  vmalloc area after the dedicated module memory area has been
1938	  exhausted.
1939
1940	  When running with address space randomization (KASLR), the module
1941	  region itself may be too far away for ordinary relative jumps and
1942	  calls, and so in that case, module PLTs are required and cannot be
1943	  disabled.
1944
1945	  Specific errata workaround(s) might also force module PLTs to be
1946	  enabled (ARM64_ERRATUM_843419).
1947
1948config ARM64_PSEUDO_NMI
1949	bool "Support for NMI-like interrupts"
1950	select ARM_GIC_V3
1951	help
1952	  Adds support for mimicking Non-Maskable Interrupts through the use of
1953	  GIC interrupt priority. This support requires version 3 or later of
1954	  ARM GIC.
1955
1956	  This high priority configuration for interrupts needs to be
1957	  explicitly enabled by setting the kernel parameter
1958	  "irqchip.gicv3_pseudo_nmi" to 1.
1959
1960	  If unsure, say N
1961
1962if ARM64_PSEUDO_NMI
1963config ARM64_DEBUG_PRIORITY_MASKING
1964	bool "Debug interrupt priority masking"
1965	help
1966	  This adds runtime checks to functions enabling/disabling
1967	  interrupts when using priority masking. The additional checks verify
1968	  the validity of ICC_PMR_EL1 when calling concerned functions.
1969
1970	  If unsure, say N
1971endif
1972
1973config RELOCATABLE
1974	bool "Build a relocatable kernel image" if EXPERT
1975	select ARCH_HAS_RELR
1976	default y
1977	help
1978	  This builds the kernel as a Position Independent Executable (PIE),
1979	  which retains all relocation metadata required to relocate the
1980	  kernel binary at runtime to a different virtual address than the
1981	  address it was linked at.
1982	  Since AArch64 uses the RELA relocation format, this requires a
1983	  relocation pass at runtime even if the kernel is loaded at the
1984	  same address it was linked at.
1985
1986config RANDOMIZE_BASE
1987	bool "Randomize the address of the kernel image"
1988	select ARM64_MODULE_PLTS if MODULES
1989	select RELOCATABLE
1990	help
1991	  Randomizes the virtual address at which the kernel image is
1992	  loaded, as a security feature that deters exploit attempts
1993	  relying on knowledge of the location of kernel internals.
1994
1995	  It is the bootloader's job to provide entropy, by passing a
1996	  random u64 value in /chosen/kaslr-seed at kernel entry.
1997
1998	  When booting via the UEFI stub, it will invoke the firmware's
1999	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2000	  to the kernel proper. In addition, it will randomise the physical
2001	  location of the kernel Image as well.
2002
2003	  If unsure, say N.
2004
2005config RANDOMIZE_MODULE_REGION_FULL
2006	bool "Randomize the module region over a 2 GB range"
2007	depends on RANDOMIZE_BASE
2008	default y
2009	help
2010	  Randomizes the location of the module region inside a 2 GB window
2011	  covering the core kernel. This way, it is less likely for modules
2012	  to leak information about the location of core kernel data structures
2013	  but it does imply that function calls between modules and the core
2014	  kernel will need to be resolved via veneers in the module PLT.
2015
2016	  When this option is not set, the module region will be randomized over
2017	  a limited range that contains the [_stext, _etext] interval of the
2018	  core kernel, so branch relocations are almost always in range unless
2019	  ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2020	  particular case of region exhaustion, modules might be able to fall
2021	  back to a larger 2GB area.
2022
2023config CC_HAVE_STACKPROTECTOR_SYSREG
2024	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2025
2026config STACKPROTECTOR_PER_TASK
2027	def_bool y
2028	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2029
2030endmenu
2031
2032menu "Boot options"
2033
2034config ARM64_ACPI_PARKING_PROTOCOL
2035	bool "Enable support for the ARM64 ACPI parking protocol"
2036	depends on ACPI
2037	help
2038	  Enable support for the ARM64 ACPI parking protocol. If disabled
2039	  the kernel will not allow booting through the ARM64 ACPI parking
2040	  protocol even if the corresponding data is present in the ACPI
2041	  MADT table.
2042
2043config CMDLINE
2044	string "Default kernel command string"
2045	default ""
2046	help
2047	  Provide a set of default command-line options at build time by
2048	  entering them here. As a minimum, you should specify the the
2049	  root device (e.g. root=/dev/nfs).
2050
2051choice
2052	prompt "Kernel command line type" if CMDLINE != ""
2053	default CMDLINE_FROM_BOOTLOADER
2054	help
2055	  Choose how the kernel will handle the provided default kernel
2056	  command line string.
2057
2058config CMDLINE_FROM_BOOTLOADER
2059	bool "Use bootloader kernel arguments if available"
2060	help
2061	  Uses the command-line options passed by the boot loader. If
2062	  the boot loader doesn't provide any, the default kernel command
2063	  string provided in CMDLINE will be used.
2064
2065config CMDLINE_FORCE
2066	bool "Always use the default kernel command string"
2067	help
2068	  Always use the default kernel command string, even if the boot
2069	  loader passes other arguments to the kernel.
2070	  This is useful if you cannot or don't want to change the
2071	  command-line options your boot loader passes to the kernel.
2072
2073endchoice
2074
2075config EFI_STUB
2076	bool
2077
2078config EFI
2079	bool "UEFI runtime support"
2080	depends on OF && !CPU_BIG_ENDIAN
2081	depends on KERNEL_MODE_NEON
2082	select ARCH_SUPPORTS_ACPI
2083	select LIBFDT
2084	select UCS2_STRING
2085	select EFI_PARAMS_FROM_FDT
2086	select EFI_RUNTIME_WRAPPERS
2087	select EFI_STUB
2088	select EFI_GENERIC_STUB
2089	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2090	default y
2091	help
2092	  This option provides support for runtime services provided
2093	  by UEFI firmware (such as non-volatile variables, realtime
2094          clock, and platform reset). A UEFI stub is also provided to
2095	  allow the kernel to be booted as an EFI application. This
2096	  is only useful on systems that have UEFI firmware.
2097
2098config DMI
2099	bool "Enable support for SMBIOS (DMI) tables"
2100	depends on EFI
2101	default y
2102	help
2103	  This enables SMBIOS/DMI feature for systems.
2104
2105	  This option is only useful on systems that have UEFI firmware.
2106	  However, even with this option, the resultant kernel should
2107	  continue to boot on existing non-UEFI platforms.
2108
2109endmenu
2110
2111config SYSVIPC_COMPAT
2112	def_bool y
2113	depends on COMPAT && SYSVIPC
2114
2115menu "Power management options"
2116
2117source "kernel/power/Kconfig"
2118
2119config ARCH_HIBERNATION_POSSIBLE
2120	def_bool y
2121	depends on CPU_PM
2122
2123config ARCH_HIBERNATION_HEADER
2124	def_bool y
2125	depends on HIBERNATION
2126
2127config ARCH_SUSPEND_POSSIBLE
2128	def_bool y
2129
2130endmenu
2131
2132menu "CPU Power Management"
2133
2134source "drivers/cpuidle/Kconfig"
2135
2136source "drivers/cpufreq/Kconfig"
2137
2138endmenu
2139
2140source "drivers/acpi/Kconfig"
2141
2142source "arch/arm64/kvm/Kconfig"
2143
2144if CRYPTO
2145source "arch/arm64/crypto/Kconfig"
2146endif
2147