1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ARCH_HAS_DEVMEM_IS_ALLOWED 7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 8 select ARCH_HAS_ELF_RANDOMIZE 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_HAS_SG_CHAIN 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_SUPPORTS_ATOMIC_RMW 14 select ARCH_SUPPORTS_NUMA_BALANCING 15 select ARCH_WANT_OPTIONAL_GPIOLIB 16 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 17 select ARCH_WANT_FRAME_POINTERS 18 select ARCH_HAS_UBSAN_SANITIZE_ALL 19 select ARM_AMBA 20 select ARM_ARCH_TIMER 21 select ARM_GIC 22 select AUDIT_ARCH_COMPAT_GENERIC 23 select ARM_GIC_V2M if PCI_MSI 24 select ARM_GIC_V3 25 select ARM_GIC_V3_ITS if PCI_MSI 26 select ARM_PSCI_FW 27 select BUILDTIME_EXTABLE_SORT 28 select CLONE_BACKWARDS 29 select COMMON_CLK 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS 32 select EDAC_SUPPORT 33 select FRAME_POINTER 34 select GENERIC_ALLOCATOR 35 select GENERIC_CLOCKEVENTS 36 select GENERIC_CLOCKEVENTS_BROADCAST 37 select GENERIC_CPU_AUTOPROBE 38 select GENERIC_EARLY_IOREMAP 39 select GENERIC_IDLE_POLL_SETUP 40 select GENERIC_IRQ_PROBE 41 select GENERIC_IRQ_SHOW 42 select GENERIC_IRQ_SHOW_LEVEL 43 select GENERIC_PCI_IOMAP 44 select GENERIC_SCHED_CLOCK 45 select GENERIC_SMP_IDLE_THREAD 46 select GENERIC_STRNCPY_FROM_USER 47 select GENERIC_STRNLEN_USER 48 select GENERIC_TIME_VSYSCALL 49 select HANDLE_DOMAIN_IRQ 50 select HARDIRQS_SW_RESEND 51 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 52 select HAVE_ARCH_AUDITSYSCALL 53 select HAVE_ARCH_BITREVERSE 54 select HAVE_ARCH_HUGE_VMAP 55 select HAVE_ARCH_JUMP_LABEL 56 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 57 select HAVE_ARCH_KGDB 58 select HAVE_ARCH_MMAP_RND_BITS 59 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 60 select HAVE_ARCH_SECCOMP_FILTER 61 select HAVE_ARCH_TRACEHOOK 62 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 63 select HAVE_ARM_SMCCC 64 select HAVE_EBPF_JIT 65 select HAVE_C_RECORDMCOUNT 66 select HAVE_CC_STACKPROTECTOR 67 select HAVE_CMPXCHG_DOUBLE 68 select HAVE_CMPXCHG_LOCAL 69 select HAVE_CONTEXT_TRACKING 70 select HAVE_DEBUG_BUGVERBOSE 71 select HAVE_DEBUG_KMEMLEAK 72 select HAVE_DMA_API_DEBUG 73 select HAVE_DMA_CONTIGUOUS 74 select HAVE_DYNAMIC_FTRACE 75 select HAVE_EFFICIENT_UNALIGNED_ACCESS 76 select HAVE_FTRACE_MCOUNT_RECORD 77 select HAVE_FUNCTION_TRACER 78 select HAVE_FUNCTION_GRAPH_TRACER 79 select HAVE_GENERIC_DMA_COHERENT 80 select HAVE_HW_BREAKPOINT if PERF_EVENTS 81 select HAVE_IRQ_TIME_ACCOUNTING 82 select HAVE_MEMBLOCK 83 select HAVE_MEMBLOCK_NODE_MAP if NUMA 84 select HAVE_PATA_PLATFORM 85 select HAVE_PERF_EVENTS 86 select HAVE_PERF_REGS 87 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_RCU_TABLE_FREE 89 select HAVE_SYSCALL_TRACEPOINTS 90 select IOMMU_DMA if IOMMU_SUPPORT 91 select IRQ_DOMAIN 92 select IRQ_FORCED_THREADING 93 select MODULES_USE_ELF_RELA 94 select NO_BOOTMEM 95 select OF 96 select OF_EARLY_FLATTREE 97 select OF_NUMA if NUMA && OF 98 select OF_RESERVED_MEM 99 select PERF_USE_VMALLOC 100 select POWER_RESET 101 select POWER_SUPPLY 102 select SPARSE_IRQ 103 select SYSCTL_EXCEPTION_TRACE 104 help 105 ARM 64-bit (AArch64) Linux support. 106 107config 64BIT 108 def_bool y 109 110config ARCH_PHYS_ADDR_T_64BIT 111 def_bool y 112 113config MMU 114 def_bool y 115 116config ARCH_MMAP_RND_BITS_MIN 117 default 14 if ARM64_64K_PAGES 118 default 16 if ARM64_16K_PAGES 119 default 18 120 121# max bits determined by the following formula: 122# VA_BITS - PAGE_SHIFT - 3 123config ARCH_MMAP_RND_BITS_MAX 124 default 19 if ARM64_VA_BITS=36 125 default 24 if ARM64_VA_BITS=39 126 default 27 if ARM64_VA_BITS=42 127 default 30 if ARM64_VA_BITS=47 128 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 129 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 130 default 33 if ARM64_VA_BITS=48 131 default 14 if ARM64_64K_PAGES 132 default 16 if ARM64_16K_PAGES 133 default 18 134 135config ARCH_MMAP_RND_COMPAT_BITS_MIN 136 default 7 if ARM64_64K_PAGES 137 default 9 if ARM64_16K_PAGES 138 default 11 139 140config ARCH_MMAP_RND_COMPAT_BITS_MAX 141 default 16 142 143config NO_IOPORT_MAP 144 def_bool y if !PCI 145 146config STACKTRACE_SUPPORT 147 def_bool y 148 149config ILLEGAL_POINTER_VALUE 150 hex 151 default 0xdead000000000000 152 153config LOCKDEP_SUPPORT 154 def_bool y 155 156config TRACE_IRQFLAGS_SUPPORT 157 def_bool y 158 159config RWSEM_XCHGADD_ALGORITHM 160 def_bool y 161 162config GENERIC_BUG 163 def_bool y 164 depends on BUG 165 166config GENERIC_BUG_RELATIVE_POINTERS 167 def_bool y 168 depends on GENERIC_BUG 169 170config GENERIC_HWEIGHT 171 def_bool y 172 173config GENERIC_CSUM 174 def_bool y 175 176config GENERIC_CALIBRATE_DELAY 177 def_bool y 178 179config ZONE_DMA 180 def_bool y 181 182config HAVE_GENERIC_RCU_GUP 183 def_bool y 184 185config ARCH_DMA_ADDR_T_64BIT 186 def_bool y 187 188config NEED_DMA_MAP_STATE 189 def_bool y 190 191config NEED_SG_DMA_LENGTH 192 def_bool y 193 194config SMP 195 def_bool y 196 197config SWIOTLB 198 def_bool y 199 200config IOMMU_HELPER 201 def_bool SWIOTLB 202 203config KERNEL_MODE_NEON 204 def_bool y 205 206config FIX_EARLYCON_MEM 207 def_bool y 208 209config PGTABLE_LEVELS 210 int 211 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 212 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 213 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 214 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 215 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 216 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 217 218source "init/Kconfig" 219 220source "kernel/Kconfig.freezer" 221 222source "arch/arm64/Kconfig.platforms" 223 224menu "Bus support" 225 226config PCI 227 bool "PCI support" 228 help 229 This feature enables support for PCI bus system. If you say Y 230 here, the kernel will include drivers and infrastructure code 231 to support PCI bus devices. 232 233config PCI_DOMAINS 234 def_bool PCI 235 236config PCI_DOMAINS_GENERIC 237 def_bool PCI 238 239config PCI_SYSCALL 240 def_bool PCI 241 242source "drivers/pci/Kconfig" 243 244endmenu 245 246menu "Kernel Features" 247 248menu "ARM errata workarounds via the alternatives framework" 249 250config ARM64_ERRATUM_826319 251 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 252 default y 253 help 254 This option adds an alternative code sequence to work around ARM 255 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 256 AXI master interface and an L2 cache. 257 258 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 259 and is unable to accept a certain write via this interface, it will 260 not progress on read data presented on the read data channel and the 261 system can deadlock. 262 263 The workaround promotes data cache clean instructions to 264 data cache clean-and-invalidate. 265 Please note that this does not necessarily enable the workaround, 266 as it depends on the alternative framework, which will only patch 267 the kernel if an affected CPU is detected. 268 269 If unsure, say Y. 270 271config ARM64_ERRATUM_827319 272 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 273 default y 274 help 275 This option adds an alternative code sequence to work around ARM 276 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 277 master interface and an L2 cache. 278 279 Under certain conditions this erratum can cause a clean line eviction 280 to occur at the same time as another transaction to the same address 281 on the AMBA 5 CHI interface, which can cause data corruption if the 282 interconnect reorders the two transactions. 283 284 The workaround promotes data cache clean instructions to 285 data cache clean-and-invalidate. 286 Please note that this does not necessarily enable the workaround, 287 as it depends on the alternative framework, which will only patch 288 the kernel if an affected CPU is detected. 289 290 If unsure, say Y. 291 292config ARM64_ERRATUM_824069 293 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 294 default y 295 help 296 This option adds an alternative code sequence to work around ARM 297 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 298 to a coherent interconnect. 299 300 If a Cortex-A53 processor is executing a store or prefetch for 301 write instruction at the same time as a processor in another 302 cluster is executing a cache maintenance operation to the same 303 address, then this erratum might cause a clean cache line to be 304 incorrectly marked as dirty. 305 306 The workaround promotes data cache clean instructions to 307 data cache clean-and-invalidate. 308 Please note that this option does not necessarily enable the 309 workaround, as it depends on the alternative framework, which will 310 only patch the kernel if an affected CPU is detected. 311 312 If unsure, say Y. 313 314config ARM64_ERRATUM_819472 315 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 316 default y 317 help 318 This option adds an alternative code sequence to work around ARM 319 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 320 present when it is connected to a coherent interconnect. 321 322 If the processor is executing a load and store exclusive sequence at 323 the same time as a processor in another cluster is executing a cache 324 maintenance operation to the same address, then this erratum might 325 cause data corruption. 326 327 The workaround promotes data cache clean instructions to 328 data cache clean-and-invalidate. 329 Please note that this does not necessarily enable the workaround, 330 as it depends on the alternative framework, which will only patch 331 the kernel if an affected CPU is detected. 332 333 If unsure, say Y. 334 335config ARM64_ERRATUM_832075 336 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 337 default y 338 help 339 This option adds an alternative code sequence to work around ARM 340 erratum 832075 on Cortex-A57 parts up to r1p2. 341 342 Affected Cortex-A57 parts might deadlock when exclusive load/store 343 instructions to Write-Back memory are mixed with Device loads. 344 345 The workaround is to promote device loads to use Load-Acquire 346 semantics. 347 Please note that this does not necessarily enable the workaround, 348 as it depends on the alternative framework, which will only patch 349 the kernel if an affected CPU is detected. 350 351 If unsure, say Y. 352 353config ARM64_ERRATUM_834220 354 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 355 depends on KVM 356 default y 357 help 358 This option adds an alternative code sequence to work around ARM 359 erratum 834220 on Cortex-A57 parts up to r1p2. 360 361 Affected Cortex-A57 parts might report a Stage 2 translation 362 fault as the result of a Stage 1 fault for load crossing a 363 page boundary when there is a permission or device memory 364 alignment fault at Stage 1 and a translation fault at Stage 2. 365 366 The workaround is to verify that the Stage 1 translation 367 doesn't generate a fault before handling the Stage 2 fault. 368 Please note that this does not necessarily enable the workaround, 369 as it depends on the alternative framework, which will only patch 370 the kernel if an affected CPU is detected. 371 372 If unsure, say Y. 373 374config ARM64_ERRATUM_845719 375 bool "Cortex-A53: 845719: a load might read incorrect data" 376 depends on COMPAT 377 default y 378 help 379 This option adds an alternative code sequence to work around ARM 380 erratum 845719 on Cortex-A53 parts up to r0p4. 381 382 When running a compat (AArch32) userspace on an affected Cortex-A53 383 part, a load at EL0 from a virtual address that matches the bottom 32 384 bits of the virtual address used by a recent load at (AArch64) EL1 385 might return incorrect data. 386 387 The workaround is to write the contextidr_el1 register on exception 388 return to a 32-bit task. 389 Please note that this does not necessarily enable the workaround, 390 as it depends on the alternative framework, which will only patch 391 the kernel if an affected CPU is detected. 392 393 If unsure, say Y. 394 395config ARM64_ERRATUM_843419 396 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 397 depends on MODULES 398 default y 399 select ARM64_MODULE_CMODEL_LARGE 400 help 401 This option builds kernel modules using the large memory model in 402 order to avoid the use of the ADRP instruction, which can cause 403 a subsequent memory access to use an incorrect address on Cortex-A53 404 parts up to r0p4. 405 406 Note that the kernel itself must be linked with a version of ld 407 which fixes potentially affected ADRP instructions through the 408 use of veneers. 409 410 If unsure, say Y. 411 412config CAVIUM_ERRATUM_22375 413 bool "Cavium erratum 22375, 24313" 414 default y 415 help 416 Enable workaround for erratum 22375, 24313. 417 418 This implements two gicv3-its errata workarounds for ThunderX. Both 419 with small impact affecting only ITS table allocation. 420 421 erratum 22375: only alloc 8MB table size 422 erratum 24313: ignore memory access type 423 424 The fixes are in ITS initialization and basically ignore memory access 425 type and table size provided by the TYPER and BASER registers. 426 427 If unsure, say Y. 428 429config CAVIUM_ERRATUM_23154 430 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 431 default y 432 help 433 The gicv3 of ThunderX requires a modified version for 434 reading the IAR status to ensure data synchronization 435 (access to icc_iar1_el1 is not sync'ed before and after). 436 437 If unsure, say Y. 438 439config CAVIUM_ERRATUM_27456 440 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 441 default y 442 help 443 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 444 instructions may cause the icache to become corrupted if it 445 contains data for a non-current ASID. The fix is to 446 invalidate the icache when changing the mm context. 447 448 If unsure, say Y. 449 450endmenu 451 452 453choice 454 prompt "Page size" 455 default ARM64_4K_PAGES 456 help 457 Page size (translation granule) configuration. 458 459config ARM64_4K_PAGES 460 bool "4KB" 461 help 462 This feature enables 4KB pages support. 463 464config ARM64_16K_PAGES 465 bool "16KB" 466 help 467 The system will use 16KB pages support. AArch32 emulation 468 requires applications compiled with 16K (or a multiple of 16K) 469 aligned segments. 470 471config ARM64_64K_PAGES 472 bool "64KB" 473 help 474 This feature enables 64KB pages support (4KB by default) 475 allowing only two levels of page tables and faster TLB 476 look-up. AArch32 emulation requires applications compiled 477 with 64K aligned segments. 478 479endchoice 480 481choice 482 prompt "Virtual address space size" 483 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 484 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 485 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 486 help 487 Allows choosing one of multiple possible virtual address 488 space sizes. The level of translation table is determined by 489 a combination of page size and virtual address space size. 490 491config ARM64_VA_BITS_36 492 bool "36-bit" if EXPERT 493 depends on ARM64_16K_PAGES 494 495config ARM64_VA_BITS_39 496 bool "39-bit" 497 depends on ARM64_4K_PAGES 498 499config ARM64_VA_BITS_42 500 bool "42-bit" 501 depends on ARM64_64K_PAGES 502 503config ARM64_VA_BITS_47 504 bool "47-bit" 505 depends on ARM64_16K_PAGES 506 507config ARM64_VA_BITS_48 508 bool "48-bit" 509 510endchoice 511 512config ARM64_VA_BITS 513 int 514 default 36 if ARM64_VA_BITS_36 515 default 39 if ARM64_VA_BITS_39 516 default 42 if ARM64_VA_BITS_42 517 default 47 if ARM64_VA_BITS_47 518 default 48 if ARM64_VA_BITS_48 519 520config CPU_BIG_ENDIAN 521 bool "Build big-endian kernel" 522 help 523 Say Y if you plan on running a kernel in big-endian mode. 524 525config SCHED_MC 526 bool "Multi-core scheduler support" 527 help 528 Multi-core scheduler support improves the CPU scheduler's decision 529 making when dealing with multi-core CPU chips at a cost of slightly 530 increased overhead in some places. If unsure say N here. 531 532config SCHED_SMT 533 bool "SMT scheduler support" 534 help 535 Improves the CPU scheduler's decision making when dealing with 536 MultiThreading at a cost of slightly increased overhead in some 537 places. If unsure say N here. 538 539config NR_CPUS 540 int "Maximum number of CPUs (2-4096)" 541 range 2 4096 542 # These have to remain sorted largest to smallest 543 default "64" 544 545config HOTPLUG_CPU 546 bool "Support for hot-pluggable CPUs" 547 select GENERIC_IRQ_MIGRATION 548 help 549 Say Y here to experiment with turning CPUs off and on. CPUs 550 can be controlled through /sys/devices/system/cpu. 551 552# Common NUMA Features 553config NUMA 554 bool "Numa Memory Allocation and Scheduler Support" 555 depends on SMP 556 help 557 Enable NUMA (Non Uniform Memory Access) support. 558 559 The kernel will try to allocate memory used by a CPU on the 560 local memory of the CPU and add some more 561 NUMA awareness to the kernel. 562 563config NODES_SHIFT 564 int "Maximum NUMA Nodes (as a power of 2)" 565 range 1 10 566 default "2" 567 depends on NEED_MULTIPLE_NODES 568 help 569 Specify the maximum number of NUMA Nodes available on the target 570 system. Increases memory reserved to accommodate various tables. 571 572config USE_PERCPU_NUMA_NODE_ID 573 def_bool y 574 depends on NUMA 575 576source kernel/Kconfig.preempt 577source kernel/Kconfig.hz 578 579config ARCH_SUPPORTS_DEBUG_PAGEALLOC 580 depends on !HIBERNATION 581 def_bool y 582 583config ARCH_HAS_HOLES_MEMORYMODEL 584 def_bool y if SPARSEMEM 585 586config ARCH_SPARSEMEM_ENABLE 587 def_bool y 588 select SPARSEMEM_VMEMMAP_ENABLE 589 590config ARCH_SPARSEMEM_DEFAULT 591 def_bool ARCH_SPARSEMEM_ENABLE 592 593config ARCH_SELECT_MEMORY_MODEL 594 def_bool ARCH_SPARSEMEM_ENABLE 595 596config HAVE_ARCH_PFN_VALID 597 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 598 599config HW_PERF_EVENTS 600 def_bool y 601 depends on ARM_PMU 602 603config SYS_SUPPORTS_HUGETLBFS 604 def_bool y 605 606config ARCH_WANT_HUGE_PMD_SHARE 607 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 608 609config ARCH_HAS_CACHE_LINE_SIZE 610 def_bool y 611 612source "mm/Kconfig" 613 614config SECCOMP 615 bool "Enable seccomp to safely compute untrusted bytecode" 616 ---help--- 617 This kernel feature is useful for number crunching applications 618 that may need to compute untrusted bytecode during their 619 execution. By using pipes or other transports made available to 620 the process as file descriptors supporting the read/write 621 syscalls, it's possible to isolate those applications in 622 their own address space using seccomp. Once seccomp is 623 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 624 and the task is only allowed to execute a few safe syscalls 625 defined by each seccomp mode. 626 627config PARAVIRT 628 bool "Enable paravirtualization code" 629 help 630 This changes the kernel so it can modify itself when it is run 631 under a hypervisor, potentially improving performance significantly 632 over full virtualization. 633 634config PARAVIRT_TIME_ACCOUNTING 635 bool "Paravirtual steal time accounting" 636 select PARAVIRT 637 default n 638 help 639 Select this option to enable fine granularity task steal time 640 accounting. Time spent executing other tasks in parallel with 641 the current vCPU is discounted from the vCPU power. To account for 642 that, there can be a small performance impact. 643 644 If in doubt, say N here. 645 646config XEN_DOM0 647 def_bool y 648 depends on XEN 649 650config XEN 651 bool "Xen guest support on ARM64" 652 depends on ARM64 && OF 653 select SWIOTLB_XEN 654 select PARAVIRT 655 help 656 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 657 658config FORCE_MAX_ZONEORDER 659 int 660 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 661 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 662 default "11" 663 help 664 The kernel memory allocator divides physically contiguous memory 665 blocks into "zones", where each zone is a power of two number of 666 pages. This option selects the largest power of two that the kernel 667 keeps in the memory allocator. If you need to allocate very large 668 blocks of physically contiguous memory, then you may need to 669 increase this value. 670 671 This config option is actually maximum order plus one. For example, 672 a value of 11 means that the largest free memory block is 2^10 pages. 673 674 We make sure that we can allocate upto a HugePage size for each configuration. 675 Hence we have : 676 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 677 678 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 679 4M allocations matching the default size used by generic code. 680 681menuconfig ARMV8_DEPRECATED 682 bool "Emulate deprecated/obsolete ARMv8 instructions" 683 depends on COMPAT 684 help 685 Legacy software support may require certain instructions 686 that have been deprecated or obsoleted in the architecture. 687 688 Enable this config to enable selective emulation of these 689 features. 690 691 If unsure, say Y 692 693if ARMV8_DEPRECATED 694 695config SWP_EMULATION 696 bool "Emulate SWP/SWPB instructions" 697 help 698 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 699 they are always undefined. Say Y here to enable software 700 emulation of these instructions for userspace using LDXR/STXR. 701 702 In some older versions of glibc [<=2.8] SWP is used during futex 703 trylock() operations with the assumption that the code will not 704 be preempted. This invalid assumption may be more likely to fail 705 with SWP emulation enabled, leading to deadlock of the user 706 application. 707 708 NOTE: when accessing uncached shared regions, LDXR/STXR rely 709 on an external transaction monitoring block called a global 710 monitor to maintain update atomicity. If your system does not 711 implement a global monitor, this option can cause programs that 712 perform SWP operations to uncached memory to deadlock. 713 714 If unsure, say Y 715 716config CP15_BARRIER_EMULATION 717 bool "Emulate CP15 Barrier instructions" 718 help 719 The CP15 barrier instructions - CP15ISB, CP15DSB, and 720 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 721 strongly recommended to use the ISB, DSB, and DMB 722 instructions instead. 723 724 Say Y here to enable software emulation of these 725 instructions for AArch32 userspace code. When this option is 726 enabled, CP15 barrier usage is traced which can help 727 identify software that needs updating. 728 729 If unsure, say Y 730 731config SETEND_EMULATION 732 bool "Emulate SETEND instruction" 733 help 734 The SETEND instruction alters the data-endianness of the 735 AArch32 EL0, and is deprecated in ARMv8. 736 737 Say Y here to enable software emulation of the instruction 738 for AArch32 userspace code. 739 740 Note: All the cpus on the system must have mixed endian support at EL0 741 for this feature to be enabled. If a new CPU - which doesn't support mixed 742 endian - is hotplugged in after this feature has been enabled, there could 743 be unexpected results in the applications. 744 745 If unsure, say Y 746endif 747 748menu "ARMv8.1 architectural features" 749 750config ARM64_HW_AFDBM 751 bool "Support for hardware updates of the Access and Dirty page flags" 752 default y 753 help 754 The ARMv8.1 architecture extensions introduce support for 755 hardware updates of the access and dirty information in page 756 table entries. When enabled in TCR_EL1 (HA and HD bits) on 757 capable processors, accesses to pages with PTE_AF cleared will 758 set this bit instead of raising an access flag fault. 759 Similarly, writes to read-only pages with the DBM bit set will 760 clear the read-only bit (AP[2]) instead of raising a 761 permission fault. 762 763 Kernels built with this configuration option enabled continue 764 to work on pre-ARMv8.1 hardware and the performance impact is 765 minimal. If unsure, say Y. 766 767config ARM64_PAN 768 bool "Enable support for Privileged Access Never (PAN)" 769 default y 770 help 771 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 772 prevents the kernel or hypervisor from accessing user-space (EL0) 773 memory directly. 774 775 Choosing this option will cause any unprotected (not using 776 copy_to_user et al) memory access to fail with a permission fault. 777 778 The feature is detected at runtime, and will remain as a 'nop' 779 instruction if the cpu does not implement the feature. 780 781config ARM64_LSE_ATOMICS 782 bool "Atomic instructions" 783 help 784 As part of the Large System Extensions, ARMv8.1 introduces new 785 atomic instructions that are designed specifically to scale in 786 very large systems. 787 788 Say Y here to make use of these instructions for the in-kernel 789 atomic routines. This incurs a small overhead on CPUs that do 790 not support these instructions and requires the kernel to be 791 built with binutils >= 2.25. 792 793config ARM64_VHE 794 bool "Enable support for Virtualization Host Extensions (VHE)" 795 default y 796 help 797 Virtualization Host Extensions (VHE) allow the kernel to run 798 directly at EL2 (instead of EL1) on processors that support 799 it. This leads to better performance for KVM, as they reduce 800 the cost of the world switch. 801 802 Selecting this option allows the VHE feature to be detected 803 at runtime, and does not affect processors that do not 804 implement this feature. 805 806endmenu 807 808menu "ARMv8.2 architectural features" 809 810config ARM64_UAO 811 bool "Enable support for User Access Override (UAO)" 812 default y 813 help 814 User Access Override (UAO; part of the ARMv8.2 Extensions) 815 causes the 'unprivileged' variant of the load/store instructions to 816 be overriden to be privileged. 817 818 This option changes get_user() and friends to use the 'unprivileged' 819 variant of the load/store instructions. This ensures that user-space 820 really did have access to the supplied memory. When addr_limit is 821 set to kernel memory the UAO bit will be set, allowing privileged 822 access to kernel memory. 823 824 Choosing this option will cause copy_to_user() et al to use user-space 825 memory permissions. 826 827 The feature is detected at runtime, the kernel will use the 828 regular load/store instructions if the cpu does not implement the 829 feature. 830 831endmenu 832 833config ARM64_MODULE_CMODEL_LARGE 834 bool 835 836config ARM64_MODULE_PLTS 837 bool 838 select ARM64_MODULE_CMODEL_LARGE 839 select HAVE_MOD_ARCH_SPECIFIC 840 841config RELOCATABLE 842 bool 843 help 844 This builds the kernel as a Position Independent Executable (PIE), 845 which retains all relocation metadata required to relocate the 846 kernel binary at runtime to a different virtual address than the 847 address it was linked at. 848 Since AArch64 uses the RELA relocation format, this requires a 849 relocation pass at runtime even if the kernel is loaded at the 850 same address it was linked at. 851 852config RANDOMIZE_BASE 853 bool "Randomize the address of the kernel image" 854 select ARM64_MODULE_PLTS 855 select RELOCATABLE 856 help 857 Randomizes the virtual address at which the kernel image is 858 loaded, as a security feature that deters exploit attempts 859 relying on knowledge of the location of kernel internals. 860 861 It is the bootloader's job to provide entropy, by passing a 862 random u64 value in /chosen/kaslr-seed at kernel entry. 863 864 When booting via the UEFI stub, it will invoke the firmware's 865 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 866 to the kernel proper. In addition, it will randomise the physical 867 location of the kernel Image as well. 868 869 If unsure, say N. 870 871config RANDOMIZE_MODULE_REGION_FULL 872 bool "Randomize the module region independently from the core kernel" 873 depends on RANDOMIZE_BASE 874 default y 875 help 876 Randomizes the location of the module region without considering the 877 location of the core kernel. This way, it is impossible for modules 878 to leak information about the location of core kernel data structures 879 but it does imply that function calls between modules and the core 880 kernel will need to be resolved via veneers in the module PLT. 881 882 When this option is not set, the module region will be randomized over 883 a limited range that contains the [_stext, _etext] interval of the 884 core kernel, so branch relocations are always in range. 885 886endmenu 887 888menu "Boot options" 889 890config ARM64_ACPI_PARKING_PROTOCOL 891 bool "Enable support for the ARM64 ACPI parking protocol" 892 depends on ACPI 893 help 894 Enable support for the ARM64 ACPI parking protocol. If disabled 895 the kernel will not allow booting through the ARM64 ACPI parking 896 protocol even if the corresponding data is present in the ACPI 897 MADT table. 898 899config CMDLINE 900 string "Default kernel command string" 901 default "" 902 help 903 Provide a set of default command-line options at build time by 904 entering them here. As a minimum, you should specify the the 905 root device (e.g. root=/dev/nfs). 906 907config CMDLINE_FORCE 908 bool "Always use the default kernel command string" 909 help 910 Always use the default kernel command string, even if the boot 911 loader passes other arguments to the kernel. 912 This is useful if you cannot or don't want to change the 913 command-line options your boot loader passes to the kernel. 914 915config EFI_STUB 916 bool 917 918config EFI 919 bool "UEFI runtime support" 920 depends on OF && !CPU_BIG_ENDIAN 921 select LIBFDT 922 select UCS2_STRING 923 select EFI_PARAMS_FROM_FDT 924 select EFI_RUNTIME_WRAPPERS 925 select EFI_STUB 926 select EFI_ARMSTUB 927 default y 928 help 929 This option provides support for runtime services provided 930 by UEFI firmware (such as non-volatile variables, realtime 931 clock, and platform reset). A UEFI stub is also provided to 932 allow the kernel to be booted as an EFI application. This 933 is only useful on systems that have UEFI firmware. 934 935config DMI 936 bool "Enable support for SMBIOS (DMI) tables" 937 depends on EFI 938 default y 939 help 940 This enables SMBIOS/DMI feature for systems. 941 942 This option is only useful on systems that have UEFI firmware. 943 However, even with this option, the resultant kernel should 944 continue to boot on existing non-UEFI platforms. 945 946endmenu 947 948menu "Userspace binary formats" 949 950source "fs/Kconfig.binfmt" 951 952config COMPAT 953 bool "Kernel support for 32-bit EL0" 954 depends on ARM64_4K_PAGES || EXPERT 955 select COMPAT_BINFMT_ELF 956 select HAVE_UID16 957 select OLD_SIGSUSPEND3 958 select COMPAT_OLD_SIGACTION 959 help 960 This option enables support for a 32-bit EL0 running under a 64-bit 961 kernel at EL1. AArch32-specific components such as system calls, 962 the user helper functions, VFP support and the ptrace interface are 963 handled appropriately by the kernel. 964 965 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 966 that you will only be able to execute AArch32 binaries that were compiled 967 with page size aligned segments. 968 969 If you want to execute 32-bit userspace applications, say Y. 970 971config SYSVIPC_COMPAT 972 def_bool y 973 depends on COMPAT && SYSVIPC 974 975endmenu 976 977menu "Power management options" 978 979source "kernel/power/Kconfig" 980 981config ARCH_HIBERNATION_POSSIBLE 982 def_bool y 983 depends on CPU_PM 984 985config ARCH_HIBERNATION_HEADER 986 def_bool y 987 depends on HIBERNATION 988 989config ARCH_SUSPEND_POSSIBLE 990 def_bool y 991 992endmenu 993 994menu "CPU Power Management" 995 996source "drivers/cpuidle/Kconfig" 997 998source "drivers/cpufreq/Kconfig" 999 1000endmenu 1001 1002source "net/Kconfig" 1003 1004source "drivers/Kconfig" 1005 1006source "drivers/firmware/Kconfig" 1007 1008source "drivers/acpi/Kconfig" 1009 1010source "fs/Kconfig" 1011 1012source "arch/arm64/kvm/Kconfig" 1013 1014source "arch/arm64/Kconfig.debug" 1015 1016source "security/Kconfig" 1017 1018source "crypto/Kconfig" 1019if CRYPTO 1020source "arch/arm64/crypto/Kconfig" 1021endif 1022 1023source "lib/Kconfig" 1024