1config ARM64 2 def_bool y 3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_GCOV_PROFILE_ALL 6 select ARCH_HAS_SG_CHAIN 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_USE_CMPXCHG_LOCKREF 9 select ARCH_SUPPORTS_ATOMIC_RMW 10 select ARCH_WANT_OPTIONAL_GPIOLIB 11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 12 select ARCH_WANT_FRAME_POINTERS 13 select ARM_AMBA 14 select ARM_ARCH_TIMER 15 select ARM_GIC 16 select AUDIT_ARCH_COMPAT_GENERIC 17 select ARM_GIC_V2M if PCI_MSI 18 select ARM_GIC_V3 19 select ARM_GIC_V3_ITS if PCI_MSI 20 select BUILDTIME_EXTABLE_SORT 21 select CLONE_BACKWARDS 22 select COMMON_CLK 23 select CPU_PM if (SUSPEND || CPU_IDLE) 24 select DCACHE_WORD_ACCESS 25 select GENERIC_ALLOCATOR 26 select GENERIC_CLOCKEVENTS 27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 28 select GENERIC_CPU_AUTOPROBE 29 select GENERIC_EARLY_IOREMAP 30 select GENERIC_IRQ_PROBE 31 select GENERIC_IRQ_SHOW 32 select GENERIC_PCI_IOMAP 33 select GENERIC_SCHED_CLOCK 34 select GENERIC_SMP_IDLE_THREAD 35 select GENERIC_STRNCPY_FROM_USER 36 select GENERIC_STRNLEN_USER 37 select GENERIC_TIME_VSYSCALL 38 select HANDLE_DOMAIN_IRQ 39 select HARDIRQS_SW_RESEND 40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 41 select HAVE_ARCH_AUDITSYSCALL 42 select HAVE_ARCH_JUMP_LABEL 43 select HAVE_ARCH_KGDB 44 select HAVE_ARCH_SECCOMP_FILTER 45 select HAVE_ARCH_TRACEHOOK 46 select HAVE_BPF_JIT 47 select HAVE_C_RECORDMCOUNT 48 select HAVE_CC_STACKPROTECTOR 49 select HAVE_CMPXCHG_DOUBLE 50 select HAVE_DEBUG_BUGVERBOSE 51 select HAVE_DEBUG_KMEMLEAK 52 select HAVE_DMA_API_DEBUG 53 select HAVE_DMA_ATTRS 54 select HAVE_DMA_CONTIGUOUS 55 select HAVE_DYNAMIC_FTRACE 56 select HAVE_EFFICIENT_UNALIGNED_ACCESS 57 select HAVE_FTRACE_MCOUNT_RECORD 58 select HAVE_FUNCTION_TRACER 59 select HAVE_FUNCTION_GRAPH_TRACER 60 select HAVE_GENERIC_DMA_COHERENT 61 select HAVE_HW_BREAKPOINT if PERF_EVENTS 62 select HAVE_MEMBLOCK 63 select HAVE_PATA_PLATFORM 64 select HAVE_PERF_EVENTS 65 select HAVE_PERF_REGS 66 select HAVE_PERF_USER_STACK_DUMP 67 select HAVE_RCU_TABLE_FREE 68 select HAVE_SYSCALL_TRACEPOINTS 69 select IRQ_DOMAIN 70 select MODULES_USE_ELF_RELA 71 select NO_BOOTMEM 72 select OF 73 select OF_EARLY_FLATTREE 74 select OF_RESERVED_MEM 75 select PERF_USE_VMALLOC 76 select POWER_RESET 77 select POWER_SUPPLY 78 select RTC_LIB 79 select SPARSE_IRQ 80 select SYSCTL_EXCEPTION_TRACE 81 select HAVE_CONTEXT_TRACKING 82 help 83 ARM 64-bit (AArch64) Linux support. 84 85config 64BIT 86 def_bool y 87 88config ARCH_PHYS_ADDR_T_64BIT 89 def_bool y 90 91config MMU 92 def_bool y 93 94config NO_IOPORT_MAP 95 def_bool y if !PCI 96 97config STACKTRACE_SUPPORT 98 def_bool y 99 100config LOCKDEP_SUPPORT 101 def_bool y 102 103config TRACE_IRQFLAGS_SUPPORT 104 def_bool y 105 106config RWSEM_XCHGADD_ALGORITHM 107 def_bool y 108 109config GENERIC_HWEIGHT 110 def_bool y 111 112config GENERIC_CSUM 113 def_bool y 114 115config GENERIC_CALIBRATE_DELAY 116 def_bool y 117 118config ZONE_DMA 119 def_bool y 120 121config HAVE_GENERIC_RCU_GUP 122 def_bool y 123 124config ARCH_DMA_ADDR_T_64BIT 125 def_bool y 126 127config NEED_DMA_MAP_STATE 128 def_bool y 129 130config NEED_SG_DMA_LENGTH 131 def_bool y 132 133config SWIOTLB 134 def_bool y 135 136config IOMMU_HELPER 137 def_bool SWIOTLB 138 139config KERNEL_MODE_NEON 140 def_bool y 141 142config FIX_EARLYCON_MEM 143 def_bool y 144 145source "init/Kconfig" 146 147source "kernel/Kconfig.freezer" 148 149menu "Platform selection" 150 151config ARCH_SEATTLE 152 bool "AMD Seattle SoC Family" 153 help 154 This enables support for AMD Seattle SOC Family 155 156config ARCH_THUNDER 157 bool "Cavium Inc. Thunder SoC Family" 158 help 159 This enables support for Cavium's Thunder Family of SoCs. 160 161config ARCH_VEXPRESS 162 bool "ARMv8 software model (Versatile Express)" 163 select ARCH_REQUIRE_GPIOLIB 164 select COMMON_CLK_VERSATILE 165 select POWER_RESET_VEXPRESS 166 select VEXPRESS_CONFIG 167 help 168 This enables support for the ARMv8 software model (Versatile 169 Express). 170 171config ARCH_XGENE 172 bool "AppliedMicro X-Gene SOC Family" 173 help 174 This enables support for AppliedMicro X-Gene SOC Family 175 176endmenu 177 178menu "Bus support" 179 180config PCI 181 bool "PCI support" 182 help 183 This feature enables support for PCI bus system. If you say Y 184 here, the kernel will include drivers and infrastructure code 185 to support PCI bus devices. 186 187config PCI_DOMAINS 188 def_bool PCI 189 190config PCI_DOMAINS_GENERIC 191 def_bool PCI 192 193config PCI_SYSCALL 194 def_bool PCI 195 196source "drivers/pci/Kconfig" 197source "drivers/pci/pcie/Kconfig" 198source "drivers/pci/hotplug/Kconfig" 199 200endmenu 201 202menu "Kernel Features" 203 204menu "ARM errata workarounds via the alternatives framework" 205 206config ARM64_ERRATUM_826319 207 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 208 default y 209 help 210 This option adds an alternative code sequence to work around ARM 211 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 212 AXI master interface and an L2 cache. 213 214 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 215 and is unable to accept a certain write via this interface, it will 216 not progress on read data presented on the read data channel and the 217 system can deadlock. 218 219 The workaround promotes data cache clean instructions to 220 data cache clean-and-invalidate. 221 Please note that this does not necessarily enable the workaround, 222 as it depends on the alternative framework, which will only patch 223 the kernel if an affected CPU is detected. 224 225 If unsure, say Y. 226 227config ARM64_ERRATUM_827319 228 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 229 default y 230 help 231 This option adds an alternative code sequence to work around ARM 232 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 233 master interface and an L2 cache. 234 235 Under certain conditions this erratum can cause a clean line eviction 236 to occur at the same time as another transaction to the same address 237 on the AMBA 5 CHI interface, which can cause data corruption if the 238 interconnect reorders the two transactions. 239 240 The workaround promotes data cache clean instructions to 241 data cache clean-and-invalidate. 242 Please note that this does not necessarily enable the workaround, 243 as it depends on the alternative framework, which will only patch 244 the kernel if an affected CPU is detected. 245 246 If unsure, say Y. 247 248config ARM64_ERRATUM_824069 249 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 250 default y 251 help 252 This option adds an alternative code sequence to work around ARM 253 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 254 to a coherent interconnect. 255 256 If a Cortex-A53 processor is executing a store or prefetch for 257 write instruction at the same time as a processor in another 258 cluster is executing a cache maintenance operation to the same 259 address, then this erratum might cause a clean cache line to be 260 incorrectly marked as dirty. 261 262 The workaround promotes data cache clean instructions to 263 data cache clean-and-invalidate. 264 Please note that this option does not necessarily enable the 265 workaround, as it depends on the alternative framework, which will 266 only patch the kernel if an affected CPU is detected. 267 268 If unsure, say Y. 269 270config ARM64_ERRATUM_819472 271 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 272 default y 273 help 274 This option adds an alternative code sequence to work around ARM 275 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 276 present when it is connected to a coherent interconnect. 277 278 If the processor is executing a load and store exclusive sequence at 279 the same time as a processor in another cluster is executing a cache 280 maintenance operation to the same address, then this erratum might 281 cause data corruption. 282 283 The workaround promotes data cache clean instructions to 284 data cache clean-and-invalidate. 285 Please note that this does not necessarily enable the workaround, 286 as it depends on the alternative framework, which will only patch 287 the kernel if an affected CPU is detected. 288 289 If unsure, say Y. 290 291config ARM64_ERRATUM_832075 292 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 293 default y 294 help 295 This option adds an alternative code sequence to work around ARM 296 erratum 832075 on Cortex-A57 parts up to r1p2. 297 298 Affected Cortex-A57 parts might deadlock when exclusive load/store 299 instructions to Write-Back memory are mixed with Device loads. 300 301 The workaround is to promote device loads to use Load-Acquire 302 semantics. 303 Please note that this does not necessarily enable the workaround, 304 as it depends on the alternative framework, which will only patch 305 the kernel if an affected CPU is detected. 306 307 If unsure, say Y. 308 309endmenu 310 311 312choice 313 prompt "Page size" 314 default ARM64_4K_PAGES 315 help 316 Page size (translation granule) configuration. 317 318config ARM64_4K_PAGES 319 bool "4KB" 320 help 321 This feature enables 4KB pages support. 322 323config ARM64_64K_PAGES 324 bool "64KB" 325 help 326 This feature enables 64KB pages support (4KB by default) 327 allowing only two levels of page tables and faster TLB 328 look-up. AArch32 emulation is not available when this feature 329 is enabled. 330 331endchoice 332 333choice 334 prompt "Virtual address space size" 335 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 336 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 337 help 338 Allows choosing one of multiple possible virtual address 339 space sizes. The level of translation table is determined by 340 a combination of page size and virtual address space size. 341 342config ARM64_VA_BITS_39 343 bool "39-bit" 344 depends on ARM64_4K_PAGES 345 346config ARM64_VA_BITS_42 347 bool "42-bit" 348 depends on ARM64_64K_PAGES 349 350config ARM64_VA_BITS_48 351 bool "48-bit" 352 depends on !ARM_SMMU 353 354endchoice 355 356config ARM64_VA_BITS 357 int 358 default 39 if ARM64_VA_BITS_39 359 default 42 if ARM64_VA_BITS_42 360 default 48 if ARM64_VA_BITS_48 361 362config ARM64_PGTABLE_LEVELS 363 int 364 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 365 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 366 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 367 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 368 369config CPU_BIG_ENDIAN 370 bool "Build big-endian kernel" 371 help 372 Say Y if you plan on running a kernel in big-endian mode. 373 374config SMP 375 bool "Symmetric Multi-Processing" 376 help 377 This enables support for systems with more than one CPU. If 378 you say N here, the kernel will run on single and 379 multiprocessor machines, but will use only one CPU of a 380 multiprocessor machine. If you say Y here, the kernel will run 381 on many, but not all, single processor machines. On a single 382 processor machine, the kernel will run faster if you say N 383 here. 384 385 If you don't know what to do here, say N. 386 387config SCHED_MC 388 bool "Multi-core scheduler support" 389 depends on SMP 390 help 391 Multi-core scheduler support improves the CPU scheduler's decision 392 making when dealing with multi-core CPU chips at a cost of slightly 393 increased overhead in some places. If unsure say N here. 394 395config SCHED_SMT 396 bool "SMT scheduler support" 397 depends on SMP 398 help 399 Improves the CPU scheduler's decision making when dealing with 400 MultiThreading at a cost of slightly increased overhead in some 401 places. If unsure say N here. 402 403config NR_CPUS 404 int "Maximum number of CPUs (2-64)" 405 range 2 64 406 depends on SMP 407 # These have to remain sorted largest to smallest 408 default "64" 409 410config HOTPLUG_CPU 411 bool "Support for hot-pluggable CPUs" 412 depends on SMP 413 help 414 Say Y here to experiment with turning CPUs off and on. CPUs 415 can be controlled through /sys/devices/system/cpu. 416 417source kernel/Kconfig.preempt 418 419config HZ 420 int 421 default 100 422 423config ARCH_HAS_HOLES_MEMORYMODEL 424 def_bool y if SPARSEMEM 425 426config ARCH_SPARSEMEM_ENABLE 427 def_bool y 428 select SPARSEMEM_VMEMMAP_ENABLE 429 430config ARCH_SPARSEMEM_DEFAULT 431 def_bool ARCH_SPARSEMEM_ENABLE 432 433config ARCH_SELECT_MEMORY_MODEL 434 def_bool ARCH_SPARSEMEM_ENABLE 435 436config HAVE_ARCH_PFN_VALID 437 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 438 439config HW_PERF_EVENTS 440 bool "Enable hardware performance counter support for perf events" 441 depends on PERF_EVENTS 442 default y 443 help 444 Enable hardware performance counter support for perf events. If 445 disabled, perf events will use software events only. 446 447config SYS_SUPPORTS_HUGETLBFS 448 def_bool y 449 450config ARCH_WANT_GENERAL_HUGETLB 451 def_bool y 452 453config ARCH_WANT_HUGE_PMD_SHARE 454 def_bool y if !ARM64_64K_PAGES 455 456config HAVE_ARCH_TRANSPARENT_HUGEPAGE 457 def_bool y 458 459config ARCH_HAS_CACHE_LINE_SIZE 460 def_bool y 461 462source "mm/Kconfig" 463 464config SECCOMP 465 bool "Enable seccomp to safely compute untrusted bytecode" 466 ---help--- 467 This kernel feature is useful for number crunching applications 468 that may need to compute untrusted bytecode during their 469 execution. By using pipes or other transports made available to 470 the process as file descriptors supporting the read/write 471 syscalls, it's possible to isolate those applications in 472 their own address space using seccomp. Once seccomp is 473 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 474 and the task is only allowed to execute a few safe syscalls 475 defined by each seccomp mode. 476 477config XEN_DOM0 478 def_bool y 479 depends on XEN 480 481config XEN 482 bool "Xen guest support on ARM64" 483 depends on ARM64 && OF 484 select SWIOTLB_XEN 485 help 486 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 487 488config FORCE_MAX_ZONEORDER 489 int 490 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 491 default "11" 492 493menuconfig ARMV8_DEPRECATED 494 bool "Emulate deprecated/obsolete ARMv8 instructions" 495 depends on COMPAT 496 help 497 Legacy software support may require certain instructions 498 that have been deprecated or obsoleted in the architecture. 499 500 Enable this config to enable selective emulation of these 501 features. 502 503 If unsure, say Y 504 505if ARMV8_DEPRECATED 506 507config SWP_EMULATION 508 bool "Emulate SWP/SWPB instructions" 509 help 510 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 511 they are always undefined. Say Y here to enable software 512 emulation of these instructions for userspace using LDXR/STXR. 513 514 In some older versions of glibc [<=2.8] SWP is used during futex 515 trylock() operations with the assumption that the code will not 516 be preempted. This invalid assumption may be more likely to fail 517 with SWP emulation enabled, leading to deadlock of the user 518 application. 519 520 NOTE: when accessing uncached shared regions, LDXR/STXR rely 521 on an external transaction monitoring block called a global 522 monitor to maintain update atomicity. If your system does not 523 implement a global monitor, this option can cause programs that 524 perform SWP operations to uncached memory to deadlock. 525 526 If unsure, say Y 527 528config CP15_BARRIER_EMULATION 529 bool "Emulate CP15 Barrier instructions" 530 help 531 The CP15 barrier instructions - CP15ISB, CP15DSB, and 532 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 533 strongly recommended to use the ISB, DSB, and DMB 534 instructions instead. 535 536 Say Y here to enable software emulation of these 537 instructions for AArch32 userspace code. When this option is 538 enabled, CP15 barrier usage is traced which can help 539 identify software that needs updating. 540 541 If unsure, say Y 542 543endif 544 545endmenu 546 547menu "Boot options" 548 549config CMDLINE 550 string "Default kernel command string" 551 default "" 552 help 553 Provide a set of default command-line options at build time by 554 entering them here. As a minimum, you should specify the the 555 root device (e.g. root=/dev/nfs). 556 557config CMDLINE_FORCE 558 bool "Always use the default kernel command string" 559 help 560 Always use the default kernel command string, even if the boot 561 loader passes other arguments to the kernel. 562 This is useful if you cannot or don't want to change the 563 command-line options your boot loader passes to the kernel. 564 565config EFI_STUB 566 bool 567 568config EFI 569 bool "UEFI runtime support" 570 depends on OF && !CPU_BIG_ENDIAN 571 select LIBFDT 572 select UCS2_STRING 573 select EFI_PARAMS_FROM_FDT 574 select EFI_RUNTIME_WRAPPERS 575 select EFI_STUB 576 select EFI_ARMSTUB 577 default y 578 help 579 This option provides support for runtime services provided 580 by UEFI firmware (such as non-volatile variables, realtime 581 clock, and platform reset). A UEFI stub is also provided to 582 allow the kernel to be booted as an EFI application. This 583 is only useful on systems that have UEFI firmware. 584 585config DMI 586 bool "Enable support for SMBIOS (DMI) tables" 587 depends on EFI 588 default y 589 help 590 This enables SMBIOS/DMI feature for systems. 591 592 This option is only useful on systems that have UEFI firmware. 593 However, even with this option, the resultant kernel should 594 continue to boot on existing non-UEFI platforms. 595 596endmenu 597 598menu "Userspace binary formats" 599 600source "fs/Kconfig.binfmt" 601 602config COMPAT 603 bool "Kernel support for 32-bit EL0" 604 depends on !ARM64_64K_PAGES 605 select COMPAT_BINFMT_ELF 606 select HAVE_UID16 607 select OLD_SIGSUSPEND3 608 select COMPAT_OLD_SIGACTION 609 help 610 This option enables support for a 32-bit EL0 running under a 64-bit 611 kernel at EL1. AArch32-specific components such as system calls, 612 the user helper functions, VFP support and the ptrace interface are 613 handled appropriately by the kernel. 614 615 If you want to execute 32-bit userspace applications, say Y. 616 617config SYSVIPC_COMPAT 618 def_bool y 619 depends on COMPAT && SYSVIPC 620 621endmenu 622 623menu "Power management options" 624 625source "kernel/power/Kconfig" 626 627config ARCH_SUSPEND_POSSIBLE 628 def_bool y 629 630config ARM64_CPU_SUSPEND 631 def_bool PM_SLEEP 632 633endmenu 634 635menu "CPU Power Management" 636 637source "drivers/cpuidle/Kconfig" 638 639source "drivers/cpufreq/Kconfig" 640 641endmenu 642 643source "net/Kconfig" 644 645source "drivers/Kconfig" 646 647source "drivers/firmware/Kconfig" 648 649source "fs/Kconfig" 650 651source "arch/arm64/kvm/Kconfig" 652 653source "arch/arm64/Kconfig.debug" 654 655source "security/Kconfig" 656 657source "crypto/Kconfig" 658if CRYPTO 659source "arch/arm64/crypto/Kconfig" 660endif 661 662source "lib/Kconfig" 663