1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_HAVE_TRACE_MMIO_ACCESS 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 97 select ARCH_WANT_DEFAULT_BPF_JIT 98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 99 select ARCH_WANT_FRAME_POINTERS 100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 102 select ARCH_WANT_LD_ORPHAN_WARN 103 select ARCH_WANTS_NO_INSTR 104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 105 select ARCH_HAS_UBSAN_SANITIZE_ALL 106 select ARM_AMBA 107 select ARM_ARCH_TIMER 108 select ARM_GIC 109 select AUDIT_ARCH_COMPAT_GENERIC 110 select ARM_GIC_V2M if PCI 111 select ARM_GIC_V3 112 select ARM_GIC_V3_ITS if PCI 113 select ARM_PSCI_FW 114 select BUILDTIME_TABLE_SORT 115 select CLONE_BACKWARDS 116 select COMMON_CLK 117 select CPU_PM if (SUSPEND || CPU_IDLE) 118 select CRC32 119 select DCACHE_WORD_ACCESS 120 select DMA_DIRECT_REMAP 121 select EDAC_SUPPORT 122 select FRAME_POINTER 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_VULNERABILITIES 128 select GENERIC_EARLY_IOREMAP 129 select GENERIC_IDLE_POLL_SETUP 130 select GENERIC_IOREMAP 131 select GENERIC_IRQ_IPI 132 select GENERIC_IRQ_PROBE 133 select GENERIC_IRQ_SHOW 134 select GENERIC_IRQ_SHOW_LEVEL 135 select GENERIC_LIB_DEVMEM_IS_ALLOWED 136 select GENERIC_PCI_IOMAP 137 select GENERIC_PTDUMP 138 select GENERIC_SCHED_CLOCK 139 select GENERIC_SMP_IDLE_THREAD 140 select GENERIC_TIME_VSYSCALL 141 select GENERIC_GETTIMEOFDAY 142 select GENERIC_VDSO_TIME_NS 143 select HARDIRQS_SW_RESEND 144 select HAVE_MOVE_PMD 145 select HAVE_MOVE_PUD 146 select HAVE_PCI 147 select HAVE_ACPI_APEI if (ACPI && EFI) 148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 149 select HAVE_ARCH_AUDITSYSCALL 150 select HAVE_ARCH_BITREVERSE 151 select HAVE_ARCH_COMPILER_H 152 select HAVE_ARCH_HUGE_VMALLOC 153 select HAVE_ARCH_HUGE_VMAP 154 select HAVE_ARCH_JUMP_LABEL 155 select HAVE_ARCH_JUMP_LABEL_RELATIVE 156 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 157 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 158 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 159 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 160 # Some instrumentation may be unsound, hence EXPERT 161 select HAVE_ARCH_KCSAN if EXPERT 162 select HAVE_ARCH_KFENCE 163 select HAVE_ARCH_KGDB 164 select HAVE_ARCH_MMAP_RND_BITS 165 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 166 select HAVE_ARCH_PREL32_RELOCATIONS 167 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 168 select HAVE_ARCH_SECCOMP_FILTER 169 select HAVE_ARCH_STACKLEAK 170 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 171 select HAVE_ARCH_TRACEHOOK 172 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 173 select HAVE_ARCH_VMAP_STACK 174 select HAVE_ARM_SMCCC 175 select HAVE_ASM_MODVERSIONS 176 select HAVE_EBPF_JIT 177 select HAVE_C_RECORDMCOUNT 178 select HAVE_CMPXCHG_DOUBLE 179 select HAVE_CMPXCHG_LOCAL 180 select HAVE_CONTEXT_TRACKING_USER 181 select HAVE_DEBUG_KMEMLEAK 182 select HAVE_DMA_CONTIGUOUS 183 select HAVE_DYNAMIC_FTRACE 184 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 185 if DYNAMIC_FTRACE_WITH_REGS 186 select HAVE_EFFICIENT_UNALIGNED_ACCESS 187 select HAVE_FAST_GUP 188 select HAVE_FTRACE_MCOUNT_RECORD 189 select HAVE_FUNCTION_TRACER 190 select HAVE_FUNCTION_ERROR_INJECTION 191 select HAVE_FUNCTION_GRAPH_TRACER 192 select HAVE_GCC_PLUGINS 193 select HAVE_HW_BREAKPOINT if PERF_EVENTS 194 select HAVE_IOREMAP_PROT 195 select HAVE_IRQ_TIME_ACCOUNTING 196 select HAVE_KVM 197 select HAVE_NMI 198 select HAVE_PERF_EVENTS 199 select HAVE_PERF_REGS 200 select HAVE_PERF_USER_STACK_DUMP 201 select HAVE_PREEMPT_DYNAMIC_KEY 202 select HAVE_REGS_AND_STACK_ACCESS_API 203 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 204 select HAVE_FUNCTION_ARG_ACCESS_API 205 select MMU_GATHER_RCU_TABLE_FREE 206 select HAVE_RSEQ 207 select HAVE_STACKPROTECTOR 208 select HAVE_SYSCALL_TRACEPOINTS 209 select HAVE_KPROBES 210 select HAVE_KRETPROBES 211 select HAVE_GENERIC_VDSO 212 select IRQ_DOMAIN 213 select IRQ_FORCED_THREADING 214 select KASAN_VMALLOC if KASAN 215 select MODULES_USE_ELF_RELA 216 select NEED_DMA_MAP_STATE 217 select NEED_SG_DMA_LENGTH 218 select OF 219 select OF_EARLY_FLATTREE 220 select PCI_DOMAINS_GENERIC if PCI 221 select PCI_ECAM if (ACPI && PCI) 222 select PCI_SYSCALL if PCI 223 select POWER_RESET 224 select POWER_SUPPLY 225 select SPARSE_IRQ 226 select SWIOTLB 227 select SYSCTL_EXCEPTION_TRACE 228 select THREAD_INFO_IN_TASK 229 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 230 select TRACE_IRQFLAGS_SUPPORT 231 select TRACE_IRQFLAGS_NMI_SUPPORT 232 select HAVE_SOFTIRQ_ON_OWN_STACK 233 help 234 ARM 64-bit (AArch64) Linux support. 235 236config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 237 def_bool CC_IS_CLANG 238 # https://github.com/ClangBuiltLinux/linux/issues/1507 239 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 240 select HAVE_DYNAMIC_FTRACE_WITH_REGS 241 242config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 243 def_bool CC_IS_GCC 244 depends on $(cc-option,-fpatchable-function-entry=2) 245 select HAVE_DYNAMIC_FTRACE_WITH_REGS 246 247config 64BIT 248 def_bool y 249 250config MMU 251 def_bool y 252 253config ARM64_PAGE_SHIFT 254 int 255 default 16 if ARM64_64K_PAGES 256 default 14 if ARM64_16K_PAGES 257 default 12 258 259config ARM64_CONT_PTE_SHIFT 260 int 261 default 5 if ARM64_64K_PAGES 262 default 7 if ARM64_16K_PAGES 263 default 4 264 265config ARM64_CONT_PMD_SHIFT 266 int 267 default 5 if ARM64_64K_PAGES 268 default 5 if ARM64_16K_PAGES 269 default 4 270 271config ARCH_MMAP_RND_BITS_MIN 272 default 14 if ARM64_64K_PAGES 273 default 16 if ARM64_16K_PAGES 274 default 18 275 276# max bits determined by the following formula: 277# VA_BITS - PAGE_SHIFT - 3 278config ARCH_MMAP_RND_BITS_MAX 279 default 19 if ARM64_VA_BITS=36 280 default 24 if ARM64_VA_BITS=39 281 default 27 if ARM64_VA_BITS=42 282 default 30 if ARM64_VA_BITS=47 283 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 284 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 285 default 33 if ARM64_VA_BITS=48 286 default 14 if ARM64_64K_PAGES 287 default 16 if ARM64_16K_PAGES 288 default 18 289 290config ARCH_MMAP_RND_COMPAT_BITS_MIN 291 default 7 if ARM64_64K_PAGES 292 default 9 if ARM64_16K_PAGES 293 default 11 294 295config ARCH_MMAP_RND_COMPAT_BITS_MAX 296 default 16 297 298config NO_IOPORT_MAP 299 def_bool y if !PCI 300 301config STACKTRACE_SUPPORT 302 def_bool y 303 304config ILLEGAL_POINTER_VALUE 305 hex 306 default 0xdead000000000000 307 308config LOCKDEP_SUPPORT 309 def_bool y 310 311config GENERIC_BUG 312 def_bool y 313 depends on BUG 314 315config GENERIC_BUG_RELATIVE_POINTERS 316 def_bool y 317 depends on GENERIC_BUG 318 319config GENERIC_HWEIGHT 320 def_bool y 321 322config GENERIC_CSUM 323 def_bool y 324 325config GENERIC_CALIBRATE_DELAY 326 def_bool y 327 328config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 329 def_bool y 330 331config SMP 332 def_bool y 333 334config KERNEL_MODE_NEON 335 def_bool y 336 337config FIX_EARLYCON_MEM 338 def_bool y 339 340config PGTABLE_LEVELS 341 int 342 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 343 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 344 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 345 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 346 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 347 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 348 349config ARCH_SUPPORTS_UPROBES 350 def_bool y 351 352config ARCH_PROC_KCORE_TEXT 353 def_bool y 354 355config BROKEN_GAS_INST 356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 357 358config KASAN_SHADOW_OFFSET 359 hex 360 depends on KASAN_GENERIC || KASAN_SW_TAGS 361 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 362 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 363 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 364 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 365 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 366 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 367 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 368 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 369 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 370 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 371 default 0xffffffffffffffff 372 373source "arch/arm64/Kconfig.platforms" 374 375menu "Kernel Features" 376 377menu "ARM errata workarounds via the alternatives framework" 378 379config ARM64_WORKAROUND_CLEAN_CACHE 380 bool 381 382config ARM64_ERRATUM_826319 383 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 384 default y 385 select ARM64_WORKAROUND_CLEAN_CACHE 386 help 387 This option adds an alternative code sequence to work around ARM 388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 389 AXI master interface and an L2 cache. 390 391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 392 and is unable to accept a certain write via this interface, it will 393 not progress on read data presented on the read data channel and the 394 system can deadlock. 395 396 The workaround promotes data cache clean instructions to 397 data cache clean-and-invalidate. 398 Please note that this does not necessarily enable the workaround, 399 as it depends on the alternative framework, which will only patch 400 the kernel if an affected CPU is detected. 401 402 If unsure, say Y. 403 404config ARM64_ERRATUM_827319 405 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 406 default y 407 select ARM64_WORKAROUND_CLEAN_CACHE 408 help 409 This option adds an alternative code sequence to work around ARM 410 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 411 master interface and an L2 cache. 412 413 Under certain conditions this erratum can cause a clean line eviction 414 to occur at the same time as another transaction to the same address 415 on the AMBA 5 CHI interface, which can cause data corruption if the 416 interconnect reorders the two transactions. 417 418 The workaround promotes data cache clean instructions to 419 data cache clean-and-invalidate. 420 Please note that this does not necessarily enable the workaround, 421 as it depends on the alternative framework, which will only patch 422 the kernel if an affected CPU is detected. 423 424 If unsure, say Y. 425 426config ARM64_ERRATUM_824069 427 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 428 default y 429 select ARM64_WORKAROUND_CLEAN_CACHE 430 help 431 This option adds an alternative code sequence to work around ARM 432 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 433 to a coherent interconnect. 434 435 If a Cortex-A53 processor is executing a store or prefetch for 436 write instruction at the same time as a processor in another 437 cluster is executing a cache maintenance operation to the same 438 address, then this erratum might cause a clean cache line to be 439 incorrectly marked as dirty. 440 441 The workaround promotes data cache clean instructions to 442 data cache clean-and-invalidate. 443 Please note that this option does not necessarily enable the 444 workaround, as it depends on the alternative framework, which will 445 only patch the kernel if an affected CPU is detected. 446 447 If unsure, say Y. 448 449config ARM64_ERRATUM_819472 450 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 451 default y 452 select ARM64_WORKAROUND_CLEAN_CACHE 453 help 454 This option adds an alternative code sequence to work around ARM 455 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 456 present when it is connected to a coherent interconnect. 457 458 If the processor is executing a load and store exclusive sequence at 459 the same time as a processor in another cluster is executing a cache 460 maintenance operation to the same address, then this erratum might 461 cause data corruption. 462 463 The workaround promotes data cache clean instructions to 464 data cache clean-and-invalidate. 465 Please note that this does not necessarily enable the workaround, 466 as it depends on the alternative framework, which will only patch 467 the kernel if an affected CPU is detected. 468 469 If unsure, say Y. 470 471config ARM64_ERRATUM_832075 472 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 473 default y 474 help 475 This option adds an alternative code sequence to work around ARM 476 erratum 832075 on Cortex-A57 parts up to r1p2. 477 478 Affected Cortex-A57 parts might deadlock when exclusive load/store 479 instructions to Write-Back memory are mixed with Device loads. 480 481 The workaround is to promote device loads to use Load-Acquire 482 semantics. 483 Please note that this does not necessarily enable the workaround, 484 as it depends on the alternative framework, which will only patch 485 the kernel if an affected CPU is detected. 486 487 If unsure, say Y. 488 489config ARM64_ERRATUM_834220 490 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 491 depends on KVM 492 default y 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 834220 on Cortex-A57 parts up to r1p2. 496 497 Affected Cortex-A57 parts might report a Stage 2 translation 498 fault as the result of a Stage 1 fault for load crossing a 499 page boundary when there is a permission or device memory 500 alignment fault at Stage 1 and a translation fault at Stage 2. 501 502 The workaround is to verify that the Stage 1 translation 503 doesn't generate a fault before handling the Stage 2 fault. 504 Please note that this does not necessarily enable the workaround, 505 as it depends on the alternative framework, which will only patch 506 the kernel if an affected CPU is detected. 507 508 If unsure, say Y. 509 510config ARM64_ERRATUM_1742098 511 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 512 depends on COMPAT 513 default y 514 help 515 This option removes the AES hwcap for aarch32 user-space to 516 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 517 518 Affected parts may corrupt the AES state if an interrupt is 519 taken between a pair of AES instructions. These instructions 520 are only present if the cryptography extensions are present. 521 All software should have a fallback implementation for CPUs 522 that don't implement the cryptography extensions. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_845719 527 bool "Cortex-A53: 845719: a load might read incorrect data" 528 depends on COMPAT 529 default y 530 help 531 This option adds an alternative code sequence to work around ARM 532 erratum 845719 on Cortex-A53 parts up to r0p4. 533 534 When running a compat (AArch32) userspace on an affected Cortex-A53 535 part, a load at EL0 from a virtual address that matches the bottom 32 536 bits of the virtual address used by a recent load at (AArch64) EL1 537 might return incorrect data. 538 539 The workaround is to write the contextidr_el1 register on exception 540 return to a 32-bit task. 541 Please note that this does not necessarily enable the workaround, 542 as it depends on the alternative framework, which will only patch 543 the kernel if an affected CPU is detected. 544 545 If unsure, say Y. 546 547config ARM64_ERRATUM_843419 548 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 549 default y 550 select ARM64_MODULE_PLTS if MODULES 551 help 552 This option links the kernel with '--fix-cortex-a53-843419' and 553 enables PLT support to replace certain ADRP instructions, which can 554 cause subsequent memory accesses to use an incorrect address on 555 Cortex-A53 parts up to r0p4. 556 557 If unsure, say Y. 558 559config ARM64_LD_HAS_FIX_ERRATUM_843419 560 def_bool $(ld-option,--fix-cortex-a53-843419) 561 562config ARM64_ERRATUM_1024718 563 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 564 default y 565 help 566 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 567 568 Affected Cortex-A55 cores (all revisions) could cause incorrect 569 update of the hardware dirty bit when the DBM/AP bits are updated 570 without a break-before-make. The workaround is to disable the usage 571 of hardware DBM locally on the affected cores. CPUs not affected by 572 this erratum will continue to use the feature. 573 574 If unsure, say Y. 575 576config ARM64_ERRATUM_1418040 577 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 578 default y 579 depends on COMPAT 580 help 581 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 582 errata 1188873 and 1418040. 583 584 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 585 cause register corruption when accessing the timer registers 586 from AArch32 userspace. 587 588 If unsure, say Y. 589 590config ARM64_WORKAROUND_SPECULATIVE_AT 591 bool 592 593config ARM64_ERRATUM_1165522 594 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 595 default y 596 select ARM64_WORKAROUND_SPECULATIVE_AT 597 help 598 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 599 600 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 601 corrupted TLBs by speculating an AT instruction during a guest 602 context switch. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_1319367 607 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 608 default y 609 select ARM64_WORKAROUND_SPECULATIVE_AT 610 help 611 This option adds work arounds for ARM Cortex-A57 erratum 1319537 612 and A72 erratum 1319367 613 614 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 615 speculating an AT instruction during a guest context switch. 616 617 If unsure, say Y. 618 619config ARM64_ERRATUM_1530923 620 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 621 default y 622 select ARM64_WORKAROUND_SPECULATIVE_AT 623 help 624 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 625 626 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 627 corrupted TLBs by speculating an AT instruction during a guest 628 context switch. 629 630 If unsure, say Y. 631 632config ARM64_WORKAROUND_REPEAT_TLBI 633 bool 634 635config ARM64_ERRATUM_1286807 636 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 637 default y 638 select ARM64_WORKAROUND_REPEAT_TLBI 639 help 640 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 641 642 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 643 address for a cacheable mapping of a location is being 644 accessed by a core while another core is remapping the virtual 645 address to a new physical page using the recommended 646 break-before-make sequence, then under very rare circumstances 647 TLBI+DSB completes before a read using the translation being 648 invalidated has been observed by other observers. The 649 workaround repeats the TLBI+DSB operation. 650 651config ARM64_ERRATUM_1463225 652 bool "Cortex-A76: Software Step might prevent interrupt recognition" 653 default y 654 help 655 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 656 657 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 658 of a system call instruction (SVC) can prevent recognition of 659 subsequent interrupts when software stepping is disabled in the 660 exception handler of the system call and either kernel debugging 661 is enabled or VHE is in use. 662 663 Work around the erratum by triggering a dummy step exception 664 when handling a system call from a task that is being stepped 665 in a VHE configuration of the kernel. 666 667 If unsure, say Y. 668 669config ARM64_ERRATUM_1542419 670 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 671 default y 672 help 673 This option adds a workaround for ARM Neoverse-N1 erratum 674 1542419. 675 676 Affected Neoverse-N1 cores could execute a stale instruction when 677 modified by another CPU. The workaround depends on a firmware 678 counterpart. 679 680 Workaround the issue by hiding the DIC feature from EL0. This 681 forces user-space to perform cache maintenance. 682 683 If unsure, say Y. 684 685config ARM64_ERRATUM_1508412 686 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 687 default y 688 help 689 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 690 691 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 692 of a store-exclusive or read of PAR_EL1 and a load with device or 693 non-cacheable memory attributes. The workaround depends on a firmware 694 counterpart. 695 696 KVM guests must also have the workaround implemented or they can 697 deadlock the system. 698 699 Work around the issue by inserting DMB SY barriers around PAR_EL1 700 register reads and warning KVM users. The DMB barrier is sufficient 701 to prevent a speculative PAR_EL1 read. 702 703 If unsure, say Y. 704 705config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 706 bool 707 708config ARM64_ERRATUM_2051678 709 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 710 default y 711 help 712 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 713 Affected Cortex-A510 might not respect the ordering rules for 714 hardware update of the page table's dirty bit. The workaround 715 is to not enable the feature on affected CPUs. 716 717 If unsure, say Y. 718 719config ARM64_ERRATUM_2077057 720 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 721 default y 722 help 723 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 724 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 725 expected, but a Pointer Authentication trap is taken instead. The 726 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 727 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 728 729 This can only happen when EL2 is stepping EL1. 730 731 When these conditions occur, the SPSR_EL2 value is unchanged from the 732 previous guest entry, and can be restored from the in-memory copy. 733 734 If unsure, say Y. 735 736config ARM64_ERRATUM_2658417 737 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 738 default y 739 help 740 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 741 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 742 BFMMLA or VMMLA instructions in rare circumstances when a pair of 743 A510 CPUs are using shared neon hardware. As the sharing is not 744 discoverable by the kernel, hide the BF16 HWCAP to indicate that 745 user-space should not be using these instructions. 746 747 If unsure, say Y. 748 749config ARM64_ERRATUM_2119858 750 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 751 default y 752 depends on CORESIGHT_TRBE 753 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 754 help 755 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 756 757 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 758 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 759 the event of a WRAP event. 760 761 Work around the issue by always making sure we move the TRBPTR_EL1 by 762 256 bytes before enabling the buffer and filling the first 256 bytes of 763 the buffer with ETM ignore packets upon disabling. 764 765 If unsure, say Y. 766 767config ARM64_ERRATUM_2139208 768 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 769 default y 770 depends on CORESIGHT_TRBE 771 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 772 help 773 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 774 775 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 776 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 777 the event of a WRAP event. 778 779 Work around the issue by always making sure we move the TRBPTR_EL1 by 780 256 bytes before enabling the buffer and filling the first 256 bytes of 781 the buffer with ETM ignore packets upon disabling. 782 783 If unsure, say Y. 784 785config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 786 bool 787 788config ARM64_ERRATUM_2054223 789 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 790 default y 791 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 792 help 793 Enable workaround for ARM Cortex-A710 erratum 2054223 794 795 Affected cores may fail to flush the trace data on a TSB instruction, when 796 the PE is in trace prohibited state. This will cause losing a few bytes 797 of the trace cached. 798 799 Workaround is to issue two TSB consecutively on affected cores. 800 801 If unsure, say Y. 802 803config ARM64_ERRATUM_2067961 804 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 805 default y 806 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 807 help 808 Enable workaround for ARM Neoverse-N2 erratum 2067961 809 810 Affected cores may fail to flush the trace data on a TSB instruction, when 811 the PE is in trace prohibited state. This will cause losing a few bytes 812 of the trace cached. 813 814 Workaround is to issue two TSB consecutively on affected cores. 815 816 If unsure, say Y. 817 818config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 819 bool 820 821config ARM64_ERRATUM_2253138 822 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 823 depends on CORESIGHT_TRBE 824 default y 825 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 826 help 827 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 828 829 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 830 for TRBE. Under some conditions, the TRBE might generate a write to the next 831 virtually addressed page following the last page of the TRBE address space 832 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 833 834 Work around this in the driver by always making sure that there is a 835 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 836 837 If unsure, say Y. 838 839config ARM64_ERRATUM_2224489 840 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 841 depends on CORESIGHT_TRBE 842 default y 843 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 844 help 845 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 846 847 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 848 for TRBE. Under some conditions, the TRBE might generate a write to the next 849 virtually addressed page following the last page of the TRBE address space 850 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 851 852 Work around this in the driver by always making sure that there is a 853 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 854 855 If unsure, say Y. 856 857config ARM64_ERRATUM_2441009 858 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 859 default y 860 select ARM64_WORKAROUND_REPEAT_TLBI 861 help 862 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 863 864 Under very rare circumstances, affected Cortex-A510 CPUs 865 may not handle a race between a break-before-make sequence on one 866 CPU, and another CPU accessing the same page. This could allow a 867 store to a page that has been unmapped. 868 869 Work around this by adding the affected CPUs to the list that needs 870 TLB sequences to be done twice. 871 872 If unsure, say Y. 873 874config ARM64_ERRATUM_2064142 875 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 876 depends on CORESIGHT_TRBE 877 default y 878 help 879 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 880 881 Affected Cortex-A510 core might fail to write into system registers after the 882 TRBE has been disabled. Under some conditions after the TRBE has been disabled 883 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 884 and TRBTRG_EL1 will be ignored and will not be effected. 885 886 Work around this in the driver by executing TSB CSYNC and DSB after collection 887 is stopped and before performing a system register write to one of the affected 888 registers. 889 890 If unsure, say Y. 891 892config ARM64_ERRATUM_2038923 893 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 894 depends on CORESIGHT_TRBE 895 default y 896 help 897 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 898 899 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 900 prohibited within the CPU. As a result, the trace buffer or trace buffer state 901 might be corrupted. This happens after TRBE buffer has been enabled by setting 902 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 903 execution changes from a context, in which trace is prohibited to one where it 904 isn't, or vice versa. In these mentioned conditions, the view of whether trace 905 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 906 the trace buffer state might be corrupted. 907 908 Work around this in the driver by preventing an inconsistent view of whether the 909 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 910 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 911 two ISB instructions if no ERET is to take place. 912 913 If unsure, say Y. 914 915config ARM64_ERRATUM_1902691 916 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 917 depends on CORESIGHT_TRBE 918 default y 919 help 920 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 921 922 Affected Cortex-A510 core might cause trace data corruption, when being written 923 into the memory. Effectively TRBE is broken and hence cannot be used to capture 924 trace data. 925 926 Work around this problem in the driver by just preventing TRBE initialization on 927 affected cpus. The firmware must have disabled the access to TRBE for the kernel 928 on such implementations. This will cover the kernel for any firmware that doesn't 929 do this already. 930 931 If unsure, say Y. 932 933config ARM64_ERRATUM_2457168 934 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 935 depends on ARM64_AMU_EXTN 936 default y 937 help 938 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 939 940 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 941 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 942 incorrectly giving a significantly higher output value. 943 944 Work around this problem by returning 0 when reading the affected counter in 945 key locations that results in disabling all users of this counter. This effect 946 is the same to firmware disabling affected counters. 947 948 If unsure, say Y. 949 950config CAVIUM_ERRATUM_22375 951 bool "Cavium erratum 22375, 24313" 952 default y 953 help 954 Enable workaround for errata 22375 and 24313. 955 956 This implements two gicv3-its errata workarounds for ThunderX. Both 957 with a small impact affecting only ITS table allocation. 958 959 erratum 22375: only alloc 8MB table size 960 erratum 24313: ignore memory access type 961 962 The fixes are in ITS initialization and basically ignore memory access 963 type and table size provided by the TYPER and BASER registers. 964 965 If unsure, say Y. 966 967config CAVIUM_ERRATUM_23144 968 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 969 depends on NUMA 970 default y 971 help 972 ITS SYNC command hang for cross node io and collections/cpu mapping. 973 974 If unsure, say Y. 975 976config CAVIUM_ERRATUM_23154 977 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 978 default y 979 help 980 The ThunderX GICv3 implementation requires a modified version for 981 reading the IAR status to ensure data synchronization 982 (access to icc_iar1_el1 is not sync'ed before and after). 983 984 It also suffers from erratum 38545 (also present on Marvell's 985 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 986 spuriously presented to the CPU interface. 987 988 If unsure, say Y. 989 990config CAVIUM_ERRATUM_27456 991 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 992 default y 993 help 994 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 995 instructions may cause the icache to become corrupted if it 996 contains data for a non-current ASID. The fix is to 997 invalidate the icache when changing the mm context. 998 999 If unsure, say Y. 1000 1001config CAVIUM_ERRATUM_30115 1002 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1003 default y 1004 help 1005 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1006 1.2, and T83 Pass 1.0, KVM guest execution may disable 1007 interrupts in host. Trapping both GICv3 group-0 and group-1 1008 accesses sidesteps the issue. 1009 1010 If unsure, say Y. 1011 1012config CAVIUM_TX2_ERRATUM_219 1013 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1014 default y 1015 help 1016 On Cavium ThunderX2, a load, store or prefetch instruction between a 1017 TTBR update and the corresponding context synchronizing operation can 1018 cause a spurious Data Abort to be delivered to any hardware thread in 1019 the CPU core. 1020 1021 Work around the issue by avoiding the problematic code sequence and 1022 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1023 trap handler performs the corresponding register access, skips the 1024 instruction and ensures context synchronization by virtue of the 1025 exception return. 1026 1027 If unsure, say Y. 1028 1029config FUJITSU_ERRATUM_010001 1030 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1031 default y 1032 help 1033 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1034 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1035 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1036 This fault occurs under a specific hardware condition when a 1037 load/store instruction performs an address translation using: 1038 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1039 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1040 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1041 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1042 1043 The workaround is to ensure these bits are clear in TCR_ELx. 1044 The workaround only affects the Fujitsu-A64FX. 1045 1046 If unsure, say Y. 1047 1048config HISILICON_ERRATUM_161600802 1049 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1050 default y 1051 help 1052 The HiSilicon Hip07 SoC uses the wrong redistributor base 1053 when issued ITS commands such as VMOVP and VMAPP, and requires 1054 a 128kB offset to be applied to the target address in this commands. 1055 1056 If unsure, say Y. 1057 1058config QCOM_FALKOR_ERRATUM_1003 1059 bool "Falkor E1003: Incorrect translation due to ASID change" 1060 default y 1061 help 1062 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1063 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1064 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1065 then only for entries in the walk cache, since the leaf translation 1066 is unchanged. Work around the erratum by invalidating the walk cache 1067 entries for the trampoline before entering the kernel proper. 1068 1069config QCOM_FALKOR_ERRATUM_1009 1070 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1071 default y 1072 select ARM64_WORKAROUND_REPEAT_TLBI 1073 help 1074 On Falkor v1, the CPU may prematurely complete a DSB following a 1075 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1076 one more time to fix the issue. 1077 1078 If unsure, say Y. 1079 1080config QCOM_QDF2400_ERRATUM_0065 1081 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1082 default y 1083 help 1084 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1085 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1086 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1087 1088 If unsure, say Y. 1089 1090config QCOM_FALKOR_ERRATUM_E1041 1091 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1092 default y 1093 help 1094 Falkor CPU may speculatively fetch instructions from an improper 1095 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1096 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1097 1098 If unsure, say Y. 1099 1100config NVIDIA_CARMEL_CNP_ERRATUM 1101 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1102 default y 1103 help 1104 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1105 invalidate shared TLB entries installed by a different core, as it would 1106 on standard ARM cores. 1107 1108 If unsure, say Y. 1109 1110config SOCIONEXT_SYNQUACER_PREITS 1111 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1112 default y 1113 help 1114 Socionext Synquacer SoCs implement a separate h/w block to generate 1115 MSI doorbell writes with non-zero values for the device ID. 1116 1117 If unsure, say Y. 1118 1119endmenu # "ARM errata workarounds via the alternatives framework" 1120 1121choice 1122 prompt "Page size" 1123 default ARM64_4K_PAGES 1124 help 1125 Page size (translation granule) configuration. 1126 1127config ARM64_4K_PAGES 1128 bool "4KB" 1129 help 1130 This feature enables 4KB pages support. 1131 1132config ARM64_16K_PAGES 1133 bool "16KB" 1134 help 1135 The system will use 16KB pages support. AArch32 emulation 1136 requires applications compiled with 16K (or a multiple of 16K) 1137 aligned segments. 1138 1139config ARM64_64K_PAGES 1140 bool "64KB" 1141 help 1142 This feature enables 64KB pages support (4KB by default) 1143 allowing only two levels of page tables and faster TLB 1144 look-up. AArch32 emulation requires applications compiled 1145 with 64K aligned segments. 1146 1147endchoice 1148 1149choice 1150 prompt "Virtual address space size" 1151 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1152 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1153 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1154 help 1155 Allows choosing one of multiple possible virtual address 1156 space sizes. The level of translation table is determined by 1157 a combination of page size and virtual address space size. 1158 1159config ARM64_VA_BITS_36 1160 bool "36-bit" if EXPERT 1161 depends on ARM64_16K_PAGES 1162 1163config ARM64_VA_BITS_39 1164 bool "39-bit" 1165 depends on ARM64_4K_PAGES 1166 1167config ARM64_VA_BITS_42 1168 bool "42-bit" 1169 depends on ARM64_64K_PAGES 1170 1171config ARM64_VA_BITS_47 1172 bool "47-bit" 1173 depends on ARM64_16K_PAGES 1174 1175config ARM64_VA_BITS_48 1176 bool "48-bit" 1177 1178config ARM64_VA_BITS_52 1179 bool "52-bit" 1180 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1181 help 1182 Enable 52-bit virtual addressing for userspace when explicitly 1183 requested via a hint to mmap(). The kernel will also use 52-bit 1184 virtual addresses for its own mappings (provided HW support for 1185 this feature is available, otherwise it reverts to 48-bit). 1186 1187 NOTE: Enabling 52-bit virtual addressing in conjunction with 1188 ARMv8.3 Pointer Authentication will result in the PAC being 1189 reduced from 7 bits to 3 bits, which may have a significant 1190 impact on its susceptibility to brute-force attacks. 1191 1192 If unsure, select 48-bit virtual addressing instead. 1193 1194endchoice 1195 1196config ARM64_FORCE_52BIT 1197 bool "Force 52-bit virtual addresses for userspace" 1198 depends on ARM64_VA_BITS_52 && EXPERT 1199 help 1200 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1201 to maintain compatibility with older software by providing 48-bit VAs 1202 unless a hint is supplied to mmap. 1203 1204 This configuration option disables the 48-bit compatibility logic, and 1205 forces all userspace addresses to be 52-bit on HW that supports it. One 1206 should only enable this configuration option for stress testing userspace 1207 memory management code. If unsure say N here. 1208 1209config ARM64_VA_BITS 1210 int 1211 default 36 if ARM64_VA_BITS_36 1212 default 39 if ARM64_VA_BITS_39 1213 default 42 if ARM64_VA_BITS_42 1214 default 47 if ARM64_VA_BITS_47 1215 default 48 if ARM64_VA_BITS_48 1216 default 52 if ARM64_VA_BITS_52 1217 1218choice 1219 prompt "Physical address space size" 1220 default ARM64_PA_BITS_48 1221 help 1222 Choose the maximum physical address range that the kernel will 1223 support. 1224 1225config ARM64_PA_BITS_48 1226 bool "48-bit" 1227 1228config ARM64_PA_BITS_52 1229 bool "52-bit (ARMv8.2)" 1230 depends on ARM64_64K_PAGES 1231 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1232 help 1233 Enable support for a 52-bit physical address space, introduced as 1234 part of the ARMv8.2-LPA extension. 1235 1236 With this enabled, the kernel will also continue to work on CPUs that 1237 do not support ARMv8.2-LPA, but with some added memory overhead (and 1238 minor performance overhead). 1239 1240endchoice 1241 1242config ARM64_PA_BITS 1243 int 1244 default 48 if ARM64_PA_BITS_48 1245 default 52 if ARM64_PA_BITS_52 1246 1247choice 1248 prompt "Endianness" 1249 default CPU_LITTLE_ENDIAN 1250 help 1251 Select the endianness of data accesses performed by the CPU. Userspace 1252 applications will need to be compiled and linked for the endianness 1253 that is selected here. 1254 1255config CPU_BIG_ENDIAN 1256 bool "Build big-endian kernel" 1257 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1258 help 1259 Say Y if you plan on running a kernel with a big-endian userspace. 1260 1261config CPU_LITTLE_ENDIAN 1262 bool "Build little-endian kernel" 1263 help 1264 Say Y if you plan on running a kernel with a little-endian userspace. 1265 This is usually the case for distributions targeting arm64. 1266 1267endchoice 1268 1269config SCHED_MC 1270 bool "Multi-core scheduler support" 1271 help 1272 Multi-core scheduler support improves the CPU scheduler's decision 1273 making when dealing with multi-core CPU chips at a cost of slightly 1274 increased overhead in some places. If unsure say N here. 1275 1276config SCHED_CLUSTER 1277 bool "Cluster scheduler support" 1278 help 1279 Cluster scheduler support improves the CPU scheduler's decision 1280 making when dealing with machines that have clusters of CPUs. 1281 Cluster usually means a couple of CPUs which are placed closely 1282 by sharing mid-level caches, last-level cache tags or internal 1283 busses. 1284 1285config SCHED_SMT 1286 bool "SMT scheduler support" 1287 help 1288 Improves the CPU scheduler's decision making when dealing with 1289 MultiThreading at a cost of slightly increased overhead in some 1290 places. If unsure say N here. 1291 1292config NR_CPUS 1293 int "Maximum number of CPUs (2-4096)" 1294 range 2 4096 1295 default "256" 1296 1297config HOTPLUG_CPU 1298 bool "Support for hot-pluggable CPUs" 1299 select GENERIC_IRQ_MIGRATION 1300 help 1301 Say Y here to experiment with turning CPUs off and on. CPUs 1302 can be controlled through /sys/devices/system/cpu. 1303 1304# Common NUMA Features 1305config NUMA 1306 bool "NUMA Memory Allocation and Scheduler Support" 1307 select GENERIC_ARCH_NUMA 1308 select ACPI_NUMA if ACPI 1309 select OF_NUMA 1310 select HAVE_SETUP_PER_CPU_AREA 1311 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1312 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1313 select USE_PERCPU_NUMA_NODE_ID 1314 help 1315 Enable NUMA (Non-Uniform Memory Access) support. 1316 1317 The kernel will try to allocate memory used by a CPU on the 1318 local memory of the CPU and add some more 1319 NUMA awareness to the kernel. 1320 1321config NODES_SHIFT 1322 int "Maximum NUMA Nodes (as a power of 2)" 1323 range 1 10 1324 default "4" 1325 depends on NUMA 1326 help 1327 Specify the maximum number of NUMA Nodes available on the target 1328 system. Increases memory reserved to accommodate various tables. 1329 1330source "kernel/Kconfig.hz" 1331 1332config ARCH_SPARSEMEM_ENABLE 1333 def_bool y 1334 select SPARSEMEM_VMEMMAP_ENABLE 1335 select SPARSEMEM_VMEMMAP 1336 1337config HW_PERF_EVENTS 1338 def_bool y 1339 depends on ARM_PMU 1340 1341# Supported by clang >= 7.0 or GCC >= 12.0.0 1342config CC_HAVE_SHADOW_CALL_STACK 1343 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1344 1345config PARAVIRT 1346 bool "Enable paravirtualization code" 1347 help 1348 This changes the kernel so it can modify itself when it is run 1349 under a hypervisor, potentially improving performance significantly 1350 over full virtualization. 1351 1352config PARAVIRT_TIME_ACCOUNTING 1353 bool "Paravirtual steal time accounting" 1354 select PARAVIRT 1355 help 1356 Select this option to enable fine granularity task steal time 1357 accounting. Time spent executing other tasks in parallel with 1358 the current vCPU is discounted from the vCPU power. To account for 1359 that, there can be a small performance impact. 1360 1361 If in doubt, say N here. 1362 1363config KEXEC 1364 depends on PM_SLEEP_SMP 1365 select KEXEC_CORE 1366 bool "kexec system call" 1367 help 1368 kexec is a system call that implements the ability to shutdown your 1369 current kernel, and to start another kernel. It is like a reboot 1370 but it is independent of the system firmware. And like a reboot 1371 you can start any kernel with it, not just Linux. 1372 1373config KEXEC_FILE 1374 bool "kexec file based system call" 1375 select KEXEC_CORE 1376 select HAVE_IMA_KEXEC if IMA 1377 help 1378 This is new version of kexec system call. This system call is 1379 file based and takes file descriptors as system call argument 1380 for kernel and initramfs as opposed to list of segments as 1381 accepted by previous system call. 1382 1383config KEXEC_SIG 1384 bool "Verify kernel signature during kexec_file_load() syscall" 1385 depends on KEXEC_FILE 1386 help 1387 Select this option to verify a signature with loaded kernel 1388 image. If configured, any attempt of loading a image without 1389 valid signature will fail. 1390 1391 In addition to that option, you need to enable signature 1392 verification for the corresponding kernel image type being 1393 loaded in order for this to work. 1394 1395config KEXEC_IMAGE_VERIFY_SIG 1396 bool "Enable Image signature verification support" 1397 default y 1398 depends on KEXEC_SIG 1399 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1400 help 1401 Enable Image signature verification support. 1402 1403comment "Support for PE file signature verification disabled" 1404 depends on KEXEC_SIG 1405 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1406 1407config CRASH_DUMP 1408 bool "Build kdump crash kernel" 1409 help 1410 Generate crash dump after being started by kexec. This should 1411 be normally only set in special crash dump kernels which are 1412 loaded in the main kernel with kexec-tools into a specially 1413 reserved region and then later executed after a crash by 1414 kdump/kexec. 1415 1416 For more details see Documentation/admin-guide/kdump/kdump.rst 1417 1418config TRANS_TABLE 1419 def_bool y 1420 depends on HIBERNATION || KEXEC_CORE 1421 1422config XEN_DOM0 1423 def_bool y 1424 depends on XEN 1425 1426config XEN 1427 bool "Xen guest support on ARM64" 1428 depends on ARM64 && OF 1429 select SWIOTLB_XEN 1430 select PARAVIRT 1431 help 1432 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1433 1434config ARCH_FORCE_MAX_ORDER 1435 int 1436 default "14" if ARM64_64K_PAGES 1437 default "12" if ARM64_16K_PAGES 1438 default "11" 1439 help 1440 The kernel memory allocator divides physically contiguous memory 1441 blocks into "zones", where each zone is a power of two number of 1442 pages. This option selects the largest power of two that the kernel 1443 keeps in the memory allocator. If you need to allocate very large 1444 blocks of physically contiguous memory, then you may need to 1445 increase this value. 1446 1447 This config option is actually maximum order plus one. For example, 1448 a value of 11 means that the largest free memory block is 2^10 pages. 1449 1450 We make sure that we can allocate upto a HugePage size for each configuration. 1451 Hence we have : 1452 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1453 1454 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1455 4M allocations matching the default size used by generic code. 1456 1457config UNMAP_KERNEL_AT_EL0 1458 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1459 default y 1460 help 1461 Speculation attacks against some high-performance processors can 1462 be used to bypass MMU permission checks and leak kernel data to 1463 userspace. This can be defended against by unmapping the kernel 1464 when running in userspace, mapping it back in on exception entry 1465 via a trampoline page in the vector table. 1466 1467 If unsure, say Y. 1468 1469config MITIGATE_SPECTRE_BRANCH_HISTORY 1470 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1471 default y 1472 help 1473 Speculation attacks against some high-performance processors can 1474 make use of branch history to influence future speculation. 1475 When taking an exception from user-space, a sequence of branches 1476 or a firmware call overwrites the branch history. 1477 1478config RODATA_FULL_DEFAULT_ENABLED 1479 bool "Apply r/o permissions of VM areas also to their linear aliases" 1480 default y 1481 help 1482 Apply read-only attributes of VM areas to the linear alias of 1483 the backing pages as well. This prevents code or read-only data 1484 from being modified (inadvertently or intentionally) via another 1485 mapping of the same memory page. This additional enhancement can 1486 be turned off at runtime by passing rodata=[off|on] (and turned on 1487 with rodata=full if this option is set to 'n') 1488 1489 This requires the linear region to be mapped down to pages, 1490 which may adversely affect performance in some cases. 1491 1492config ARM64_SW_TTBR0_PAN 1493 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1494 help 1495 Enabling this option prevents the kernel from accessing 1496 user-space memory directly by pointing TTBR0_EL1 to a reserved 1497 zeroed area and reserved ASID. The user access routines 1498 restore the valid TTBR0_EL1 temporarily. 1499 1500config ARM64_TAGGED_ADDR_ABI 1501 bool "Enable the tagged user addresses syscall ABI" 1502 default y 1503 help 1504 When this option is enabled, user applications can opt in to a 1505 relaxed ABI via prctl() allowing tagged addresses to be passed 1506 to system calls as pointer arguments. For details, see 1507 Documentation/arm64/tagged-address-abi.rst. 1508 1509menuconfig COMPAT 1510 bool "Kernel support for 32-bit EL0" 1511 depends on ARM64_4K_PAGES || EXPERT 1512 select HAVE_UID16 1513 select OLD_SIGSUSPEND3 1514 select COMPAT_OLD_SIGACTION 1515 help 1516 This option enables support for a 32-bit EL0 running under a 64-bit 1517 kernel at EL1. AArch32-specific components such as system calls, 1518 the user helper functions, VFP support and the ptrace interface are 1519 handled appropriately by the kernel. 1520 1521 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1522 that you will only be able to execute AArch32 binaries that were compiled 1523 with page size aligned segments. 1524 1525 If you want to execute 32-bit userspace applications, say Y. 1526 1527if COMPAT 1528 1529config KUSER_HELPERS 1530 bool "Enable kuser helpers page for 32-bit applications" 1531 default y 1532 help 1533 Warning: disabling this option may break 32-bit user programs. 1534 1535 Provide kuser helpers to compat tasks. The kernel provides 1536 helper code to userspace in read only form at a fixed location 1537 to allow userspace to be independent of the CPU type fitted to 1538 the system. This permits binaries to be run on ARMv4 through 1539 to ARMv8 without modification. 1540 1541 See Documentation/arm/kernel_user_helpers.rst for details. 1542 1543 However, the fixed address nature of these helpers can be used 1544 by ROP (return orientated programming) authors when creating 1545 exploits. 1546 1547 If all of the binaries and libraries which run on your platform 1548 are built specifically for your platform, and make no use of 1549 these helpers, then you can turn this option off to hinder 1550 such exploits. However, in that case, if a binary or library 1551 relying on those helpers is run, it will not function correctly. 1552 1553 Say N here only if you are absolutely certain that you do not 1554 need these helpers; otherwise, the safe option is to say Y. 1555 1556config COMPAT_VDSO 1557 bool "Enable vDSO for 32-bit applications" 1558 depends on !CPU_BIG_ENDIAN 1559 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1560 select GENERIC_COMPAT_VDSO 1561 default y 1562 help 1563 Place in the process address space of 32-bit applications an 1564 ELF shared object providing fast implementations of gettimeofday 1565 and clock_gettime. 1566 1567 You must have a 32-bit build of glibc 2.22 or later for programs 1568 to seamlessly take advantage of this. 1569 1570config THUMB2_COMPAT_VDSO 1571 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1572 depends on COMPAT_VDSO 1573 default y 1574 help 1575 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1576 otherwise with '-marm'. 1577 1578config COMPAT_ALIGNMENT_FIXUPS 1579 bool "Fix up misaligned multi-word loads and stores in user space" 1580 1581menuconfig ARMV8_DEPRECATED 1582 bool "Emulate deprecated/obsolete ARMv8 instructions" 1583 depends on SYSCTL 1584 help 1585 Legacy software support may require certain instructions 1586 that have been deprecated or obsoleted in the architecture. 1587 1588 Enable this config to enable selective emulation of these 1589 features. 1590 1591 If unsure, say Y 1592 1593if ARMV8_DEPRECATED 1594 1595config SWP_EMULATION 1596 bool "Emulate SWP/SWPB instructions" 1597 help 1598 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1599 they are always undefined. Say Y here to enable software 1600 emulation of these instructions for userspace using LDXR/STXR. 1601 This feature can be controlled at runtime with the abi.swp 1602 sysctl which is disabled by default. 1603 1604 In some older versions of glibc [<=2.8] SWP is used during futex 1605 trylock() operations with the assumption that the code will not 1606 be preempted. This invalid assumption may be more likely to fail 1607 with SWP emulation enabled, leading to deadlock of the user 1608 application. 1609 1610 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1611 on an external transaction monitoring block called a global 1612 monitor to maintain update atomicity. If your system does not 1613 implement a global monitor, this option can cause programs that 1614 perform SWP operations to uncached memory to deadlock. 1615 1616 If unsure, say Y 1617 1618config CP15_BARRIER_EMULATION 1619 bool "Emulate CP15 Barrier instructions" 1620 help 1621 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1622 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1623 strongly recommended to use the ISB, DSB, and DMB 1624 instructions instead. 1625 1626 Say Y here to enable software emulation of these 1627 instructions for AArch32 userspace code. When this option is 1628 enabled, CP15 barrier usage is traced which can help 1629 identify software that needs updating. This feature can be 1630 controlled at runtime with the abi.cp15_barrier sysctl. 1631 1632 If unsure, say Y 1633 1634config SETEND_EMULATION 1635 bool "Emulate SETEND instruction" 1636 help 1637 The SETEND instruction alters the data-endianness of the 1638 AArch32 EL0, and is deprecated in ARMv8. 1639 1640 Say Y here to enable software emulation of the instruction 1641 for AArch32 userspace code. This feature can be controlled 1642 at runtime with the abi.setend sysctl. 1643 1644 Note: All the cpus on the system must have mixed endian support at EL0 1645 for this feature to be enabled. If a new CPU - which doesn't support mixed 1646 endian - is hotplugged in after this feature has been enabled, there could 1647 be unexpected results in the applications. 1648 1649 If unsure, say Y 1650endif # ARMV8_DEPRECATED 1651 1652endif # COMPAT 1653 1654menu "ARMv8.1 architectural features" 1655 1656config ARM64_HW_AFDBM 1657 bool "Support for hardware updates of the Access and Dirty page flags" 1658 default y 1659 help 1660 The ARMv8.1 architecture extensions introduce support for 1661 hardware updates of the access and dirty information in page 1662 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1663 capable processors, accesses to pages with PTE_AF cleared will 1664 set this bit instead of raising an access flag fault. 1665 Similarly, writes to read-only pages with the DBM bit set will 1666 clear the read-only bit (AP[2]) instead of raising a 1667 permission fault. 1668 1669 Kernels built with this configuration option enabled continue 1670 to work on pre-ARMv8.1 hardware and the performance impact is 1671 minimal. If unsure, say Y. 1672 1673config ARM64_PAN 1674 bool "Enable support for Privileged Access Never (PAN)" 1675 default y 1676 help 1677 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1678 prevents the kernel or hypervisor from accessing user-space (EL0) 1679 memory directly. 1680 1681 Choosing this option will cause any unprotected (not using 1682 copy_to_user et al) memory access to fail with a permission fault. 1683 1684 The feature is detected at runtime, and will remain as a 'nop' 1685 instruction if the cpu does not implement the feature. 1686 1687config AS_HAS_LDAPR 1688 def_bool $(as-instr,.arch_extension rcpc) 1689 1690config AS_HAS_LSE_ATOMICS 1691 def_bool $(as-instr,.arch_extension lse) 1692 1693config ARM64_LSE_ATOMICS 1694 bool 1695 default ARM64_USE_LSE_ATOMICS 1696 depends on AS_HAS_LSE_ATOMICS 1697 1698config ARM64_USE_LSE_ATOMICS 1699 bool "Atomic instructions" 1700 depends on JUMP_LABEL 1701 default y 1702 help 1703 As part of the Large System Extensions, ARMv8.1 introduces new 1704 atomic instructions that are designed specifically to scale in 1705 very large systems. 1706 1707 Say Y here to make use of these instructions for the in-kernel 1708 atomic routines. This incurs a small overhead on CPUs that do 1709 not support these instructions and requires the kernel to be 1710 built with binutils >= 2.25 in order for the new instructions 1711 to be used. 1712 1713endmenu # "ARMv8.1 architectural features" 1714 1715menu "ARMv8.2 architectural features" 1716 1717config AS_HAS_ARMV8_2 1718 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1719 1720config AS_HAS_SHA3 1721 def_bool $(as-instr,.arch armv8.2-a+sha3) 1722 1723config ARM64_PMEM 1724 bool "Enable support for persistent memory" 1725 select ARCH_HAS_PMEM_API 1726 select ARCH_HAS_UACCESS_FLUSHCACHE 1727 help 1728 Say Y to enable support for the persistent memory API based on the 1729 ARMv8.2 DCPoP feature. 1730 1731 The feature is detected at runtime, and the kernel will use DC CVAC 1732 operations if DC CVAP is not supported (following the behaviour of 1733 DC CVAP itself if the system does not define a point of persistence). 1734 1735config ARM64_RAS_EXTN 1736 bool "Enable support for RAS CPU Extensions" 1737 default y 1738 help 1739 CPUs that support the Reliability, Availability and Serviceability 1740 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1741 errors, classify them and report them to software. 1742 1743 On CPUs with these extensions system software can use additional 1744 barriers to determine if faults are pending and read the 1745 classification from a new set of registers. 1746 1747 Selecting this feature will allow the kernel to use these barriers 1748 and access the new registers if the system supports the extension. 1749 Platform RAS features may additionally depend on firmware support. 1750 1751config ARM64_CNP 1752 bool "Enable support for Common Not Private (CNP) translations" 1753 default y 1754 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1755 help 1756 Common Not Private (CNP) allows translation table entries to 1757 be shared between different PEs in the same inner shareable 1758 domain, so the hardware can use this fact to optimise the 1759 caching of such entries in the TLB. 1760 1761 Selecting this option allows the CNP feature to be detected 1762 at runtime, and does not affect PEs that do not implement 1763 this feature. 1764 1765endmenu # "ARMv8.2 architectural features" 1766 1767menu "ARMv8.3 architectural features" 1768 1769config ARM64_PTR_AUTH 1770 bool "Enable support for pointer authentication" 1771 default y 1772 help 1773 Pointer authentication (part of the ARMv8.3 Extensions) provides 1774 instructions for signing and authenticating pointers against secret 1775 keys, which can be used to mitigate Return Oriented Programming (ROP) 1776 and other attacks. 1777 1778 This option enables these instructions at EL0 (i.e. for userspace). 1779 Choosing this option will cause the kernel to initialise secret keys 1780 for each process at exec() time, with these keys being 1781 context-switched along with the process. 1782 1783 The feature is detected at runtime. If the feature is not present in 1784 hardware it will not be advertised to userspace/KVM guest nor will it 1785 be enabled. 1786 1787 If the feature is present on the boot CPU but not on a late CPU, then 1788 the late CPU will be parked. Also, if the boot CPU does not have 1789 address auth and the late CPU has then the late CPU will still boot 1790 but with the feature disabled. On such a system, this option should 1791 not be selected. 1792 1793config ARM64_PTR_AUTH_KERNEL 1794 bool "Use pointer authentication for kernel" 1795 default y 1796 depends on ARM64_PTR_AUTH 1797 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1798 # Modern compilers insert a .note.gnu.property section note for PAC 1799 # which is only understood by binutils starting with version 2.33.1. 1800 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1801 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1802 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1803 help 1804 If the compiler supports the -mbranch-protection or 1805 -msign-return-address flag (e.g. GCC 7 or later), then this option 1806 will cause the kernel itself to be compiled with return address 1807 protection. In this case, and if the target hardware is known to 1808 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1809 disabled with minimal loss of protection. 1810 1811 This feature works with FUNCTION_GRAPH_TRACER option only if 1812 DYNAMIC_FTRACE_WITH_REGS is enabled. 1813 1814config CC_HAS_BRANCH_PROT_PAC_RET 1815 # GCC 9 or later, clang 8 or later 1816 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1817 1818config CC_HAS_SIGN_RETURN_ADDRESS 1819 # GCC 7, 8 1820 def_bool $(cc-option,-msign-return-address=all) 1821 1822config AS_HAS_PAC 1823 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1824 1825config AS_HAS_CFI_NEGATE_RA_STATE 1826 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1827 1828endmenu # "ARMv8.3 architectural features" 1829 1830menu "ARMv8.4 architectural features" 1831 1832config ARM64_AMU_EXTN 1833 bool "Enable support for the Activity Monitors Unit CPU extension" 1834 default y 1835 help 1836 The activity monitors extension is an optional extension introduced 1837 by the ARMv8.4 CPU architecture. This enables support for version 1 1838 of the activity monitors architecture, AMUv1. 1839 1840 To enable the use of this extension on CPUs that implement it, say Y. 1841 1842 Note that for architectural reasons, firmware _must_ implement AMU 1843 support when running on CPUs that present the activity monitors 1844 extension. The required support is present in: 1845 * Version 1.5 and later of the ARM Trusted Firmware 1846 1847 For kernels that have this configuration enabled but boot with broken 1848 firmware, you may need to say N here until the firmware is fixed. 1849 Otherwise you may experience firmware panics or lockups when 1850 accessing the counter registers. Even if you are not observing these 1851 symptoms, the values returned by the register reads might not 1852 correctly reflect reality. Most commonly, the value read will be 0, 1853 indicating that the counter is not enabled. 1854 1855config AS_HAS_ARMV8_4 1856 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1857 1858config ARM64_TLB_RANGE 1859 bool "Enable support for tlbi range feature" 1860 default y 1861 depends on AS_HAS_ARMV8_4 1862 help 1863 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1864 range of input addresses. 1865 1866 The feature introduces new assembly instructions, and they were 1867 support when binutils >= 2.30. 1868 1869endmenu # "ARMv8.4 architectural features" 1870 1871menu "ARMv8.5 architectural features" 1872 1873config AS_HAS_ARMV8_5 1874 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1875 1876config ARM64_BTI 1877 bool "Branch Target Identification support" 1878 default y 1879 help 1880 Branch Target Identification (part of the ARMv8.5 Extensions) 1881 provides a mechanism to limit the set of locations to which computed 1882 branch instructions such as BR or BLR can jump. 1883 1884 To make use of BTI on CPUs that support it, say Y. 1885 1886 BTI is intended to provide complementary protection to other control 1887 flow integrity protection mechanisms, such as the Pointer 1888 authentication mechanism provided as part of the ARMv8.3 Extensions. 1889 For this reason, it does not make sense to enable this option without 1890 also enabling support for pointer authentication. Thus, when 1891 enabling this option you should also select ARM64_PTR_AUTH=y. 1892 1893 Userspace binaries must also be specifically compiled to make use of 1894 this mechanism. If you say N here or the hardware does not support 1895 BTI, such binaries can still run, but you get no additional 1896 enforcement of branch destinations. 1897 1898config ARM64_BTI_KERNEL 1899 bool "Use Branch Target Identification for kernel" 1900 default y 1901 depends on ARM64_BTI 1902 depends on ARM64_PTR_AUTH_KERNEL 1903 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1904 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1905 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1906 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1907 depends on !CC_IS_GCC 1908 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1909 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1910 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1911 help 1912 Build the kernel with Branch Target Identification annotations 1913 and enable enforcement of this for kernel code. When this option 1914 is enabled and the system supports BTI all kernel code including 1915 modular code must have BTI enabled. 1916 1917config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1918 # GCC 9 or later, clang 8 or later 1919 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1920 1921config ARM64_E0PD 1922 bool "Enable support for E0PD" 1923 default y 1924 help 1925 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1926 that EL0 accesses made via TTBR1 always fault in constant time, 1927 providing similar benefits to KASLR as those provided by KPTI, but 1928 with lower overhead and without disrupting legitimate access to 1929 kernel memory such as SPE. 1930 1931 This option enables E0PD for TTBR1 where available. 1932 1933config ARM64_AS_HAS_MTE 1934 # Initial support for MTE went in binutils 2.32.0, checked with 1935 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1936 # as a late addition to the final architecture spec (LDGM/STGM) 1937 # is only supported in the newer 2.32.x and 2.33 binutils 1938 # versions, hence the extra "stgm" instruction check below. 1939 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1940 1941config ARM64_MTE 1942 bool "Memory Tagging Extension support" 1943 default y 1944 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1945 depends on AS_HAS_ARMV8_5 1946 depends on AS_HAS_LSE_ATOMICS 1947 # Required for tag checking in the uaccess routines 1948 depends on ARM64_PAN 1949 select ARCH_HAS_SUBPAGE_FAULTS 1950 select ARCH_USES_HIGH_VMA_FLAGS 1951 help 1952 Memory Tagging (part of the ARMv8.5 Extensions) provides 1953 architectural support for run-time, always-on detection of 1954 various classes of memory error to aid with software debugging 1955 to eliminate vulnerabilities arising from memory-unsafe 1956 languages. 1957 1958 This option enables the support for the Memory Tagging 1959 Extension at EL0 (i.e. for userspace). 1960 1961 Selecting this option allows the feature to be detected at 1962 runtime. Any secondary CPU not implementing this feature will 1963 not be allowed a late bring-up. 1964 1965 Userspace binaries that want to use this feature must 1966 explicitly opt in. The mechanism for the userspace is 1967 described in: 1968 1969 Documentation/arm64/memory-tagging-extension.rst. 1970 1971endmenu # "ARMv8.5 architectural features" 1972 1973menu "ARMv8.7 architectural features" 1974 1975config ARM64_EPAN 1976 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1977 default y 1978 depends on ARM64_PAN 1979 help 1980 Enhanced Privileged Access Never (EPAN) allows Privileged 1981 Access Never to be used with Execute-only mappings. 1982 1983 The feature is detected at runtime, and will remain disabled 1984 if the cpu does not implement the feature. 1985endmenu # "ARMv8.7 architectural features" 1986 1987config ARM64_SVE 1988 bool "ARM Scalable Vector Extension support" 1989 default y 1990 help 1991 The Scalable Vector Extension (SVE) is an extension to the AArch64 1992 execution state which complements and extends the SIMD functionality 1993 of the base architecture to support much larger vectors and to enable 1994 additional vectorisation opportunities. 1995 1996 To enable use of this extension on CPUs that implement it, say Y. 1997 1998 On CPUs that support the SVE2 extensions, this option will enable 1999 those too. 2000 2001 Note that for architectural reasons, firmware _must_ implement SVE 2002 support when running on SVE capable hardware. The required support 2003 is present in: 2004 2005 * version 1.5 and later of the ARM Trusted Firmware 2006 * the AArch64 boot wrapper since commit 5e1261e08abf 2007 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2008 2009 For other firmware implementations, consult the firmware documentation 2010 or vendor. 2011 2012 If you need the kernel to boot on SVE-capable hardware with broken 2013 firmware, you may need to say N here until you get your firmware 2014 fixed. Otherwise, you may experience firmware panics or lockups when 2015 booting the kernel. If unsure and you are not observing these 2016 symptoms, you should assume that it is safe to say Y. 2017 2018config ARM64_SME 2019 bool "ARM Scalable Matrix Extension support" 2020 default y 2021 depends on ARM64_SVE 2022 help 2023 The Scalable Matrix Extension (SME) is an extension to the AArch64 2024 execution state which utilises a substantial subset of the SVE 2025 instruction set, together with the addition of new architectural 2026 register state capable of holding two dimensional matrix tiles to 2027 enable various matrix operations. 2028 2029config ARM64_MODULE_PLTS 2030 bool "Use PLTs to allow module memory to spill over into vmalloc area" 2031 depends on MODULES 2032 select HAVE_MOD_ARCH_SPECIFIC 2033 help 2034 Allocate PLTs when loading modules so that jumps and calls whose 2035 targets are too far away for their relative offsets to be encoded 2036 in the instructions themselves can be bounced via veneers in the 2037 module's PLT. This allows modules to be allocated in the generic 2038 vmalloc area after the dedicated module memory area has been 2039 exhausted. 2040 2041 When running with address space randomization (KASLR), the module 2042 region itself may be too far away for ordinary relative jumps and 2043 calls, and so in that case, module PLTs are required and cannot be 2044 disabled. 2045 2046 Specific errata workaround(s) might also force module PLTs to be 2047 enabled (ARM64_ERRATUM_843419). 2048 2049config ARM64_PSEUDO_NMI 2050 bool "Support for NMI-like interrupts" 2051 select ARM_GIC_V3 2052 help 2053 Adds support for mimicking Non-Maskable Interrupts through the use of 2054 GIC interrupt priority. This support requires version 3 or later of 2055 ARM GIC. 2056 2057 This high priority configuration for interrupts needs to be 2058 explicitly enabled by setting the kernel parameter 2059 "irqchip.gicv3_pseudo_nmi" to 1. 2060 2061 If unsure, say N 2062 2063if ARM64_PSEUDO_NMI 2064config ARM64_DEBUG_PRIORITY_MASKING 2065 bool "Debug interrupt priority masking" 2066 help 2067 This adds runtime checks to functions enabling/disabling 2068 interrupts when using priority masking. The additional checks verify 2069 the validity of ICC_PMR_EL1 when calling concerned functions. 2070 2071 If unsure, say N 2072endif # ARM64_PSEUDO_NMI 2073 2074config RELOCATABLE 2075 bool "Build a relocatable kernel image" if EXPERT 2076 select ARCH_HAS_RELR 2077 default y 2078 help 2079 This builds the kernel as a Position Independent Executable (PIE), 2080 which retains all relocation metadata required to relocate the 2081 kernel binary at runtime to a different virtual address than the 2082 address it was linked at. 2083 Since AArch64 uses the RELA relocation format, this requires a 2084 relocation pass at runtime even if the kernel is loaded at the 2085 same address it was linked at. 2086 2087config RANDOMIZE_BASE 2088 bool "Randomize the address of the kernel image" 2089 select ARM64_MODULE_PLTS if MODULES 2090 select RELOCATABLE 2091 help 2092 Randomizes the virtual address at which the kernel image is 2093 loaded, as a security feature that deters exploit attempts 2094 relying on knowledge of the location of kernel internals. 2095 2096 It is the bootloader's job to provide entropy, by passing a 2097 random u64 value in /chosen/kaslr-seed at kernel entry. 2098 2099 When booting via the UEFI stub, it will invoke the firmware's 2100 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2101 to the kernel proper. In addition, it will randomise the physical 2102 location of the kernel Image as well. 2103 2104 If unsure, say N. 2105 2106config RANDOMIZE_MODULE_REGION_FULL 2107 bool "Randomize the module region over a 2 GB range" 2108 depends on RANDOMIZE_BASE 2109 default y 2110 help 2111 Randomizes the location of the module region inside a 2 GB window 2112 covering the core kernel. This way, it is less likely for modules 2113 to leak information about the location of core kernel data structures 2114 but it does imply that function calls between modules and the core 2115 kernel will need to be resolved via veneers in the module PLT. 2116 2117 When this option is not set, the module region will be randomized over 2118 a limited range that contains the [_stext, _etext] interval of the 2119 core kernel, so branch relocations are almost always in range unless 2120 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2121 particular case of region exhaustion, modules might be able to fall 2122 back to a larger 2GB area. 2123 2124config CC_HAVE_STACKPROTECTOR_SYSREG 2125 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2126 2127config STACKPROTECTOR_PER_TASK 2128 def_bool y 2129 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2130 2131# The GPIO number here must be sorted by descending number. In case of 2132# a multiplatform kernel, we just want the highest value required by the 2133# selected platforms. 2134config ARCH_NR_GPIO 2135 int 2136 default 2048 if ARCH_APPLE 2137 default 0 2138 help 2139 Maximum number of GPIOs in the system. 2140 2141 If unsure, leave the default value. 2142 2143endmenu # "Kernel Features" 2144 2145menu "Boot options" 2146 2147config ARM64_ACPI_PARKING_PROTOCOL 2148 bool "Enable support for the ARM64 ACPI parking protocol" 2149 depends on ACPI 2150 help 2151 Enable support for the ARM64 ACPI parking protocol. If disabled 2152 the kernel will not allow booting through the ARM64 ACPI parking 2153 protocol even if the corresponding data is present in the ACPI 2154 MADT table. 2155 2156config CMDLINE 2157 string "Default kernel command string" 2158 default "" 2159 help 2160 Provide a set of default command-line options at build time by 2161 entering them here. As a minimum, you should specify the the 2162 root device (e.g. root=/dev/nfs). 2163 2164choice 2165 prompt "Kernel command line type" if CMDLINE != "" 2166 default CMDLINE_FROM_BOOTLOADER 2167 help 2168 Choose how the kernel will handle the provided default kernel 2169 command line string. 2170 2171config CMDLINE_FROM_BOOTLOADER 2172 bool "Use bootloader kernel arguments if available" 2173 help 2174 Uses the command-line options passed by the boot loader. If 2175 the boot loader doesn't provide any, the default kernel command 2176 string provided in CMDLINE will be used. 2177 2178config CMDLINE_FORCE 2179 bool "Always use the default kernel command string" 2180 help 2181 Always use the default kernel command string, even if the boot 2182 loader passes other arguments to the kernel. 2183 This is useful if you cannot or don't want to change the 2184 command-line options your boot loader passes to the kernel. 2185 2186endchoice 2187 2188config EFI_STUB 2189 bool 2190 2191config EFI 2192 bool "UEFI runtime support" 2193 depends on OF && !CPU_BIG_ENDIAN 2194 depends on KERNEL_MODE_NEON 2195 select ARCH_SUPPORTS_ACPI 2196 select LIBFDT 2197 select UCS2_STRING 2198 select EFI_PARAMS_FROM_FDT 2199 select EFI_RUNTIME_WRAPPERS 2200 select EFI_STUB 2201 select EFI_GENERIC_STUB 2202 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2203 default y 2204 help 2205 This option provides support for runtime services provided 2206 by UEFI firmware (such as non-volatile variables, realtime 2207 clock, and platform reset). A UEFI stub is also provided to 2208 allow the kernel to be booted as an EFI application. This 2209 is only useful on systems that have UEFI firmware. 2210 2211config DMI 2212 bool "Enable support for SMBIOS (DMI) tables" 2213 depends on EFI 2214 default y 2215 help 2216 This enables SMBIOS/DMI feature for systems. 2217 2218 This option is only useful on systems that have UEFI firmware. 2219 However, even with this option, the resultant kernel should 2220 continue to boot on existing non-UEFI platforms. 2221 2222endmenu # "Boot options" 2223 2224menu "Power management options" 2225 2226source "kernel/power/Kconfig" 2227 2228config ARCH_HIBERNATION_POSSIBLE 2229 def_bool y 2230 depends on CPU_PM 2231 2232config ARCH_HIBERNATION_HEADER 2233 def_bool y 2234 depends on HIBERNATION 2235 2236config ARCH_SUSPEND_POSSIBLE 2237 def_bool y 2238 2239endmenu # "Power management options" 2240 2241menu "CPU Power Management" 2242 2243source "drivers/cpuidle/Kconfig" 2244 2245source "drivers/cpufreq/Kconfig" 2246 2247endmenu # "CPU Power Management" 2248 2249source "drivers/acpi/Kconfig" 2250 2251source "arch/arm64/kvm/Kconfig" 2252 2253