1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_STATE 14 select ARCH_HAS_DEBUG_VIRTUAL 15 select ARCH_HAS_DEBUG_VM_PGTABLE 16 select ARCH_HAS_DMA_PREP_COHERENT 17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 18 select ARCH_HAS_FAST_MULTIPLIER 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_HAS_GIGANTIC_PAGE 22 select ARCH_HAS_KCOV 23 select ARCH_HAS_KEEPINITRD 24 select ARCH_HAS_MEMBARRIER_SYNC_CORE 25 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 26 select ARCH_HAS_PTE_DEVMAP 27 select ARCH_HAS_PTE_SPECIAL 28 select ARCH_HAS_SETUP_DMA_OPS 29 select ARCH_HAS_SET_DIRECT_MAP 30 select ARCH_HAS_SET_MEMORY 31 select ARCH_STACKWALK 32 select ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_HAS_STRICT_MODULE_RWX 34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 35 select ARCH_HAS_SYNC_DMA_FOR_CPU 36 select ARCH_HAS_SYSCALL_WRAPPER 37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 39 select ARCH_HAVE_ELF_PROT 40 select ARCH_HAVE_NMI_SAFE_CMPXCHG 41 select ARCH_INLINE_READ_LOCK if !PREEMPTION 42 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 43 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 44 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 45 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 46 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 47 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 48 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 49 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 50 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 51 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 52 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 53 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 54 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 55 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 56 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 57 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 58 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 59 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 60 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 61 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 62 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 63 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 64 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 65 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 67 select ARCH_KEEP_MEMBLOCK 68 select ARCH_USE_CMPXCHG_LOCKREF 69 select ARCH_USE_GNU_PROPERTY 70 select ARCH_USE_QUEUED_RWLOCKS 71 select ARCH_USE_QUEUED_SPINLOCKS 72 select ARCH_USE_SYM_ANNOTATIONS 73 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 74 select ARCH_SUPPORTS_MEMORY_FAILURE 75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 76 select ARCH_SUPPORTS_ATOMIC_RMW 77 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG) 78 select ARCH_SUPPORTS_NUMA_BALANCING 79 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 80 select ARCH_WANT_DEFAULT_BPF_JIT 81 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 82 select ARCH_WANT_FRAME_POINTERS 83 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 84 select ARCH_WANT_LD_ORPHAN_WARN 85 select ARCH_HAS_UBSAN_SANITIZE_ALL 86 select ARM_AMBA 87 select ARM_ARCH_TIMER 88 select ARM_GIC 89 select AUDIT_ARCH_COMPAT_GENERIC 90 select ARM_GIC_V2M if PCI 91 select ARM_GIC_V3 92 select ARM_GIC_V3_ITS if PCI 93 select ARM_PSCI_FW 94 select BUILDTIME_TABLE_SORT 95 select CLONE_BACKWARDS 96 select COMMON_CLK 97 select CPU_PM if (SUSPEND || CPU_IDLE) 98 select CRC32 99 select DCACHE_WORD_ACCESS 100 select DMA_DIRECT_REMAP 101 select EDAC_SUPPORT 102 select FRAME_POINTER 103 select GENERIC_ALLOCATOR 104 select GENERIC_ARCH_TOPOLOGY 105 select GENERIC_CLOCKEVENTS_BROADCAST 106 select GENERIC_CPU_AUTOPROBE 107 select GENERIC_CPU_VULNERABILITIES 108 select GENERIC_EARLY_IOREMAP 109 select GENERIC_IDLE_POLL_SETUP 110 select GENERIC_IRQ_IPI 111 select GENERIC_IRQ_MULTI_HANDLER 112 select GENERIC_IRQ_PROBE 113 select GENERIC_IRQ_SHOW 114 select GENERIC_IRQ_SHOW_LEVEL 115 select GENERIC_LIB_DEVMEM_IS_ALLOWED 116 select GENERIC_PCI_IOMAP 117 select GENERIC_PTDUMP 118 select GENERIC_SCHED_CLOCK 119 select GENERIC_SMP_IDLE_THREAD 120 select GENERIC_STRNCPY_FROM_USER 121 select GENERIC_STRNLEN_USER 122 select GENERIC_TIME_VSYSCALL 123 select GENERIC_GETTIMEOFDAY 124 select GENERIC_VDSO_TIME_NS 125 select HANDLE_DOMAIN_IRQ 126 select HARDIRQS_SW_RESEND 127 select HAVE_MOVE_PMD 128 select HAVE_MOVE_PUD 129 select HAVE_PCI 130 select HAVE_ACPI_APEI if (ACPI && EFI) 131 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 132 select HAVE_ARCH_AUDITSYSCALL 133 select HAVE_ARCH_BITREVERSE 134 select HAVE_ARCH_COMPILER_H 135 select HAVE_ARCH_HUGE_VMAP 136 select HAVE_ARCH_JUMP_LABEL 137 select HAVE_ARCH_JUMP_LABEL_RELATIVE 138 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 139 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 140 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 141 select HAVE_ARCH_KGDB 142 select HAVE_ARCH_MMAP_RND_BITS 143 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 144 select HAVE_ARCH_PFN_VALID 145 select HAVE_ARCH_PREL32_RELOCATIONS 146 select HAVE_ARCH_SECCOMP_FILTER 147 select HAVE_ARCH_STACKLEAK 148 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 149 select HAVE_ARCH_TRACEHOOK 150 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 151 select HAVE_ARCH_VMAP_STACK 152 select HAVE_ARM_SMCCC 153 select HAVE_ASM_MODVERSIONS 154 select HAVE_EBPF_JIT 155 select HAVE_C_RECORDMCOUNT 156 select HAVE_CMPXCHG_DOUBLE 157 select HAVE_CMPXCHG_LOCAL 158 select HAVE_CONTEXT_TRACKING 159 select HAVE_DEBUG_BUGVERBOSE 160 select HAVE_DEBUG_KMEMLEAK 161 select HAVE_DMA_CONTIGUOUS 162 select HAVE_DYNAMIC_FTRACE 163 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 164 if $(cc-option,-fpatchable-function-entry=2) 165 select HAVE_EFFICIENT_UNALIGNED_ACCESS 166 select HAVE_FAST_GUP 167 select HAVE_FTRACE_MCOUNT_RECORD 168 select HAVE_FUNCTION_TRACER 169 select HAVE_FUNCTION_ERROR_INJECTION 170 select HAVE_FUNCTION_GRAPH_TRACER 171 select HAVE_GCC_PLUGINS 172 select HAVE_HW_BREAKPOINT if PERF_EVENTS 173 select HAVE_IRQ_TIME_ACCOUNTING 174 select HAVE_NMI 175 select HAVE_PATA_PLATFORM 176 select HAVE_PERF_EVENTS 177 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS 178 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI 179 select HAVE_PERF_REGS 180 select HAVE_PERF_USER_STACK_DUMP 181 select HAVE_REGS_AND_STACK_ACCESS_API 182 select HAVE_FUNCTION_ARG_ACCESS_API 183 select HAVE_FUTEX_CMPXCHG if FUTEX 184 select MMU_GATHER_RCU_TABLE_FREE 185 select HAVE_RSEQ 186 select HAVE_STACKPROTECTOR 187 select HAVE_SYSCALL_TRACEPOINTS 188 select HAVE_KPROBES 189 select HAVE_KRETPROBES 190 select HAVE_GENERIC_VDSO 191 select IOMMU_DMA if IOMMU_SUPPORT 192 select IRQ_DOMAIN 193 select IRQ_FORCED_THREADING 194 select MODULES_USE_ELF_RELA 195 select NEED_DMA_MAP_STATE 196 select NEED_SG_DMA_LENGTH 197 select OF 198 select OF_EARLY_FLATTREE 199 select PCI_DOMAINS_GENERIC if PCI 200 select PCI_ECAM if (ACPI && PCI) 201 select PCI_SYSCALL if PCI 202 select POWER_RESET 203 select POWER_SUPPLY 204 select SPARSE_IRQ 205 select SWIOTLB 206 select SYSCTL_EXCEPTION_TRACE 207 select THREAD_INFO_IN_TASK 208 help 209 ARM 64-bit (AArch64) Linux support. 210 211config 64BIT 212 def_bool y 213 214config MMU 215 def_bool y 216 217config ARM64_PAGE_SHIFT 218 int 219 default 16 if ARM64_64K_PAGES 220 default 14 if ARM64_16K_PAGES 221 default 12 222 223config ARM64_CONT_PTE_SHIFT 224 int 225 default 5 if ARM64_64K_PAGES 226 default 7 if ARM64_16K_PAGES 227 default 4 228 229config ARM64_CONT_PMD_SHIFT 230 int 231 default 5 if ARM64_64K_PAGES 232 default 5 if ARM64_16K_PAGES 233 default 4 234 235config ARCH_MMAP_RND_BITS_MIN 236 default 14 if ARM64_64K_PAGES 237 default 16 if ARM64_16K_PAGES 238 default 18 239 240# max bits determined by the following formula: 241# VA_BITS - PAGE_SHIFT - 3 242config ARCH_MMAP_RND_BITS_MAX 243 default 19 if ARM64_VA_BITS=36 244 default 24 if ARM64_VA_BITS=39 245 default 27 if ARM64_VA_BITS=42 246 default 30 if ARM64_VA_BITS=47 247 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 248 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 249 default 33 if ARM64_VA_BITS=48 250 default 14 if ARM64_64K_PAGES 251 default 16 if ARM64_16K_PAGES 252 default 18 253 254config ARCH_MMAP_RND_COMPAT_BITS_MIN 255 default 7 if ARM64_64K_PAGES 256 default 9 if ARM64_16K_PAGES 257 default 11 258 259config ARCH_MMAP_RND_COMPAT_BITS_MAX 260 default 16 261 262config NO_IOPORT_MAP 263 def_bool y if !PCI 264 265config STACKTRACE_SUPPORT 266 def_bool y 267 268config ILLEGAL_POINTER_VALUE 269 hex 270 default 0xdead000000000000 271 272config LOCKDEP_SUPPORT 273 def_bool y 274 275config TRACE_IRQFLAGS_SUPPORT 276 def_bool y 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config GENERIC_BUG_RELATIVE_POINTERS 283 def_bool y 284 depends on GENERIC_BUG 285 286config GENERIC_HWEIGHT 287 def_bool y 288 289config GENERIC_CSUM 290 def_bool y 291 292config GENERIC_CALIBRATE_DELAY 293 def_bool y 294 295config ZONE_DMA 296 bool "Support DMA zone" if EXPERT 297 default y 298 299config ZONE_DMA32 300 bool "Support DMA32 zone" if EXPERT 301 default y 302 303config ARCH_ENABLE_MEMORY_HOTPLUG 304 def_bool y 305 306config ARCH_ENABLE_MEMORY_HOTREMOVE 307 def_bool y 308 309config SMP 310 def_bool y 311 312config KERNEL_MODE_NEON 313 def_bool y 314 315config FIX_EARLYCON_MEM 316 def_bool y 317 318config PGTABLE_LEVELS 319 int 320 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 321 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 322 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 323 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 324 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 325 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 326 327config ARCH_SUPPORTS_UPROBES 328 def_bool y 329 330config ARCH_PROC_KCORE_TEXT 331 def_bool y 332 333config BROKEN_GAS_INST 334 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 335 336config KASAN_SHADOW_OFFSET 337 hex 338 depends on KASAN_GENERIC || KASAN_SW_TAGS 339 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 340 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 341 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 342 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 343 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 344 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 345 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 346 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 347 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 348 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 349 default 0xffffffffffffffff 350 351source "arch/arm64/Kconfig.platforms" 352 353menu "Kernel Features" 354 355menu "ARM errata workarounds via the alternatives framework" 356 357config ARM64_WORKAROUND_CLEAN_CACHE 358 bool 359 360config ARM64_ERRATUM_826319 361 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 362 default y 363 select ARM64_WORKAROUND_CLEAN_CACHE 364 help 365 This option adds an alternative code sequence to work around ARM 366 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 367 AXI master interface and an L2 cache. 368 369 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 370 and is unable to accept a certain write via this interface, it will 371 not progress on read data presented on the read data channel and the 372 system can deadlock. 373 374 The workaround promotes data cache clean instructions to 375 data cache clean-and-invalidate. 376 Please note that this does not necessarily enable the workaround, 377 as it depends on the alternative framework, which will only patch 378 the kernel if an affected CPU is detected. 379 380 If unsure, say Y. 381 382config ARM64_ERRATUM_827319 383 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 384 default y 385 select ARM64_WORKAROUND_CLEAN_CACHE 386 help 387 This option adds an alternative code sequence to work around ARM 388 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 389 master interface and an L2 cache. 390 391 Under certain conditions this erratum can cause a clean line eviction 392 to occur at the same time as another transaction to the same address 393 on the AMBA 5 CHI interface, which can cause data corruption if the 394 interconnect reorders the two transactions. 395 396 The workaround promotes data cache clean instructions to 397 data cache clean-and-invalidate. 398 Please note that this does not necessarily enable the workaround, 399 as it depends on the alternative framework, which will only patch 400 the kernel if an affected CPU is detected. 401 402 If unsure, say Y. 403 404config ARM64_ERRATUM_824069 405 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 406 default y 407 select ARM64_WORKAROUND_CLEAN_CACHE 408 help 409 This option adds an alternative code sequence to work around ARM 410 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 411 to a coherent interconnect. 412 413 If a Cortex-A53 processor is executing a store or prefetch for 414 write instruction at the same time as a processor in another 415 cluster is executing a cache maintenance operation to the same 416 address, then this erratum might cause a clean cache line to be 417 incorrectly marked as dirty. 418 419 The workaround promotes data cache clean instructions to 420 data cache clean-and-invalidate. 421 Please note that this option does not necessarily enable the 422 workaround, as it depends on the alternative framework, which will 423 only patch the kernel if an affected CPU is detected. 424 425 If unsure, say Y. 426 427config ARM64_ERRATUM_819472 428 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 429 default y 430 select ARM64_WORKAROUND_CLEAN_CACHE 431 help 432 This option adds an alternative code sequence to work around ARM 433 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 434 present when it is connected to a coherent interconnect. 435 436 If the processor is executing a load and store exclusive sequence at 437 the same time as a processor in another cluster is executing a cache 438 maintenance operation to the same address, then this erratum might 439 cause data corruption. 440 441 The workaround promotes data cache clean instructions to 442 data cache clean-and-invalidate. 443 Please note that this does not necessarily enable the workaround, 444 as it depends on the alternative framework, which will only patch 445 the kernel if an affected CPU is detected. 446 447 If unsure, say Y. 448 449config ARM64_ERRATUM_832075 450 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 451 default y 452 help 453 This option adds an alternative code sequence to work around ARM 454 erratum 832075 on Cortex-A57 parts up to r1p2. 455 456 Affected Cortex-A57 parts might deadlock when exclusive load/store 457 instructions to Write-Back memory are mixed with Device loads. 458 459 The workaround is to promote device loads to use Load-Acquire 460 semantics. 461 Please note that this does not necessarily enable the workaround, 462 as it depends on the alternative framework, which will only patch 463 the kernel if an affected CPU is detected. 464 465 If unsure, say Y. 466 467config ARM64_ERRATUM_834220 468 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 469 depends on KVM 470 default y 471 help 472 This option adds an alternative code sequence to work around ARM 473 erratum 834220 on Cortex-A57 parts up to r1p2. 474 475 Affected Cortex-A57 parts might report a Stage 2 translation 476 fault as the result of a Stage 1 fault for load crossing a 477 page boundary when there is a permission or device memory 478 alignment fault at Stage 1 and a translation fault at Stage 2. 479 480 The workaround is to verify that the Stage 1 translation 481 doesn't generate a fault before handling the Stage 2 fault. 482 Please note that this does not necessarily enable the workaround, 483 as it depends on the alternative framework, which will only patch 484 the kernel if an affected CPU is detected. 485 486 If unsure, say Y. 487 488config ARM64_ERRATUM_845719 489 bool "Cortex-A53: 845719: a load might read incorrect data" 490 depends on COMPAT 491 default y 492 help 493 This option adds an alternative code sequence to work around ARM 494 erratum 845719 on Cortex-A53 parts up to r0p4. 495 496 When running a compat (AArch32) userspace on an affected Cortex-A53 497 part, a load at EL0 from a virtual address that matches the bottom 32 498 bits of the virtual address used by a recent load at (AArch64) EL1 499 might return incorrect data. 500 501 The workaround is to write the contextidr_el1 register on exception 502 return to a 32-bit task. 503 Please note that this does not necessarily enable the workaround, 504 as it depends on the alternative framework, which will only patch 505 the kernel if an affected CPU is detected. 506 507 If unsure, say Y. 508 509config ARM64_ERRATUM_843419 510 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 511 default y 512 select ARM64_MODULE_PLTS if MODULES 513 help 514 This option links the kernel with '--fix-cortex-a53-843419' and 515 enables PLT support to replace certain ADRP instructions, which can 516 cause subsequent memory accesses to use an incorrect address on 517 Cortex-A53 parts up to r0p4. 518 519 If unsure, say Y. 520 521config ARM64_ERRATUM_1024718 522 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 523 default y 524 help 525 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 526 527 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect 528 update of the hardware dirty bit when the DBM/AP bits are updated 529 without a break-before-make. The workaround is to disable the usage 530 of hardware DBM locally on the affected cores. CPUs not affected by 531 this erratum will continue to use the feature. 532 533 If unsure, say Y. 534 535config ARM64_ERRATUM_1418040 536 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 537 default y 538 depends on COMPAT 539 help 540 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 541 errata 1188873 and 1418040. 542 543 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 544 cause register corruption when accessing the timer registers 545 from AArch32 userspace. 546 547 If unsure, say Y. 548 549config ARM64_WORKAROUND_SPECULATIVE_AT 550 bool 551 552config ARM64_ERRATUM_1165522 553 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 554 default y 555 select ARM64_WORKAROUND_SPECULATIVE_AT 556 help 557 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 558 559 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 560 corrupted TLBs by speculating an AT instruction during a guest 561 context switch. 562 563 If unsure, say Y. 564 565config ARM64_ERRATUM_1319367 566 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 567 default y 568 select ARM64_WORKAROUND_SPECULATIVE_AT 569 help 570 This option adds work arounds for ARM Cortex-A57 erratum 1319537 571 and A72 erratum 1319367 572 573 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 574 speculating an AT instruction during a guest context switch. 575 576 If unsure, say Y. 577 578config ARM64_ERRATUM_1530923 579 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 580 default y 581 select ARM64_WORKAROUND_SPECULATIVE_AT 582 help 583 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 584 585 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 586 corrupted TLBs by speculating an AT instruction during a guest 587 context switch. 588 589 If unsure, say Y. 590 591config ARM64_WORKAROUND_REPEAT_TLBI 592 bool 593 594config ARM64_ERRATUM_1286807 595 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 596 default y 597 select ARM64_WORKAROUND_REPEAT_TLBI 598 help 599 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 600 601 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 602 address for a cacheable mapping of a location is being 603 accessed by a core while another core is remapping the virtual 604 address to a new physical page using the recommended 605 break-before-make sequence, then under very rare circumstances 606 TLBI+DSB completes before a read using the translation being 607 invalidated has been observed by other observers. The 608 workaround repeats the TLBI+DSB operation. 609 610config ARM64_ERRATUM_1463225 611 bool "Cortex-A76: Software Step might prevent interrupt recognition" 612 default y 613 help 614 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 615 616 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 617 of a system call instruction (SVC) can prevent recognition of 618 subsequent interrupts when software stepping is disabled in the 619 exception handler of the system call and either kernel debugging 620 is enabled or VHE is in use. 621 622 Work around the erratum by triggering a dummy step exception 623 when handling a system call from a task that is being stepped 624 in a VHE configuration of the kernel. 625 626 If unsure, say Y. 627 628config ARM64_ERRATUM_1542419 629 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 630 default y 631 help 632 This option adds a workaround for ARM Neoverse-N1 erratum 633 1542419. 634 635 Affected Neoverse-N1 cores could execute a stale instruction when 636 modified by another CPU. The workaround depends on a firmware 637 counterpart. 638 639 Workaround the issue by hiding the DIC feature from EL0. This 640 forces user-space to perform cache maintenance. 641 642 If unsure, say Y. 643 644config ARM64_ERRATUM_1508412 645 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 646 default y 647 help 648 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 649 650 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 651 of a store-exclusive or read of PAR_EL1 and a load with device or 652 non-cacheable memory attributes. The workaround depends on a firmware 653 counterpart. 654 655 KVM guests must also have the workaround implemented or they can 656 deadlock the system. 657 658 Work around the issue by inserting DMB SY barriers around PAR_EL1 659 register reads and warning KVM users. The DMB barrier is sufficient 660 to prevent a speculative PAR_EL1 read. 661 662 If unsure, say Y. 663 664config CAVIUM_ERRATUM_22375 665 bool "Cavium erratum 22375, 24313" 666 default y 667 help 668 Enable workaround for errata 22375 and 24313. 669 670 This implements two gicv3-its errata workarounds for ThunderX. Both 671 with a small impact affecting only ITS table allocation. 672 673 erratum 22375: only alloc 8MB table size 674 erratum 24313: ignore memory access type 675 676 The fixes are in ITS initialization and basically ignore memory access 677 type and table size provided by the TYPER and BASER registers. 678 679 If unsure, say Y. 680 681config CAVIUM_ERRATUM_23144 682 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 683 depends on NUMA 684 default y 685 help 686 ITS SYNC command hang for cross node io and collections/cpu mapping. 687 688 If unsure, say Y. 689 690config CAVIUM_ERRATUM_23154 691 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 692 default y 693 help 694 The gicv3 of ThunderX requires a modified version for 695 reading the IAR status to ensure data synchronization 696 (access to icc_iar1_el1 is not sync'ed before and after). 697 698 If unsure, say Y. 699 700config CAVIUM_ERRATUM_27456 701 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 702 default y 703 help 704 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 705 instructions may cause the icache to become corrupted if it 706 contains data for a non-current ASID. The fix is to 707 invalidate the icache when changing the mm context. 708 709 If unsure, say Y. 710 711config CAVIUM_ERRATUM_30115 712 bool "Cavium erratum 30115: Guest may disable interrupts in host" 713 default y 714 help 715 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 716 1.2, and T83 Pass 1.0, KVM guest execution may disable 717 interrupts in host. Trapping both GICv3 group-0 and group-1 718 accesses sidesteps the issue. 719 720 If unsure, say Y. 721 722config CAVIUM_TX2_ERRATUM_219 723 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 724 default y 725 help 726 On Cavium ThunderX2, a load, store or prefetch instruction between a 727 TTBR update and the corresponding context synchronizing operation can 728 cause a spurious Data Abort to be delivered to any hardware thread in 729 the CPU core. 730 731 Work around the issue by avoiding the problematic code sequence and 732 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 733 trap handler performs the corresponding register access, skips the 734 instruction and ensures context synchronization by virtue of the 735 exception return. 736 737 If unsure, say Y. 738 739config FUJITSU_ERRATUM_010001 740 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 741 default y 742 help 743 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 744 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 745 accesses may cause undefined fault (Data abort, DFSC=0b111111). 746 This fault occurs under a specific hardware condition when a 747 load/store instruction performs an address translation using: 748 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 749 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 750 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 751 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 752 753 The workaround is to ensure these bits are clear in TCR_ELx. 754 The workaround only affects the Fujitsu-A64FX. 755 756 If unsure, say Y. 757 758config HISILICON_ERRATUM_161600802 759 bool "Hip07 161600802: Erroneous redistributor VLPI base" 760 default y 761 help 762 The HiSilicon Hip07 SoC uses the wrong redistributor base 763 when issued ITS commands such as VMOVP and VMAPP, and requires 764 a 128kB offset to be applied to the target address in this commands. 765 766 If unsure, say Y. 767 768config QCOM_FALKOR_ERRATUM_1003 769 bool "Falkor E1003: Incorrect translation due to ASID change" 770 default y 771 help 772 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 773 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 774 in TTBR1_EL1, this situation only occurs in the entry trampoline and 775 then only for entries in the walk cache, since the leaf translation 776 is unchanged. Work around the erratum by invalidating the walk cache 777 entries for the trampoline before entering the kernel proper. 778 779config QCOM_FALKOR_ERRATUM_1009 780 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 781 default y 782 select ARM64_WORKAROUND_REPEAT_TLBI 783 help 784 On Falkor v1, the CPU may prematurely complete a DSB following a 785 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 786 one more time to fix the issue. 787 788 If unsure, say Y. 789 790config QCOM_QDF2400_ERRATUM_0065 791 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 792 default y 793 help 794 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 795 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 796 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 797 798 If unsure, say Y. 799 800config QCOM_FALKOR_ERRATUM_E1041 801 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 802 default y 803 help 804 Falkor CPU may speculatively fetch instructions from an improper 805 memory location when MMU translation is changed from SCTLR_ELn[M]=1 806 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 807 808 If unsure, say Y. 809 810config SOCIONEXT_SYNQUACER_PREITS 811 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 812 default y 813 help 814 Socionext Synquacer SoCs implement a separate h/w block to generate 815 MSI doorbell writes with non-zero values for the device ID. 816 817 If unsure, say Y. 818 819endmenu 820 821 822choice 823 prompt "Page size" 824 default ARM64_4K_PAGES 825 help 826 Page size (translation granule) configuration. 827 828config ARM64_4K_PAGES 829 bool "4KB" 830 help 831 This feature enables 4KB pages support. 832 833config ARM64_16K_PAGES 834 bool "16KB" 835 help 836 The system will use 16KB pages support. AArch32 emulation 837 requires applications compiled with 16K (or a multiple of 16K) 838 aligned segments. 839 840config ARM64_64K_PAGES 841 bool "64KB" 842 help 843 This feature enables 64KB pages support (4KB by default) 844 allowing only two levels of page tables and faster TLB 845 look-up. AArch32 emulation requires applications compiled 846 with 64K aligned segments. 847 848endchoice 849 850choice 851 prompt "Virtual address space size" 852 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 853 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 854 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 855 help 856 Allows choosing one of multiple possible virtual address 857 space sizes. The level of translation table is determined by 858 a combination of page size and virtual address space size. 859 860config ARM64_VA_BITS_36 861 bool "36-bit" if EXPERT 862 depends on ARM64_16K_PAGES 863 864config ARM64_VA_BITS_39 865 bool "39-bit" 866 depends on ARM64_4K_PAGES 867 868config ARM64_VA_BITS_42 869 bool "42-bit" 870 depends on ARM64_64K_PAGES 871 872config ARM64_VA_BITS_47 873 bool "47-bit" 874 depends on ARM64_16K_PAGES 875 876config ARM64_VA_BITS_48 877 bool "48-bit" 878 879config ARM64_VA_BITS_52 880 bool "52-bit" 881 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 882 help 883 Enable 52-bit virtual addressing for userspace when explicitly 884 requested via a hint to mmap(). The kernel will also use 52-bit 885 virtual addresses for its own mappings (provided HW support for 886 this feature is available, otherwise it reverts to 48-bit). 887 888 NOTE: Enabling 52-bit virtual addressing in conjunction with 889 ARMv8.3 Pointer Authentication will result in the PAC being 890 reduced from 7 bits to 3 bits, which may have a significant 891 impact on its susceptibility to brute-force attacks. 892 893 If unsure, select 48-bit virtual addressing instead. 894 895endchoice 896 897config ARM64_FORCE_52BIT 898 bool "Force 52-bit virtual addresses for userspace" 899 depends on ARM64_VA_BITS_52 && EXPERT 900 help 901 For systems with 52-bit userspace VAs enabled, the kernel will attempt 902 to maintain compatibility with older software by providing 48-bit VAs 903 unless a hint is supplied to mmap. 904 905 This configuration option disables the 48-bit compatibility logic, and 906 forces all userspace addresses to be 52-bit on HW that supports it. One 907 should only enable this configuration option for stress testing userspace 908 memory management code. If unsure say N here. 909 910config ARM64_VA_BITS 911 int 912 default 36 if ARM64_VA_BITS_36 913 default 39 if ARM64_VA_BITS_39 914 default 42 if ARM64_VA_BITS_42 915 default 47 if ARM64_VA_BITS_47 916 default 48 if ARM64_VA_BITS_48 917 default 52 if ARM64_VA_BITS_52 918 919choice 920 prompt "Physical address space size" 921 default ARM64_PA_BITS_48 922 help 923 Choose the maximum physical address range that the kernel will 924 support. 925 926config ARM64_PA_BITS_48 927 bool "48-bit" 928 929config ARM64_PA_BITS_52 930 bool "52-bit (ARMv8.2)" 931 depends on ARM64_64K_PAGES 932 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 933 help 934 Enable support for a 52-bit physical address space, introduced as 935 part of the ARMv8.2-LPA extension. 936 937 With this enabled, the kernel will also continue to work on CPUs that 938 do not support ARMv8.2-LPA, but with some added memory overhead (and 939 minor performance overhead). 940 941endchoice 942 943config ARM64_PA_BITS 944 int 945 default 48 if ARM64_PA_BITS_48 946 default 52 if ARM64_PA_BITS_52 947 948choice 949 prompt "Endianness" 950 default CPU_LITTLE_ENDIAN 951 help 952 Select the endianness of data accesses performed by the CPU. Userspace 953 applications will need to be compiled and linked for the endianness 954 that is selected here. 955 956config CPU_BIG_ENDIAN 957 bool "Build big-endian kernel" 958 help 959 Say Y if you plan on running a kernel with a big-endian userspace. 960 961config CPU_LITTLE_ENDIAN 962 bool "Build little-endian kernel" 963 help 964 Say Y if you plan on running a kernel with a little-endian userspace. 965 This is usually the case for distributions targeting arm64. 966 967endchoice 968 969config SCHED_MC 970 bool "Multi-core scheduler support" 971 help 972 Multi-core scheduler support improves the CPU scheduler's decision 973 making when dealing with multi-core CPU chips at a cost of slightly 974 increased overhead in some places. If unsure say N here. 975 976config SCHED_SMT 977 bool "SMT scheduler support" 978 help 979 Improves the CPU scheduler's decision making when dealing with 980 MultiThreading at a cost of slightly increased overhead in some 981 places. If unsure say N here. 982 983config NR_CPUS 984 int "Maximum number of CPUs (2-4096)" 985 range 2 4096 986 default "256" 987 988config HOTPLUG_CPU 989 bool "Support for hot-pluggable CPUs" 990 select GENERIC_IRQ_MIGRATION 991 help 992 Say Y here to experiment with turning CPUs off and on. CPUs 993 can be controlled through /sys/devices/system/cpu. 994 995# Common NUMA Features 996config NUMA 997 bool "NUMA Memory Allocation and Scheduler Support" 998 select GENERIC_ARCH_NUMA 999 select ACPI_NUMA if ACPI 1000 select OF_NUMA 1001 help 1002 Enable NUMA (Non-Uniform Memory Access) support. 1003 1004 The kernel will try to allocate memory used by a CPU on the 1005 local memory of the CPU and add some more 1006 NUMA awareness to the kernel. 1007 1008config NODES_SHIFT 1009 int "Maximum NUMA Nodes (as a power of 2)" 1010 range 1 10 1011 default "4" 1012 depends on NEED_MULTIPLE_NODES 1013 help 1014 Specify the maximum number of NUMA Nodes available on the target 1015 system. Increases memory reserved to accommodate various tables. 1016 1017config USE_PERCPU_NUMA_NODE_ID 1018 def_bool y 1019 depends on NUMA 1020 1021config HAVE_SETUP_PER_CPU_AREA 1022 def_bool y 1023 depends on NUMA 1024 1025config NEED_PER_CPU_EMBED_FIRST_CHUNK 1026 def_bool y 1027 depends on NUMA 1028 1029config HOLES_IN_ZONE 1030 def_bool y 1031 1032source "kernel/Kconfig.hz" 1033 1034config ARCH_SPARSEMEM_ENABLE 1035 def_bool y 1036 select SPARSEMEM_VMEMMAP_ENABLE 1037 1038config ARCH_SPARSEMEM_DEFAULT 1039 def_bool ARCH_SPARSEMEM_ENABLE 1040 1041config ARCH_SELECT_MEMORY_MODEL 1042 def_bool ARCH_SPARSEMEM_ENABLE 1043 1044config ARCH_FLATMEM_ENABLE 1045 def_bool !NUMA 1046 1047config HW_PERF_EVENTS 1048 def_bool y 1049 depends on ARM_PMU 1050 1051config SYS_SUPPORTS_HUGETLBFS 1052 def_bool y 1053 1054config ARCH_WANT_HUGE_PMD_SHARE 1055 1056config ARCH_HAS_CACHE_LINE_SIZE 1057 def_bool y 1058 1059config ARCH_ENABLE_SPLIT_PMD_PTLOCK 1060 def_bool y if PGTABLE_LEVELS > 2 1061 1062# Supported by clang >= 7.0 1063config CC_HAVE_SHADOW_CALL_STACK 1064 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1065 1066config PARAVIRT 1067 bool "Enable paravirtualization code" 1068 help 1069 This changes the kernel so it can modify itself when it is run 1070 under a hypervisor, potentially improving performance significantly 1071 over full virtualization. 1072 1073config PARAVIRT_TIME_ACCOUNTING 1074 bool "Paravirtual steal time accounting" 1075 select PARAVIRT 1076 help 1077 Select this option to enable fine granularity task steal time 1078 accounting. Time spent executing other tasks in parallel with 1079 the current vCPU is discounted from the vCPU power. To account for 1080 that, there can be a small performance impact. 1081 1082 If in doubt, say N here. 1083 1084config KEXEC 1085 depends on PM_SLEEP_SMP 1086 select KEXEC_CORE 1087 bool "kexec system call" 1088 help 1089 kexec is a system call that implements the ability to shutdown your 1090 current kernel, and to start another kernel. It is like a reboot 1091 but it is independent of the system firmware. And like a reboot 1092 you can start any kernel with it, not just Linux. 1093 1094config KEXEC_FILE 1095 bool "kexec file based system call" 1096 select KEXEC_CORE 1097 help 1098 This is new version of kexec system call. This system call is 1099 file based and takes file descriptors as system call argument 1100 for kernel and initramfs as opposed to list of segments as 1101 accepted by previous system call. 1102 1103config KEXEC_SIG 1104 bool "Verify kernel signature during kexec_file_load() syscall" 1105 depends on KEXEC_FILE 1106 help 1107 Select this option to verify a signature with loaded kernel 1108 image. If configured, any attempt of loading a image without 1109 valid signature will fail. 1110 1111 In addition to that option, you need to enable signature 1112 verification for the corresponding kernel image type being 1113 loaded in order for this to work. 1114 1115config KEXEC_IMAGE_VERIFY_SIG 1116 bool "Enable Image signature verification support" 1117 default y 1118 depends on KEXEC_SIG 1119 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1120 help 1121 Enable Image signature verification support. 1122 1123comment "Support for PE file signature verification disabled" 1124 depends on KEXEC_SIG 1125 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1126 1127config CRASH_DUMP 1128 bool "Build kdump crash kernel" 1129 help 1130 Generate crash dump after being started by kexec. This should 1131 be normally only set in special crash dump kernels which are 1132 loaded in the main kernel with kexec-tools into a specially 1133 reserved region and then later executed after a crash by 1134 kdump/kexec. 1135 1136 For more details see Documentation/admin-guide/kdump/kdump.rst 1137 1138config XEN_DOM0 1139 def_bool y 1140 depends on XEN 1141 1142config XEN 1143 bool "Xen guest support on ARM64" 1144 depends on ARM64 && OF 1145 select SWIOTLB_XEN 1146 select PARAVIRT 1147 help 1148 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1149 1150config FORCE_MAX_ZONEORDER 1151 int 1152 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 1153 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 1154 default "11" 1155 help 1156 The kernel memory allocator divides physically contiguous memory 1157 blocks into "zones", where each zone is a power of two number of 1158 pages. This option selects the largest power of two that the kernel 1159 keeps in the memory allocator. If you need to allocate very large 1160 blocks of physically contiguous memory, then you may need to 1161 increase this value. 1162 1163 This config option is actually maximum order plus one. For example, 1164 a value of 11 means that the largest free memory block is 2^10 pages. 1165 1166 We make sure that we can allocate upto a HugePage size for each configuration. 1167 Hence we have : 1168 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1169 1170 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1171 4M allocations matching the default size used by generic code. 1172 1173config UNMAP_KERNEL_AT_EL0 1174 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1175 default y 1176 help 1177 Speculation attacks against some high-performance processors can 1178 be used to bypass MMU permission checks and leak kernel data to 1179 userspace. This can be defended against by unmapping the kernel 1180 when running in userspace, mapping it back in on exception entry 1181 via a trampoline page in the vector table. 1182 1183 If unsure, say Y. 1184 1185config RODATA_FULL_DEFAULT_ENABLED 1186 bool "Apply r/o permissions of VM areas also to their linear aliases" 1187 default y 1188 help 1189 Apply read-only attributes of VM areas to the linear alias of 1190 the backing pages as well. This prevents code or read-only data 1191 from being modified (inadvertently or intentionally) via another 1192 mapping of the same memory page. This additional enhancement can 1193 be turned off at runtime by passing rodata=[off|on] (and turned on 1194 with rodata=full if this option is set to 'n') 1195 1196 This requires the linear region to be mapped down to pages, 1197 which may adversely affect performance in some cases. 1198 1199config ARM64_SW_TTBR0_PAN 1200 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1201 help 1202 Enabling this option prevents the kernel from accessing 1203 user-space memory directly by pointing TTBR0_EL1 to a reserved 1204 zeroed area and reserved ASID. The user access routines 1205 restore the valid TTBR0_EL1 temporarily. 1206 1207config ARM64_TAGGED_ADDR_ABI 1208 bool "Enable the tagged user addresses syscall ABI" 1209 default y 1210 help 1211 When this option is enabled, user applications can opt in to a 1212 relaxed ABI via prctl() allowing tagged addresses to be passed 1213 to system calls as pointer arguments. For details, see 1214 Documentation/arm64/tagged-address-abi.rst. 1215 1216menuconfig COMPAT 1217 bool "Kernel support for 32-bit EL0" 1218 depends on ARM64_4K_PAGES || EXPERT 1219 select COMPAT_BINFMT_ELF if BINFMT_ELF 1220 select HAVE_UID16 1221 select OLD_SIGSUSPEND3 1222 select COMPAT_OLD_SIGACTION 1223 help 1224 This option enables support for a 32-bit EL0 running under a 64-bit 1225 kernel at EL1. AArch32-specific components such as system calls, 1226 the user helper functions, VFP support and the ptrace interface are 1227 handled appropriately by the kernel. 1228 1229 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1230 that you will only be able to execute AArch32 binaries that were compiled 1231 with page size aligned segments. 1232 1233 If you want to execute 32-bit userspace applications, say Y. 1234 1235if COMPAT 1236 1237config KUSER_HELPERS 1238 bool "Enable kuser helpers page for 32-bit applications" 1239 default y 1240 help 1241 Warning: disabling this option may break 32-bit user programs. 1242 1243 Provide kuser helpers to compat tasks. The kernel provides 1244 helper code to userspace in read only form at a fixed location 1245 to allow userspace to be independent of the CPU type fitted to 1246 the system. This permits binaries to be run on ARMv4 through 1247 to ARMv8 without modification. 1248 1249 See Documentation/arm/kernel_user_helpers.rst for details. 1250 1251 However, the fixed address nature of these helpers can be used 1252 by ROP (return orientated programming) authors when creating 1253 exploits. 1254 1255 If all of the binaries and libraries which run on your platform 1256 are built specifically for your platform, and make no use of 1257 these helpers, then you can turn this option off to hinder 1258 such exploits. However, in that case, if a binary or library 1259 relying on those helpers is run, it will not function correctly. 1260 1261 Say N here only if you are absolutely certain that you do not 1262 need these helpers; otherwise, the safe option is to say Y. 1263 1264config COMPAT_VDSO 1265 bool "Enable vDSO for 32-bit applications" 1266 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != "" 1267 select GENERIC_COMPAT_VDSO 1268 default y 1269 help 1270 Place in the process address space of 32-bit applications an 1271 ELF shared object providing fast implementations of gettimeofday 1272 and clock_gettime. 1273 1274 You must have a 32-bit build of glibc 2.22 or later for programs 1275 to seamlessly take advantage of this. 1276 1277config THUMB2_COMPAT_VDSO 1278 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1279 depends on COMPAT_VDSO 1280 default y 1281 help 1282 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1283 otherwise with '-marm'. 1284 1285menuconfig ARMV8_DEPRECATED 1286 bool "Emulate deprecated/obsolete ARMv8 instructions" 1287 depends on SYSCTL 1288 help 1289 Legacy software support may require certain instructions 1290 that have been deprecated or obsoleted in the architecture. 1291 1292 Enable this config to enable selective emulation of these 1293 features. 1294 1295 If unsure, say Y 1296 1297if ARMV8_DEPRECATED 1298 1299config SWP_EMULATION 1300 bool "Emulate SWP/SWPB instructions" 1301 help 1302 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1303 they are always undefined. Say Y here to enable software 1304 emulation of these instructions for userspace using LDXR/STXR. 1305 This feature can be controlled at runtime with the abi.swp 1306 sysctl which is disabled by default. 1307 1308 In some older versions of glibc [<=2.8] SWP is used during futex 1309 trylock() operations with the assumption that the code will not 1310 be preempted. This invalid assumption may be more likely to fail 1311 with SWP emulation enabled, leading to deadlock of the user 1312 application. 1313 1314 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1315 on an external transaction monitoring block called a global 1316 monitor to maintain update atomicity. If your system does not 1317 implement a global monitor, this option can cause programs that 1318 perform SWP operations to uncached memory to deadlock. 1319 1320 If unsure, say Y 1321 1322config CP15_BARRIER_EMULATION 1323 bool "Emulate CP15 Barrier instructions" 1324 help 1325 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1326 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1327 strongly recommended to use the ISB, DSB, and DMB 1328 instructions instead. 1329 1330 Say Y here to enable software emulation of these 1331 instructions for AArch32 userspace code. When this option is 1332 enabled, CP15 barrier usage is traced which can help 1333 identify software that needs updating. This feature can be 1334 controlled at runtime with the abi.cp15_barrier sysctl. 1335 1336 If unsure, say Y 1337 1338config SETEND_EMULATION 1339 bool "Emulate SETEND instruction" 1340 help 1341 The SETEND instruction alters the data-endianness of the 1342 AArch32 EL0, and is deprecated in ARMv8. 1343 1344 Say Y here to enable software emulation of the instruction 1345 for AArch32 userspace code. This feature can be controlled 1346 at runtime with the abi.setend sysctl. 1347 1348 Note: All the cpus on the system must have mixed endian support at EL0 1349 for this feature to be enabled. If a new CPU - which doesn't support mixed 1350 endian - is hotplugged in after this feature has been enabled, there could 1351 be unexpected results in the applications. 1352 1353 If unsure, say Y 1354endif 1355 1356endif 1357 1358menu "ARMv8.1 architectural features" 1359 1360config ARM64_HW_AFDBM 1361 bool "Support for hardware updates of the Access and Dirty page flags" 1362 default y 1363 help 1364 The ARMv8.1 architecture extensions introduce support for 1365 hardware updates of the access and dirty information in page 1366 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1367 capable processors, accesses to pages with PTE_AF cleared will 1368 set this bit instead of raising an access flag fault. 1369 Similarly, writes to read-only pages with the DBM bit set will 1370 clear the read-only bit (AP[2]) instead of raising a 1371 permission fault. 1372 1373 Kernels built with this configuration option enabled continue 1374 to work on pre-ARMv8.1 hardware and the performance impact is 1375 minimal. If unsure, say Y. 1376 1377config ARM64_PAN 1378 bool "Enable support for Privileged Access Never (PAN)" 1379 default y 1380 help 1381 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1382 prevents the kernel or hypervisor from accessing user-space (EL0) 1383 memory directly. 1384 1385 Choosing this option will cause any unprotected (not using 1386 copy_to_user et al) memory access to fail with a permission fault. 1387 1388 The feature is detected at runtime, and will remain as a 'nop' 1389 instruction if the cpu does not implement the feature. 1390 1391config AS_HAS_LDAPR 1392 def_bool $(as-instr,.arch_extension rcpc) 1393 1394config ARM64_LSE_ATOMICS 1395 bool 1396 default ARM64_USE_LSE_ATOMICS 1397 depends on $(as-instr,.arch_extension lse) 1398 1399config ARM64_USE_LSE_ATOMICS 1400 bool "Atomic instructions" 1401 depends on JUMP_LABEL 1402 default y 1403 help 1404 As part of the Large System Extensions, ARMv8.1 introduces new 1405 atomic instructions that are designed specifically to scale in 1406 very large systems. 1407 1408 Say Y here to make use of these instructions for the in-kernel 1409 atomic routines. This incurs a small overhead on CPUs that do 1410 not support these instructions and requires the kernel to be 1411 built with binutils >= 2.25 in order for the new instructions 1412 to be used. 1413 1414config ARM64_VHE 1415 bool "Enable support for Virtualization Host Extensions (VHE)" 1416 default y 1417 help 1418 Virtualization Host Extensions (VHE) allow the kernel to run 1419 directly at EL2 (instead of EL1) on processors that support 1420 it. This leads to better performance for KVM, as they reduce 1421 the cost of the world switch. 1422 1423 Selecting this option allows the VHE feature to be detected 1424 at runtime, and does not affect processors that do not 1425 implement this feature. 1426 1427endmenu 1428 1429menu "ARMv8.2 architectural features" 1430 1431config ARM64_PMEM 1432 bool "Enable support for persistent memory" 1433 select ARCH_HAS_PMEM_API 1434 select ARCH_HAS_UACCESS_FLUSHCACHE 1435 help 1436 Say Y to enable support for the persistent memory API based on the 1437 ARMv8.2 DCPoP feature. 1438 1439 The feature is detected at runtime, and the kernel will use DC CVAC 1440 operations if DC CVAP is not supported (following the behaviour of 1441 DC CVAP itself if the system does not define a point of persistence). 1442 1443config ARM64_RAS_EXTN 1444 bool "Enable support for RAS CPU Extensions" 1445 default y 1446 help 1447 CPUs that support the Reliability, Availability and Serviceability 1448 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1449 errors, classify them and report them to software. 1450 1451 On CPUs with these extensions system software can use additional 1452 barriers to determine if faults are pending and read the 1453 classification from a new set of registers. 1454 1455 Selecting this feature will allow the kernel to use these barriers 1456 and access the new registers if the system supports the extension. 1457 Platform RAS features may additionally depend on firmware support. 1458 1459config ARM64_CNP 1460 bool "Enable support for Common Not Private (CNP) translations" 1461 default y 1462 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1463 help 1464 Common Not Private (CNP) allows translation table entries to 1465 be shared between different PEs in the same inner shareable 1466 domain, so the hardware can use this fact to optimise the 1467 caching of such entries in the TLB. 1468 1469 Selecting this option allows the CNP feature to be detected 1470 at runtime, and does not affect PEs that do not implement 1471 this feature. 1472 1473endmenu 1474 1475menu "ARMv8.3 architectural features" 1476 1477config ARM64_PTR_AUTH 1478 bool "Enable support for pointer authentication" 1479 default y 1480 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1481 # Modern compilers insert a .note.gnu.property section note for PAC 1482 # which is only understood by binutils starting with version 2.33.1. 1483 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100) 1484 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1485 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1486 help 1487 Pointer authentication (part of the ARMv8.3 Extensions) provides 1488 instructions for signing and authenticating pointers against secret 1489 keys, which can be used to mitigate Return Oriented Programming (ROP) 1490 and other attacks. 1491 1492 This option enables these instructions at EL0 (i.e. for userspace). 1493 Choosing this option will cause the kernel to initialise secret keys 1494 for each process at exec() time, with these keys being 1495 context-switched along with the process. 1496 1497 If the compiler supports the -mbranch-protection or 1498 -msign-return-address flag (e.g. GCC 7 or later), then this option 1499 will also cause the kernel itself to be compiled with return address 1500 protection. In this case, and if the target hardware is known to 1501 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1502 disabled with minimal loss of protection. 1503 1504 The feature is detected at runtime. If the feature is not present in 1505 hardware it will not be advertised to userspace/KVM guest nor will it 1506 be enabled. 1507 1508 If the feature is present on the boot CPU but not on a late CPU, then 1509 the late CPU will be parked. Also, if the boot CPU does not have 1510 address auth and the late CPU has then the late CPU will still boot 1511 but with the feature disabled. On such a system, this option should 1512 not be selected. 1513 1514 This feature works with FUNCTION_GRAPH_TRACER option only if 1515 DYNAMIC_FTRACE_WITH_REGS is enabled. 1516 1517config CC_HAS_BRANCH_PROT_PAC_RET 1518 # GCC 9 or later, clang 8 or later 1519 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1520 1521config CC_HAS_SIGN_RETURN_ADDRESS 1522 # GCC 7, 8 1523 def_bool $(cc-option,-msign-return-address=all) 1524 1525config AS_HAS_PAC 1526 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1527 1528config AS_HAS_CFI_NEGATE_RA_STATE 1529 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1530 1531endmenu 1532 1533menu "ARMv8.4 architectural features" 1534 1535config ARM64_AMU_EXTN 1536 bool "Enable support for the Activity Monitors Unit CPU extension" 1537 default y 1538 help 1539 The activity monitors extension is an optional extension introduced 1540 by the ARMv8.4 CPU architecture. This enables support for version 1 1541 of the activity monitors architecture, AMUv1. 1542 1543 To enable the use of this extension on CPUs that implement it, say Y. 1544 1545 Note that for architectural reasons, firmware _must_ implement AMU 1546 support when running on CPUs that present the activity monitors 1547 extension. The required support is present in: 1548 * Version 1.5 and later of the ARM Trusted Firmware 1549 1550 For kernels that have this configuration enabled but boot with broken 1551 firmware, you may need to say N here until the firmware is fixed. 1552 Otherwise you may experience firmware panics or lockups when 1553 accessing the counter registers. Even if you are not observing these 1554 symptoms, the values returned by the register reads might not 1555 correctly reflect reality. Most commonly, the value read will be 0, 1556 indicating that the counter is not enabled. 1557 1558config AS_HAS_ARMV8_4 1559 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1560 1561config ARM64_TLB_RANGE 1562 bool "Enable support for tlbi range feature" 1563 default y 1564 depends on AS_HAS_ARMV8_4 1565 help 1566 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1567 range of input addresses. 1568 1569 The feature introduces new assembly instructions, and they were 1570 support when binutils >= 2.30. 1571 1572endmenu 1573 1574menu "ARMv8.5 architectural features" 1575 1576config AS_HAS_ARMV8_5 1577 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1578 1579config ARM64_BTI 1580 bool "Branch Target Identification support" 1581 default y 1582 help 1583 Branch Target Identification (part of the ARMv8.5 Extensions) 1584 provides a mechanism to limit the set of locations to which computed 1585 branch instructions such as BR or BLR can jump. 1586 1587 To make use of BTI on CPUs that support it, say Y. 1588 1589 BTI is intended to provide complementary protection to other control 1590 flow integrity protection mechanisms, such as the Pointer 1591 authentication mechanism provided as part of the ARMv8.3 Extensions. 1592 For this reason, it does not make sense to enable this option without 1593 also enabling support for pointer authentication. Thus, when 1594 enabling this option you should also select ARM64_PTR_AUTH=y. 1595 1596 Userspace binaries must also be specifically compiled to make use of 1597 this mechanism. If you say N here or the hardware does not support 1598 BTI, such binaries can still run, but you get no additional 1599 enforcement of branch destinations. 1600 1601config ARM64_BTI_KERNEL 1602 bool "Use Branch Target Identification for kernel" 1603 default y 1604 depends on ARM64_BTI 1605 depends on ARM64_PTR_AUTH 1606 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1607 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1608 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1609 depends on !(CC_IS_CLANG && GCOV_KERNEL) 1610 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1611 help 1612 Build the kernel with Branch Target Identification annotations 1613 and enable enforcement of this for kernel code. When this option 1614 is enabled and the system supports BTI all kernel code including 1615 modular code must have BTI enabled. 1616 1617config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1618 # GCC 9 or later, clang 8 or later 1619 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1620 1621config ARM64_E0PD 1622 bool "Enable support for E0PD" 1623 default y 1624 help 1625 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1626 that EL0 accesses made via TTBR1 always fault in constant time, 1627 providing similar benefits to KASLR as those provided by KPTI, but 1628 with lower overhead and without disrupting legitimate access to 1629 kernel memory such as SPE. 1630 1631 This option enables E0PD for TTBR1 where available. 1632 1633config ARCH_RANDOM 1634 bool "Enable support for random number generation" 1635 default y 1636 help 1637 Random number generation (part of the ARMv8.5 Extensions) 1638 provides a high bandwidth, cryptographically secure 1639 hardware random number generator. 1640 1641config ARM64_AS_HAS_MTE 1642 # Initial support for MTE went in binutils 2.32.0, checked with 1643 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1644 # as a late addition to the final architecture spec (LDGM/STGM) 1645 # is only supported in the newer 2.32.x and 2.33 binutils 1646 # versions, hence the extra "stgm" instruction check below. 1647 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1648 1649config ARM64_MTE 1650 bool "Memory Tagging Extension support" 1651 default y 1652 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1653 depends on AS_HAS_ARMV8_5 1654 # Required for tag checking in the uaccess routines 1655 depends on ARM64_PAN 1656 select ARCH_USES_HIGH_VMA_FLAGS 1657 help 1658 Memory Tagging (part of the ARMv8.5 Extensions) provides 1659 architectural support for run-time, always-on detection of 1660 various classes of memory error to aid with software debugging 1661 to eliminate vulnerabilities arising from memory-unsafe 1662 languages. 1663 1664 This option enables the support for the Memory Tagging 1665 Extension at EL0 (i.e. for userspace). 1666 1667 Selecting this option allows the feature to be detected at 1668 runtime. Any secondary CPU not implementing this feature will 1669 not be allowed a late bring-up. 1670 1671 Userspace binaries that want to use this feature must 1672 explicitly opt in. The mechanism for the userspace is 1673 described in: 1674 1675 Documentation/arm64/memory-tagging-extension.rst. 1676 1677endmenu 1678 1679config ARM64_SVE 1680 bool "ARM Scalable Vector Extension support" 1681 default y 1682 depends on !KVM || ARM64_VHE 1683 help 1684 The Scalable Vector Extension (SVE) is an extension to the AArch64 1685 execution state which complements and extends the SIMD functionality 1686 of the base architecture to support much larger vectors and to enable 1687 additional vectorisation opportunities. 1688 1689 To enable use of this extension on CPUs that implement it, say Y. 1690 1691 On CPUs that support the SVE2 extensions, this option will enable 1692 those too. 1693 1694 Note that for architectural reasons, firmware _must_ implement SVE 1695 support when running on SVE capable hardware. The required support 1696 is present in: 1697 1698 * version 1.5 and later of the ARM Trusted Firmware 1699 * the AArch64 boot wrapper since commit 5e1261e08abf 1700 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1701 1702 For other firmware implementations, consult the firmware documentation 1703 or vendor. 1704 1705 If you need the kernel to boot on SVE-capable hardware with broken 1706 firmware, you may need to say N here until you get your firmware 1707 fixed. Otherwise, you may experience firmware panics or lockups when 1708 booting the kernel. If unsure and you are not observing these 1709 symptoms, you should assume that it is safe to say Y. 1710 1711 CPUs that support SVE are architecturally required to support the 1712 Virtualization Host Extensions (VHE), so the kernel makes no 1713 provision for supporting SVE alongside KVM without VHE enabled. 1714 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support 1715 KVM in the same kernel image. 1716 1717config ARM64_MODULE_PLTS 1718 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1719 depends on MODULES 1720 select HAVE_MOD_ARCH_SPECIFIC 1721 help 1722 Allocate PLTs when loading modules so that jumps and calls whose 1723 targets are too far away for their relative offsets to be encoded 1724 in the instructions themselves can be bounced via veneers in the 1725 module's PLT. This allows modules to be allocated in the generic 1726 vmalloc area after the dedicated module memory area has been 1727 exhausted. 1728 1729 When running with address space randomization (KASLR), the module 1730 region itself may be too far away for ordinary relative jumps and 1731 calls, and so in that case, module PLTs are required and cannot be 1732 disabled. 1733 1734 Specific errata workaround(s) might also force module PLTs to be 1735 enabled (ARM64_ERRATUM_843419). 1736 1737config ARM64_PSEUDO_NMI 1738 bool "Support for NMI-like interrupts" 1739 select ARM_GIC_V3 1740 help 1741 Adds support for mimicking Non-Maskable Interrupts through the use of 1742 GIC interrupt priority. This support requires version 3 or later of 1743 ARM GIC. 1744 1745 This high priority configuration for interrupts needs to be 1746 explicitly enabled by setting the kernel parameter 1747 "irqchip.gicv3_pseudo_nmi" to 1. 1748 1749 If unsure, say N 1750 1751if ARM64_PSEUDO_NMI 1752config ARM64_DEBUG_PRIORITY_MASKING 1753 bool "Debug interrupt priority masking" 1754 help 1755 This adds runtime checks to functions enabling/disabling 1756 interrupts when using priority masking. The additional checks verify 1757 the validity of ICC_PMR_EL1 when calling concerned functions. 1758 1759 If unsure, say N 1760endif 1761 1762config RELOCATABLE 1763 bool "Build a relocatable kernel image" if EXPERT 1764 select ARCH_HAS_RELR 1765 default y 1766 help 1767 This builds the kernel as a Position Independent Executable (PIE), 1768 which retains all relocation metadata required to relocate the 1769 kernel binary at runtime to a different virtual address than the 1770 address it was linked at. 1771 Since AArch64 uses the RELA relocation format, this requires a 1772 relocation pass at runtime even if the kernel is loaded at the 1773 same address it was linked at. 1774 1775config RANDOMIZE_BASE 1776 bool "Randomize the address of the kernel image" 1777 select ARM64_MODULE_PLTS if MODULES 1778 select RELOCATABLE 1779 help 1780 Randomizes the virtual address at which the kernel image is 1781 loaded, as a security feature that deters exploit attempts 1782 relying on knowledge of the location of kernel internals. 1783 1784 It is the bootloader's job to provide entropy, by passing a 1785 random u64 value in /chosen/kaslr-seed at kernel entry. 1786 1787 When booting via the UEFI stub, it will invoke the firmware's 1788 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1789 to the kernel proper. In addition, it will randomise the physical 1790 location of the kernel Image as well. 1791 1792 If unsure, say N. 1793 1794config RANDOMIZE_MODULE_REGION_FULL 1795 bool "Randomize the module region over a 4 GB range" 1796 depends on RANDOMIZE_BASE 1797 default y 1798 help 1799 Randomizes the location of the module region inside a 4 GB window 1800 covering the core kernel. This way, it is less likely for modules 1801 to leak information about the location of core kernel data structures 1802 but it does imply that function calls between modules and the core 1803 kernel will need to be resolved via veneers in the module PLT. 1804 1805 When this option is not set, the module region will be randomized over 1806 a limited range that contains the [_stext, _etext] interval of the 1807 core kernel, so branch relocations are always in range. 1808 1809config CC_HAVE_STACKPROTECTOR_SYSREG 1810 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 1811 1812config STACKPROTECTOR_PER_TASK 1813 def_bool y 1814 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 1815 1816endmenu 1817 1818menu "Boot options" 1819 1820config ARM64_ACPI_PARKING_PROTOCOL 1821 bool "Enable support for the ARM64 ACPI parking protocol" 1822 depends on ACPI 1823 help 1824 Enable support for the ARM64 ACPI parking protocol. If disabled 1825 the kernel will not allow booting through the ARM64 ACPI parking 1826 protocol even if the corresponding data is present in the ACPI 1827 MADT table. 1828 1829config CMDLINE 1830 string "Default kernel command string" 1831 default "" 1832 help 1833 Provide a set of default command-line options at build time by 1834 entering them here. As a minimum, you should specify the the 1835 root device (e.g. root=/dev/nfs). 1836 1837choice 1838 prompt "Kernel command line type" if CMDLINE != "" 1839 default CMDLINE_FROM_BOOTLOADER 1840 help 1841 Choose how the kernel will handle the provided default kernel 1842 command line string. 1843 1844config CMDLINE_FROM_BOOTLOADER 1845 bool "Use bootloader kernel arguments if available" 1846 help 1847 Uses the command-line options passed by the boot loader. If 1848 the boot loader doesn't provide any, the default kernel command 1849 string provided in CMDLINE will be used. 1850 1851config CMDLINE_EXTEND 1852 bool "Extend bootloader kernel arguments" 1853 help 1854 The command-line arguments provided by the boot loader will be 1855 appended to the default kernel command string. 1856 1857config CMDLINE_FORCE 1858 bool "Always use the default kernel command string" 1859 help 1860 Always use the default kernel command string, even if the boot 1861 loader passes other arguments to the kernel. 1862 This is useful if you cannot or don't want to change the 1863 command-line options your boot loader passes to the kernel. 1864 1865endchoice 1866 1867config EFI_STUB 1868 bool 1869 1870config EFI 1871 bool "UEFI runtime support" 1872 depends on OF && !CPU_BIG_ENDIAN 1873 depends on KERNEL_MODE_NEON 1874 select ARCH_SUPPORTS_ACPI 1875 select LIBFDT 1876 select UCS2_STRING 1877 select EFI_PARAMS_FROM_FDT 1878 select EFI_RUNTIME_WRAPPERS 1879 select EFI_STUB 1880 select EFI_GENERIC_STUB 1881 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 1882 default y 1883 help 1884 This option provides support for runtime services provided 1885 by UEFI firmware (such as non-volatile variables, realtime 1886 clock, and platform reset). A UEFI stub is also provided to 1887 allow the kernel to be booted as an EFI application. This 1888 is only useful on systems that have UEFI firmware. 1889 1890config DMI 1891 bool "Enable support for SMBIOS (DMI) tables" 1892 depends on EFI 1893 default y 1894 help 1895 This enables SMBIOS/DMI feature for systems. 1896 1897 This option is only useful on systems that have UEFI firmware. 1898 However, even with this option, the resultant kernel should 1899 continue to boot on existing non-UEFI platforms. 1900 1901endmenu 1902 1903config SYSVIPC_COMPAT 1904 def_bool y 1905 depends on COMPAT && SYSVIPC 1906 1907config ARCH_ENABLE_HUGEPAGE_MIGRATION 1908 def_bool y 1909 depends on HUGETLB_PAGE && MIGRATION 1910 1911config ARCH_ENABLE_THP_MIGRATION 1912 def_bool y 1913 depends on TRANSPARENT_HUGEPAGE 1914 1915menu "Power management options" 1916 1917source "kernel/power/Kconfig" 1918 1919config ARCH_HIBERNATION_POSSIBLE 1920 def_bool y 1921 depends on CPU_PM 1922 1923config ARCH_HIBERNATION_HEADER 1924 def_bool y 1925 depends on HIBERNATION 1926 1927config ARCH_SUSPEND_POSSIBLE 1928 def_bool y 1929 1930endmenu 1931 1932menu "CPU Power Management" 1933 1934source "drivers/cpuidle/Kconfig" 1935 1936source "drivers/cpufreq/Kconfig" 1937 1938endmenu 1939 1940source "drivers/firmware/Kconfig" 1941 1942source "drivers/acpi/Kconfig" 1943 1944source "arch/arm64/kvm/Kconfig" 1945 1946if CRYPTO 1947source "arch/arm64/crypto/Kconfig" 1948endif 1949