xref: /openbmc/linux/arch/arm64/Kconfig (revision 6197e5b7)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_CCA_REQUIRED if ACPI
5	select ACPI_GENERIC_GSI if ACPI
6	select ACPI_GTDT if ACPI
7	select ACPI_IORT if ACPI
8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9	select ACPI_MCFG if (ACPI && PCI)
10	select ACPI_SPCR_TABLE if ACPI
11	select ACPI_PPTT if ACPI
12	select ARCH_HAS_DEBUG_WX
13	select ARCH_BINFMT_ELF_STATE
14	select ARCH_HAS_DEBUG_VIRTUAL
15	select ARCH_HAS_DEBUG_VM_PGTABLE
16	select ARCH_HAS_DMA_PREP_COHERENT
17	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18	select ARCH_HAS_FAST_MULTIPLIER
19	select ARCH_HAS_FORTIFY_SOURCE
20	select ARCH_HAS_GCOV_PROFILE_ALL
21	select ARCH_HAS_GIGANTIC_PAGE
22	select ARCH_HAS_KCOV
23	select ARCH_HAS_KEEPINITRD
24	select ARCH_HAS_MEMBARRIER_SYNC_CORE
25	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26	select ARCH_HAS_PTE_DEVMAP
27	select ARCH_HAS_PTE_SPECIAL
28	select ARCH_HAS_SETUP_DMA_OPS
29	select ARCH_HAS_SET_DIRECT_MAP
30	select ARCH_HAS_SET_MEMORY
31	select ARCH_STACKWALK
32	select ARCH_HAS_STRICT_KERNEL_RWX
33	select ARCH_HAS_STRICT_MODULE_RWX
34	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35	select ARCH_HAS_SYNC_DMA_FOR_CPU
36	select ARCH_HAS_SYSCALL_WRAPPER
37	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39	select ARCH_HAVE_ELF_PROT
40	select ARCH_HAVE_NMI_SAFE_CMPXCHG
41	select ARCH_INLINE_READ_LOCK if !PREEMPTION
42	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67	select ARCH_KEEP_MEMBLOCK
68	select ARCH_USE_CMPXCHG_LOCKREF
69	select ARCH_USE_GNU_PROPERTY
70	select ARCH_USE_QUEUED_RWLOCKS
71	select ARCH_USE_QUEUED_SPINLOCKS
72	select ARCH_USE_SYM_ANNOTATIONS
73	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74	select ARCH_SUPPORTS_MEMORY_FAILURE
75	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76	select ARCH_SUPPORTS_ATOMIC_RMW
77	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78	select ARCH_SUPPORTS_NUMA_BALANCING
79	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80	select ARCH_WANT_DEFAULT_BPF_JIT
81	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82	select ARCH_WANT_FRAME_POINTERS
83	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84	select ARCH_WANT_LD_ORPHAN_WARN
85	select ARCH_HAS_UBSAN_SANITIZE_ALL
86	select ARM_AMBA
87	select ARM_ARCH_TIMER
88	select ARM_GIC
89	select AUDIT_ARCH_COMPAT_GENERIC
90	select ARM_GIC_V2M if PCI
91	select ARM_GIC_V3
92	select ARM_GIC_V3_ITS if PCI
93	select ARM_PSCI_FW
94	select BUILDTIME_TABLE_SORT
95	select CLONE_BACKWARDS
96	select COMMON_CLK
97	select CPU_PM if (SUSPEND || CPU_IDLE)
98	select CRC32
99	select DCACHE_WORD_ACCESS
100	select DMA_DIRECT_REMAP
101	select EDAC_SUPPORT
102	select FRAME_POINTER
103	select GENERIC_ALLOCATOR
104	select GENERIC_ARCH_TOPOLOGY
105	select GENERIC_CLOCKEVENTS_BROADCAST
106	select GENERIC_CPU_AUTOPROBE
107	select GENERIC_CPU_VULNERABILITIES
108	select GENERIC_EARLY_IOREMAP
109	select GENERIC_IDLE_POLL_SETUP
110	select GENERIC_IRQ_IPI
111	select GENERIC_IRQ_MULTI_HANDLER
112	select GENERIC_IRQ_PROBE
113	select GENERIC_IRQ_SHOW
114	select GENERIC_IRQ_SHOW_LEVEL
115	select GENERIC_LIB_DEVMEM_IS_ALLOWED
116	select GENERIC_PCI_IOMAP
117	select GENERIC_PTDUMP
118	select GENERIC_SCHED_CLOCK
119	select GENERIC_SMP_IDLE_THREAD
120	select GENERIC_STRNCPY_FROM_USER
121	select GENERIC_STRNLEN_USER
122	select GENERIC_TIME_VSYSCALL
123	select GENERIC_GETTIMEOFDAY
124	select GENERIC_VDSO_TIME_NS
125	select HANDLE_DOMAIN_IRQ
126	select HARDIRQS_SW_RESEND
127	select HAVE_MOVE_PMD
128	select HAVE_MOVE_PUD
129	select HAVE_PCI
130	select HAVE_ACPI_APEI if (ACPI && EFI)
131	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
132	select HAVE_ARCH_AUDITSYSCALL
133	select HAVE_ARCH_BITREVERSE
134	select HAVE_ARCH_COMPILER_H
135	select HAVE_ARCH_HUGE_VMAP
136	select HAVE_ARCH_JUMP_LABEL
137	select HAVE_ARCH_JUMP_LABEL_RELATIVE
138	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
139	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
140	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
141	select HAVE_ARCH_KGDB
142	select HAVE_ARCH_MMAP_RND_BITS
143	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
144	select HAVE_ARCH_PFN_VALID
145	select HAVE_ARCH_PREL32_RELOCATIONS
146	select HAVE_ARCH_SECCOMP_FILTER
147	select HAVE_ARCH_STACKLEAK
148	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
149	select HAVE_ARCH_TRACEHOOK
150	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
151	select HAVE_ARCH_VMAP_STACK
152	select HAVE_ARM_SMCCC
153	select HAVE_ASM_MODVERSIONS
154	select HAVE_EBPF_JIT
155	select HAVE_C_RECORDMCOUNT
156	select HAVE_CMPXCHG_DOUBLE
157	select HAVE_CMPXCHG_LOCAL
158	select HAVE_CONTEXT_TRACKING
159	select HAVE_DEBUG_BUGVERBOSE
160	select HAVE_DEBUG_KMEMLEAK
161	select HAVE_DMA_CONTIGUOUS
162	select HAVE_DYNAMIC_FTRACE
163	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
164		if $(cc-option,-fpatchable-function-entry=2)
165	select HAVE_EFFICIENT_UNALIGNED_ACCESS
166	select HAVE_FAST_GUP
167	select HAVE_FTRACE_MCOUNT_RECORD
168	select HAVE_FUNCTION_TRACER
169	select HAVE_FUNCTION_ERROR_INJECTION
170	select HAVE_FUNCTION_GRAPH_TRACER
171	select HAVE_GCC_PLUGINS
172	select HAVE_HW_BREAKPOINT if PERF_EVENTS
173	select HAVE_IRQ_TIME_ACCOUNTING
174	select HAVE_NMI
175	select HAVE_PATA_PLATFORM
176	select HAVE_PERF_EVENTS
177	select HAVE_PERF_REGS
178	select HAVE_PERF_USER_STACK_DUMP
179	select HAVE_REGS_AND_STACK_ACCESS_API
180	select HAVE_FUNCTION_ARG_ACCESS_API
181	select HAVE_FUTEX_CMPXCHG if FUTEX
182	select MMU_GATHER_RCU_TABLE_FREE
183	select HAVE_RSEQ
184	select HAVE_STACKPROTECTOR
185	select HAVE_SYSCALL_TRACEPOINTS
186	select HAVE_KPROBES
187	select HAVE_KRETPROBES
188	select HAVE_GENERIC_VDSO
189	select IOMMU_DMA if IOMMU_SUPPORT
190	select IRQ_DOMAIN
191	select IRQ_FORCED_THREADING
192	select MODULES_USE_ELF_RELA
193	select NEED_DMA_MAP_STATE
194	select NEED_SG_DMA_LENGTH
195	select OF
196	select OF_EARLY_FLATTREE
197	select PCI_DOMAINS_GENERIC if PCI
198	select PCI_ECAM if (ACPI && PCI)
199	select PCI_SYSCALL if PCI
200	select POWER_RESET
201	select POWER_SUPPLY
202	select SPARSE_IRQ
203	select SWIOTLB
204	select SYSCTL_EXCEPTION_TRACE
205	select THREAD_INFO_IN_TASK
206	help
207	  ARM 64-bit (AArch64) Linux support.
208
209config 64BIT
210	def_bool y
211
212config MMU
213	def_bool y
214
215config ARM64_PAGE_SHIFT
216	int
217	default 16 if ARM64_64K_PAGES
218	default 14 if ARM64_16K_PAGES
219	default 12
220
221config ARM64_CONT_PTE_SHIFT
222	int
223	default 5 if ARM64_64K_PAGES
224	default 7 if ARM64_16K_PAGES
225	default 4
226
227config ARM64_CONT_PMD_SHIFT
228	int
229	default 5 if ARM64_64K_PAGES
230	default 5 if ARM64_16K_PAGES
231	default 4
232
233config ARCH_MMAP_RND_BITS_MIN
234       default 14 if ARM64_64K_PAGES
235       default 16 if ARM64_16K_PAGES
236       default 18
237
238# max bits determined by the following formula:
239#  VA_BITS - PAGE_SHIFT - 3
240config ARCH_MMAP_RND_BITS_MAX
241       default 19 if ARM64_VA_BITS=36
242       default 24 if ARM64_VA_BITS=39
243       default 27 if ARM64_VA_BITS=42
244       default 30 if ARM64_VA_BITS=47
245       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
246       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
247       default 33 if ARM64_VA_BITS=48
248       default 14 if ARM64_64K_PAGES
249       default 16 if ARM64_16K_PAGES
250       default 18
251
252config ARCH_MMAP_RND_COMPAT_BITS_MIN
253       default 7 if ARM64_64K_PAGES
254       default 9 if ARM64_16K_PAGES
255       default 11
256
257config ARCH_MMAP_RND_COMPAT_BITS_MAX
258       default 16
259
260config NO_IOPORT_MAP
261	def_bool y if !PCI
262
263config STACKTRACE_SUPPORT
264	def_bool y
265
266config ILLEGAL_POINTER_VALUE
267	hex
268	default 0xdead000000000000
269
270config LOCKDEP_SUPPORT
271	def_bool y
272
273config TRACE_IRQFLAGS_SUPPORT
274	def_bool y
275
276config GENERIC_BUG
277	def_bool y
278	depends on BUG
279
280config GENERIC_BUG_RELATIVE_POINTERS
281	def_bool y
282	depends on GENERIC_BUG
283
284config GENERIC_HWEIGHT
285	def_bool y
286
287config GENERIC_CSUM
288        def_bool y
289
290config GENERIC_CALIBRATE_DELAY
291	def_bool y
292
293config ZONE_DMA
294	bool "Support DMA zone" if EXPERT
295	default y
296
297config ZONE_DMA32
298	bool "Support DMA32 zone" if EXPERT
299	default y
300
301config ARCH_ENABLE_MEMORY_HOTPLUG
302	def_bool y
303
304config ARCH_ENABLE_MEMORY_HOTREMOVE
305	def_bool y
306
307config SMP
308	def_bool y
309
310config KERNEL_MODE_NEON
311	def_bool y
312
313config FIX_EARLYCON_MEM
314	def_bool y
315
316config PGTABLE_LEVELS
317	int
318	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
319	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
320	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
321	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
322	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
323	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
324
325config ARCH_SUPPORTS_UPROBES
326	def_bool y
327
328config ARCH_PROC_KCORE_TEXT
329	def_bool y
330
331config BROKEN_GAS_INST
332	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
333
334config KASAN_SHADOW_OFFSET
335	hex
336	depends on KASAN_GENERIC || KASAN_SW_TAGS
337	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
338	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
339	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
340	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
341	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
342	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
343	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
344	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
345	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
346	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
347	default 0xffffffffffffffff
348
349source "arch/arm64/Kconfig.platforms"
350
351menu "Kernel Features"
352
353menu "ARM errata workarounds via the alternatives framework"
354
355config ARM64_WORKAROUND_CLEAN_CACHE
356	bool
357
358config ARM64_ERRATUM_826319
359	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
360	default y
361	select ARM64_WORKAROUND_CLEAN_CACHE
362	help
363	  This option adds an alternative code sequence to work around ARM
364	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
365	  AXI master interface and an L2 cache.
366
367	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
368	  and is unable to accept a certain write via this interface, it will
369	  not progress on read data presented on the read data channel and the
370	  system can deadlock.
371
372	  The workaround promotes data cache clean instructions to
373	  data cache clean-and-invalidate.
374	  Please note that this does not necessarily enable the workaround,
375	  as it depends on the alternative framework, which will only patch
376	  the kernel if an affected CPU is detected.
377
378	  If unsure, say Y.
379
380config ARM64_ERRATUM_827319
381	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
382	default y
383	select ARM64_WORKAROUND_CLEAN_CACHE
384	help
385	  This option adds an alternative code sequence to work around ARM
386	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
387	  master interface and an L2 cache.
388
389	  Under certain conditions this erratum can cause a clean line eviction
390	  to occur at the same time as another transaction to the same address
391	  on the AMBA 5 CHI interface, which can cause data corruption if the
392	  interconnect reorders the two transactions.
393
394	  The workaround promotes data cache clean instructions to
395	  data cache clean-and-invalidate.
396	  Please note that this does not necessarily enable the workaround,
397	  as it depends on the alternative framework, which will only patch
398	  the kernel if an affected CPU is detected.
399
400	  If unsure, say Y.
401
402config ARM64_ERRATUM_824069
403	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
404	default y
405	select ARM64_WORKAROUND_CLEAN_CACHE
406	help
407	  This option adds an alternative code sequence to work around ARM
408	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
409	  to a coherent interconnect.
410
411	  If a Cortex-A53 processor is executing a store or prefetch for
412	  write instruction at the same time as a processor in another
413	  cluster is executing a cache maintenance operation to the same
414	  address, then this erratum might cause a clean cache line to be
415	  incorrectly marked as dirty.
416
417	  The workaround promotes data cache clean instructions to
418	  data cache clean-and-invalidate.
419	  Please note that this option does not necessarily enable the
420	  workaround, as it depends on the alternative framework, which will
421	  only patch the kernel if an affected CPU is detected.
422
423	  If unsure, say Y.
424
425config ARM64_ERRATUM_819472
426	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
427	default y
428	select ARM64_WORKAROUND_CLEAN_CACHE
429	help
430	  This option adds an alternative code sequence to work around ARM
431	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
432	  present when it is connected to a coherent interconnect.
433
434	  If the processor is executing a load and store exclusive sequence at
435	  the same time as a processor in another cluster is executing a cache
436	  maintenance operation to the same address, then this erratum might
437	  cause data corruption.
438
439	  The workaround promotes data cache clean instructions to
440	  data cache clean-and-invalidate.
441	  Please note that this does not necessarily enable the workaround,
442	  as it depends on the alternative framework, which will only patch
443	  the kernel if an affected CPU is detected.
444
445	  If unsure, say Y.
446
447config ARM64_ERRATUM_832075
448	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
449	default y
450	help
451	  This option adds an alternative code sequence to work around ARM
452	  erratum 832075 on Cortex-A57 parts up to r1p2.
453
454	  Affected Cortex-A57 parts might deadlock when exclusive load/store
455	  instructions to Write-Back memory are mixed with Device loads.
456
457	  The workaround is to promote device loads to use Load-Acquire
458	  semantics.
459	  Please note that this does not necessarily enable the workaround,
460	  as it depends on the alternative framework, which will only patch
461	  the kernel if an affected CPU is detected.
462
463	  If unsure, say Y.
464
465config ARM64_ERRATUM_834220
466	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
467	depends on KVM
468	default y
469	help
470	  This option adds an alternative code sequence to work around ARM
471	  erratum 834220 on Cortex-A57 parts up to r1p2.
472
473	  Affected Cortex-A57 parts might report a Stage 2 translation
474	  fault as the result of a Stage 1 fault for load crossing a
475	  page boundary when there is a permission or device memory
476	  alignment fault at Stage 1 and a translation fault at Stage 2.
477
478	  The workaround is to verify that the Stage 1 translation
479	  doesn't generate a fault before handling the Stage 2 fault.
480	  Please note that this does not necessarily enable the workaround,
481	  as it depends on the alternative framework, which will only patch
482	  the kernel if an affected CPU is detected.
483
484	  If unsure, say Y.
485
486config ARM64_ERRATUM_845719
487	bool "Cortex-A53: 845719: a load might read incorrect data"
488	depends on COMPAT
489	default y
490	help
491	  This option adds an alternative code sequence to work around ARM
492	  erratum 845719 on Cortex-A53 parts up to r0p4.
493
494	  When running a compat (AArch32) userspace on an affected Cortex-A53
495	  part, a load at EL0 from a virtual address that matches the bottom 32
496	  bits of the virtual address used by a recent load at (AArch64) EL1
497	  might return incorrect data.
498
499	  The workaround is to write the contextidr_el1 register on exception
500	  return to a 32-bit task.
501	  Please note that this does not necessarily enable the workaround,
502	  as it depends on the alternative framework, which will only patch
503	  the kernel if an affected CPU is detected.
504
505	  If unsure, say Y.
506
507config ARM64_ERRATUM_843419
508	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
509	default y
510	select ARM64_MODULE_PLTS if MODULES
511	help
512	  This option links the kernel with '--fix-cortex-a53-843419' and
513	  enables PLT support to replace certain ADRP instructions, which can
514	  cause subsequent memory accesses to use an incorrect address on
515	  Cortex-A53 parts up to r0p4.
516
517	  If unsure, say Y.
518
519config ARM64_ERRATUM_1024718
520	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
521	default y
522	help
523	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
524
525	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
526	  update of the hardware dirty bit when the DBM/AP bits are updated
527	  without a break-before-make. The workaround is to disable the usage
528	  of hardware DBM locally on the affected cores. CPUs not affected by
529	  this erratum will continue to use the feature.
530
531	  If unsure, say Y.
532
533config ARM64_ERRATUM_1418040
534	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
535	default y
536	depends on COMPAT
537	help
538	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
539	  errata 1188873 and 1418040.
540
541	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
542	  cause register corruption when accessing the timer registers
543	  from AArch32 userspace.
544
545	  If unsure, say Y.
546
547config ARM64_WORKAROUND_SPECULATIVE_AT
548	bool
549
550config ARM64_ERRATUM_1165522
551	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
552	default y
553	select ARM64_WORKAROUND_SPECULATIVE_AT
554	help
555	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
556
557	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
558	  corrupted TLBs by speculating an AT instruction during a guest
559	  context switch.
560
561	  If unsure, say Y.
562
563config ARM64_ERRATUM_1319367
564	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
565	default y
566	select ARM64_WORKAROUND_SPECULATIVE_AT
567	help
568	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
569	  and A72 erratum 1319367
570
571	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
572	  speculating an AT instruction during a guest context switch.
573
574	  If unsure, say Y.
575
576config ARM64_ERRATUM_1530923
577	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
578	default y
579	select ARM64_WORKAROUND_SPECULATIVE_AT
580	help
581	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
582
583	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
584	  corrupted TLBs by speculating an AT instruction during a guest
585	  context switch.
586
587	  If unsure, say Y.
588
589config ARM64_WORKAROUND_REPEAT_TLBI
590	bool
591
592config ARM64_ERRATUM_1286807
593	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
594	default y
595	select ARM64_WORKAROUND_REPEAT_TLBI
596	help
597	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
598
599	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
600	  address for a cacheable mapping of a location is being
601	  accessed by a core while another core is remapping the virtual
602	  address to a new physical page using the recommended
603	  break-before-make sequence, then under very rare circumstances
604	  TLBI+DSB completes before a read using the translation being
605	  invalidated has been observed by other observers. The
606	  workaround repeats the TLBI+DSB operation.
607
608config ARM64_ERRATUM_1463225
609	bool "Cortex-A76: Software Step might prevent interrupt recognition"
610	default y
611	help
612	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
613
614	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
615	  of a system call instruction (SVC) can prevent recognition of
616	  subsequent interrupts when software stepping is disabled in the
617	  exception handler of the system call and either kernel debugging
618	  is enabled or VHE is in use.
619
620	  Work around the erratum by triggering a dummy step exception
621	  when handling a system call from a task that is being stepped
622	  in a VHE configuration of the kernel.
623
624	  If unsure, say Y.
625
626config ARM64_ERRATUM_1542419
627	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
628	default y
629	help
630	  This option adds a workaround for ARM Neoverse-N1 erratum
631	  1542419.
632
633	  Affected Neoverse-N1 cores could execute a stale instruction when
634	  modified by another CPU. The workaround depends on a firmware
635	  counterpart.
636
637	  Workaround the issue by hiding the DIC feature from EL0. This
638	  forces user-space to perform cache maintenance.
639
640	  If unsure, say Y.
641
642config ARM64_ERRATUM_1508412
643	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
644	default y
645	help
646	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
647
648	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
649	  of a store-exclusive or read of PAR_EL1 and a load with device or
650	  non-cacheable memory attributes. The workaround depends on a firmware
651	  counterpart.
652
653	  KVM guests must also have the workaround implemented or they can
654	  deadlock the system.
655
656	  Work around the issue by inserting DMB SY barriers around PAR_EL1
657	  register reads and warning KVM users. The DMB barrier is sufficient
658	  to prevent a speculative PAR_EL1 read.
659
660	  If unsure, say Y.
661
662config CAVIUM_ERRATUM_22375
663	bool "Cavium erratum 22375, 24313"
664	default y
665	help
666	  Enable workaround for errata 22375 and 24313.
667
668	  This implements two gicv3-its errata workarounds for ThunderX. Both
669	  with a small impact affecting only ITS table allocation.
670
671	    erratum 22375: only alloc 8MB table size
672	    erratum 24313: ignore memory access type
673
674	  The fixes are in ITS initialization and basically ignore memory access
675	  type and table size provided by the TYPER and BASER registers.
676
677	  If unsure, say Y.
678
679config CAVIUM_ERRATUM_23144
680	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
681	depends on NUMA
682	default y
683	help
684	  ITS SYNC command hang for cross node io and collections/cpu mapping.
685
686	  If unsure, say Y.
687
688config CAVIUM_ERRATUM_23154
689	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
690	default y
691	help
692	  The gicv3 of ThunderX requires a modified version for
693	  reading the IAR status to ensure data synchronization
694	  (access to icc_iar1_el1 is not sync'ed before and after).
695
696	  If unsure, say Y.
697
698config CAVIUM_ERRATUM_27456
699	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
700	default y
701	help
702	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
703	  instructions may cause the icache to become corrupted if it
704	  contains data for a non-current ASID.  The fix is to
705	  invalidate the icache when changing the mm context.
706
707	  If unsure, say Y.
708
709config CAVIUM_ERRATUM_30115
710	bool "Cavium erratum 30115: Guest may disable interrupts in host"
711	default y
712	help
713	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
714	  1.2, and T83 Pass 1.0, KVM guest execution may disable
715	  interrupts in host. Trapping both GICv3 group-0 and group-1
716	  accesses sidesteps the issue.
717
718	  If unsure, say Y.
719
720config CAVIUM_TX2_ERRATUM_219
721	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
722	default y
723	help
724	  On Cavium ThunderX2, a load, store or prefetch instruction between a
725	  TTBR update and the corresponding context synchronizing operation can
726	  cause a spurious Data Abort to be delivered to any hardware thread in
727	  the CPU core.
728
729	  Work around the issue by avoiding the problematic code sequence and
730	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
731	  trap handler performs the corresponding register access, skips the
732	  instruction and ensures context synchronization by virtue of the
733	  exception return.
734
735	  If unsure, say Y.
736
737config FUJITSU_ERRATUM_010001
738	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
739	default y
740	help
741	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
742	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
743	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
744	  This fault occurs under a specific hardware condition when a
745	  load/store instruction performs an address translation using:
746	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
747	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
748	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
749	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
750
751	  The workaround is to ensure these bits are clear in TCR_ELx.
752	  The workaround only affects the Fujitsu-A64FX.
753
754	  If unsure, say Y.
755
756config HISILICON_ERRATUM_161600802
757	bool "Hip07 161600802: Erroneous redistributor VLPI base"
758	default y
759	help
760	  The HiSilicon Hip07 SoC uses the wrong redistributor base
761	  when issued ITS commands such as VMOVP and VMAPP, and requires
762	  a 128kB offset to be applied to the target address in this commands.
763
764	  If unsure, say Y.
765
766config QCOM_FALKOR_ERRATUM_1003
767	bool "Falkor E1003: Incorrect translation due to ASID change"
768	default y
769	help
770	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
771	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
772	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
773	  then only for entries in the walk cache, since the leaf translation
774	  is unchanged. Work around the erratum by invalidating the walk cache
775	  entries for the trampoline before entering the kernel proper.
776
777config QCOM_FALKOR_ERRATUM_1009
778	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
779	default y
780	select ARM64_WORKAROUND_REPEAT_TLBI
781	help
782	  On Falkor v1, the CPU may prematurely complete a DSB following a
783	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
784	  one more time to fix the issue.
785
786	  If unsure, say Y.
787
788config QCOM_QDF2400_ERRATUM_0065
789	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
790	default y
791	help
792	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
793	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
794	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
795
796	  If unsure, say Y.
797
798config QCOM_FALKOR_ERRATUM_E1041
799	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
800	default y
801	help
802	  Falkor CPU may speculatively fetch instructions from an improper
803	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
804	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
805
806	  If unsure, say Y.
807
808config SOCIONEXT_SYNQUACER_PREITS
809	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
810	default y
811	help
812	  Socionext Synquacer SoCs implement a separate h/w block to generate
813	  MSI doorbell writes with non-zero values for the device ID.
814
815	  If unsure, say Y.
816
817endmenu
818
819
820choice
821	prompt "Page size"
822	default ARM64_4K_PAGES
823	help
824	  Page size (translation granule) configuration.
825
826config ARM64_4K_PAGES
827	bool "4KB"
828	help
829	  This feature enables 4KB pages support.
830
831config ARM64_16K_PAGES
832	bool "16KB"
833	help
834	  The system will use 16KB pages support. AArch32 emulation
835	  requires applications compiled with 16K (or a multiple of 16K)
836	  aligned segments.
837
838config ARM64_64K_PAGES
839	bool "64KB"
840	help
841	  This feature enables 64KB pages support (4KB by default)
842	  allowing only two levels of page tables and faster TLB
843	  look-up. AArch32 emulation requires applications compiled
844	  with 64K aligned segments.
845
846endchoice
847
848choice
849	prompt "Virtual address space size"
850	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
851	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
852	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
853	help
854	  Allows choosing one of multiple possible virtual address
855	  space sizes. The level of translation table is determined by
856	  a combination of page size and virtual address space size.
857
858config ARM64_VA_BITS_36
859	bool "36-bit" if EXPERT
860	depends on ARM64_16K_PAGES
861
862config ARM64_VA_BITS_39
863	bool "39-bit"
864	depends on ARM64_4K_PAGES
865
866config ARM64_VA_BITS_42
867	bool "42-bit"
868	depends on ARM64_64K_PAGES
869
870config ARM64_VA_BITS_47
871	bool "47-bit"
872	depends on ARM64_16K_PAGES
873
874config ARM64_VA_BITS_48
875	bool "48-bit"
876
877config ARM64_VA_BITS_52
878	bool "52-bit"
879	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
880	help
881	  Enable 52-bit virtual addressing for userspace when explicitly
882	  requested via a hint to mmap(). The kernel will also use 52-bit
883	  virtual addresses for its own mappings (provided HW support for
884	  this feature is available, otherwise it reverts to 48-bit).
885
886	  NOTE: Enabling 52-bit virtual addressing in conjunction with
887	  ARMv8.3 Pointer Authentication will result in the PAC being
888	  reduced from 7 bits to 3 bits, which may have a significant
889	  impact on its susceptibility to brute-force attacks.
890
891	  If unsure, select 48-bit virtual addressing instead.
892
893endchoice
894
895config ARM64_FORCE_52BIT
896	bool "Force 52-bit virtual addresses for userspace"
897	depends on ARM64_VA_BITS_52 && EXPERT
898	help
899	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
900	  to maintain compatibility with older software by providing 48-bit VAs
901	  unless a hint is supplied to mmap.
902
903	  This configuration option disables the 48-bit compatibility logic, and
904	  forces all userspace addresses to be 52-bit on HW that supports it. One
905	  should only enable this configuration option for stress testing userspace
906	  memory management code. If unsure say N here.
907
908config ARM64_VA_BITS
909	int
910	default 36 if ARM64_VA_BITS_36
911	default 39 if ARM64_VA_BITS_39
912	default 42 if ARM64_VA_BITS_42
913	default 47 if ARM64_VA_BITS_47
914	default 48 if ARM64_VA_BITS_48
915	default 52 if ARM64_VA_BITS_52
916
917choice
918	prompt "Physical address space size"
919	default ARM64_PA_BITS_48
920	help
921	  Choose the maximum physical address range that the kernel will
922	  support.
923
924config ARM64_PA_BITS_48
925	bool "48-bit"
926
927config ARM64_PA_BITS_52
928	bool "52-bit (ARMv8.2)"
929	depends on ARM64_64K_PAGES
930	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
931	help
932	  Enable support for a 52-bit physical address space, introduced as
933	  part of the ARMv8.2-LPA extension.
934
935	  With this enabled, the kernel will also continue to work on CPUs that
936	  do not support ARMv8.2-LPA, but with some added memory overhead (and
937	  minor performance overhead).
938
939endchoice
940
941config ARM64_PA_BITS
942	int
943	default 48 if ARM64_PA_BITS_48
944	default 52 if ARM64_PA_BITS_52
945
946choice
947	prompt "Endianness"
948	default CPU_LITTLE_ENDIAN
949	help
950	  Select the endianness of data accesses performed by the CPU. Userspace
951	  applications will need to be compiled and linked for the endianness
952	  that is selected here.
953
954config CPU_BIG_ENDIAN
955       bool "Build big-endian kernel"
956       help
957	  Say Y if you plan on running a kernel with a big-endian userspace.
958
959config CPU_LITTLE_ENDIAN
960	bool "Build little-endian kernel"
961	help
962	  Say Y if you plan on running a kernel with a little-endian userspace.
963	  This is usually the case for distributions targeting arm64.
964
965endchoice
966
967config SCHED_MC
968	bool "Multi-core scheduler support"
969	help
970	  Multi-core scheduler support improves the CPU scheduler's decision
971	  making when dealing with multi-core CPU chips at a cost of slightly
972	  increased overhead in some places. If unsure say N here.
973
974config SCHED_SMT
975	bool "SMT scheduler support"
976	help
977	  Improves the CPU scheduler's decision making when dealing with
978	  MultiThreading at a cost of slightly increased overhead in some
979	  places. If unsure say N here.
980
981config NR_CPUS
982	int "Maximum number of CPUs (2-4096)"
983	range 2 4096
984	default "256"
985
986config HOTPLUG_CPU
987	bool "Support for hot-pluggable CPUs"
988	select GENERIC_IRQ_MIGRATION
989	help
990	  Say Y here to experiment with turning CPUs off and on.  CPUs
991	  can be controlled through /sys/devices/system/cpu.
992
993# Common NUMA Features
994config NUMA
995	bool "NUMA Memory Allocation and Scheduler Support"
996	select ACPI_NUMA if ACPI
997	select OF_NUMA
998	help
999	  Enable NUMA (Non-Uniform Memory Access) support.
1000
1001	  The kernel will try to allocate memory used by a CPU on the
1002	  local memory of the CPU and add some more
1003	  NUMA awareness to the kernel.
1004
1005config NODES_SHIFT
1006	int "Maximum NUMA Nodes (as a power of 2)"
1007	range 1 10
1008	default "4"
1009	depends on NEED_MULTIPLE_NODES
1010	help
1011	  Specify the maximum number of NUMA Nodes available on the target
1012	  system.  Increases memory reserved to accommodate various tables.
1013
1014config USE_PERCPU_NUMA_NODE_ID
1015	def_bool y
1016	depends on NUMA
1017
1018config HAVE_SETUP_PER_CPU_AREA
1019	def_bool y
1020	depends on NUMA
1021
1022config NEED_PER_CPU_EMBED_FIRST_CHUNK
1023	def_bool y
1024	depends on NUMA
1025
1026config HOLES_IN_ZONE
1027	def_bool y
1028
1029source "kernel/Kconfig.hz"
1030
1031config ARCH_SPARSEMEM_ENABLE
1032	def_bool y
1033	select SPARSEMEM_VMEMMAP_ENABLE
1034
1035config ARCH_SPARSEMEM_DEFAULT
1036	def_bool ARCH_SPARSEMEM_ENABLE
1037
1038config ARCH_SELECT_MEMORY_MODEL
1039	def_bool ARCH_SPARSEMEM_ENABLE
1040
1041config ARCH_FLATMEM_ENABLE
1042	def_bool !NUMA
1043
1044config HW_PERF_EVENTS
1045	def_bool y
1046	depends on ARM_PMU
1047
1048config SYS_SUPPORTS_HUGETLBFS
1049	def_bool y
1050
1051config ARCH_WANT_HUGE_PMD_SHARE
1052
1053config ARCH_HAS_CACHE_LINE_SIZE
1054	def_bool y
1055
1056config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1057	def_bool y if PGTABLE_LEVELS > 2
1058
1059# Supported by clang >= 7.0
1060config CC_HAVE_SHADOW_CALL_STACK
1061	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1062
1063config PARAVIRT
1064	bool "Enable paravirtualization code"
1065	help
1066	  This changes the kernel so it can modify itself when it is run
1067	  under a hypervisor, potentially improving performance significantly
1068	  over full virtualization.
1069
1070config PARAVIRT_TIME_ACCOUNTING
1071	bool "Paravirtual steal time accounting"
1072	select PARAVIRT
1073	help
1074	  Select this option to enable fine granularity task steal time
1075	  accounting. Time spent executing other tasks in parallel with
1076	  the current vCPU is discounted from the vCPU power. To account for
1077	  that, there can be a small performance impact.
1078
1079	  If in doubt, say N here.
1080
1081config KEXEC
1082	depends on PM_SLEEP_SMP
1083	select KEXEC_CORE
1084	bool "kexec system call"
1085	help
1086	  kexec is a system call that implements the ability to shutdown your
1087	  current kernel, and to start another kernel.  It is like a reboot
1088	  but it is independent of the system firmware.   And like a reboot
1089	  you can start any kernel with it, not just Linux.
1090
1091config KEXEC_FILE
1092	bool "kexec file based system call"
1093	select KEXEC_CORE
1094	help
1095	  This is new version of kexec system call. This system call is
1096	  file based and takes file descriptors as system call argument
1097	  for kernel and initramfs as opposed to list of segments as
1098	  accepted by previous system call.
1099
1100config KEXEC_SIG
1101	bool "Verify kernel signature during kexec_file_load() syscall"
1102	depends on KEXEC_FILE
1103	help
1104	  Select this option to verify a signature with loaded kernel
1105	  image. If configured, any attempt of loading a image without
1106	  valid signature will fail.
1107
1108	  In addition to that option, you need to enable signature
1109	  verification for the corresponding kernel image type being
1110	  loaded in order for this to work.
1111
1112config KEXEC_IMAGE_VERIFY_SIG
1113	bool "Enable Image signature verification support"
1114	default y
1115	depends on KEXEC_SIG
1116	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1117	help
1118	  Enable Image signature verification support.
1119
1120comment "Support for PE file signature verification disabled"
1121	depends on KEXEC_SIG
1122	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1123
1124config CRASH_DUMP
1125	bool "Build kdump crash kernel"
1126	help
1127	  Generate crash dump after being started by kexec. This should
1128	  be normally only set in special crash dump kernels which are
1129	  loaded in the main kernel with kexec-tools into a specially
1130	  reserved region and then later executed after a crash by
1131	  kdump/kexec.
1132
1133	  For more details see Documentation/admin-guide/kdump/kdump.rst
1134
1135config XEN_DOM0
1136	def_bool y
1137	depends on XEN
1138
1139config XEN
1140	bool "Xen guest support on ARM64"
1141	depends on ARM64 && OF
1142	select SWIOTLB_XEN
1143	select PARAVIRT
1144	help
1145	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1146
1147config FORCE_MAX_ZONEORDER
1148	int
1149	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1150	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1151	default "11"
1152	help
1153	  The kernel memory allocator divides physically contiguous memory
1154	  blocks into "zones", where each zone is a power of two number of
1155	  pages.  This option selects the largest power of two that the kernel
1156	  keeps in the memory allocator.  If you need to allocate very large
1157	  blocks of physically contiguous memory, then you may need to
1158	  increase this value.
1159
1160	  This config option is actually maximum order plus one. For example,
1161	  a value of 11 means that the largest free memory block is 2^10 pages.
1162
1163	  We make sure that we can allocate upto a HugePage size for each configuration.
1164	  Hence we have :
1165		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1166
1167	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1168	  4M allocations matching the default size used by generic code.
1169
1170config UNMAP_KERNEL_AT_EL0
1171	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1172	default y
1173	help
1174	  Speculation attacks against some high-performance processors can
1175	  be used to bypass MMU permission checks and leak kernel data to
1176	  userspace. This can be defended against by unmapping the kernel
1177	  when running in userspace, mapping it back in on exception entry
1178	  via a trampoline page in the vector table.
1179
1180	  If unsure, say Y.
1181
1182config RODATA_FULL_DEFAULT_ENABLED
1183	bool "Apply r/o permissions of VM areas also to their linear aliases"
1184	default y
1185	help
1186	  Apply read-only attributes of VM areas to the linear alias of
1187	  the backing pages as well. This prevents code or read-only data
1188	  from being modified (inadvertently or intentionally) via another
1189	  mapping of the same memory page. This additional enhancement can
1190	  be turned off at runtime by passing rodata=[off|on] (and turned on
1191	  with rodata=full if this option is set to 'n')
1192
1193	  This requires the linear region to be mapped down to pages,
1194	  which may adversely affect performance in some cases.
1195
1196config ARM64_SW_TTBR0_PAN
1197	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1198	help
1199	  Enabling this option prevents the kernel from accessing
1200	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1201	  zeroed area and reserved ASID. The user access routines
1202	  restore the valid TTBR0_EL1 temporarily.
1203
1204config ARM64_TAGGED_ADDR_ABI
1205	bool "Enable the tagged user addresses syscall ABI"
1206	default y
1207	help
1208	  When this option is enabled, user applications can opt in to a
1209	  relaxed ABI via prctl() allowing tagged addresses to be passed
1210	  to system calls as pointer arguments. For details, see
1211	  Documentation/arm64/tagged-address-abi.rst.
1212
1213menuconfig COMPAT
1214	bool "Kernel support for 32-bit EL0"
1215	depends on ARM64_4K_PAGES || EXPERT
1216	select HAVE_UID16
1217	select OLD_SIGSUSPEND3
1218	select COMPAT_OLD_SIGACTION
1219	help
1220	  This option enables support for a 32-bit EL0 running under a 64-bit
1221	  kernel at EL1. AArch32-specific components such as system calls,
1222	  the user helper functions, VFP support and the ptrace interface are
1223	  handled appropriately by the kernel.
1224
1225	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1226	  that you will only be able to execute AArch32 binaries that were compiled
1227	  with page size aligned segments.
1228
1229	  If you want to execute 32-bit userspace applications, say Y.
1230
1231if COMPAT
1232
1233config KUSER_HELPERS
1234	bool "Enable kuser helpers page for 32-bit applications"
1235	default y
1236	help
1237	  Warning: disabling this option may break 32-bit user programs.
1238
1239	  Provide kuser helpers to compat tasks. The kernel provides
1240	  helper code to userspace in read only form at a fixed location
1241	  to allow userspace to be independent of the CPU type fitted to
1242	  the system. This permits binaries to be run on ARMv4 through
1243	  to ARMv8 without modification.
1244
1245	  See Documentation/arm/kernel_user_helpers.rst for details.
1246
1247	  However, the fixed address nature of these helpers can be used
1248	  by ROP (return orientated programming) authors when creating
1249	  exploits.
1250
1251	  If all of the binaries and libraries which run on your platform
1252	  are built specifically for your platform, and make no use of
1253	  these helpers, then you can turn this option off to hinder
1254	  such exploits. However, in that case, if a binary or library
1255	  relying on those helpers is run, it will not function correctly.
1256
1257	  Say N here only if you are absolutely certain that you do not
1258	  need these helpers; otherwise, the safe option is to say Y.
1259
1260config COMPAT_VDSO
1261	bool "Enable vDSO for 32-bit applications"
1262	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1263	select GENERIC_COMPAT_VDSO
1264	default y
1265	help
1266	  Place in the process address space of 32-bit applications an
1267	  ELF shared object providing fast implementations of gettimeofday
1268	  and clock_gettime.
1269
1270	  You must have a 32-bit build of glibc 2.22 or later for programs
1271	  to seamlessly take advantage of this.
1272
1273config THUMB2_COMPAT_VDSO
1274	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1275	depends on COMPAT_VDSO
1276	default y
1277	help
1278	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1279	  otherwise with '-marm'.
1280
1281menuconfig ARMV8_DEPRECATED
1282	bool "Emulate deprecated/obsolete ARMv8 instructions"
1283	depends on SYSCTL
1284	help
1285	  Legacy software support may require certain instructions
1286	  that have been deprecated or obsoleted in the architecture.
1287
1288	  Enable this config to enable selective emulation of these
1289	  features.
1290
1291	  If unsure, say Y
1292
1293if ARMV8_DEPRECATED
1294
1295config SWP_EMULATION
1296	bool "Emulate SWP/SWPB instructions"
1297	help
1298	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1299	  they are always undefined. Say Y here to enable software
1300	  emulation of these instructions for userspace using LDXR/STXR.
1301	  This feature can be controlled at runtime with the abi.swp
1302	  sysctl which is disabled by default.
1303
1304	  In some older versions of glibc [<=2.8] SWP is used during futex
1305	  trylock() operations with the assumption that the code will not
1306	  be preempted. This invalid assumption may be more likely to fail
1307	  with SWP emulation enabled, leading to deadlock of the user
1308	  application.
1309
1310	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1311	  on an external transaction monitoring block called a global
1312	  monitor to maintain update atomicity. If your system does not
1313	  implement a global monitor, this option can cause programs that
1314	  perform SWP operations to uncached memory to deadlock.
1315
1316	  If unsure, say Y
1317
1318config CP15_BARRIER_EMULATION
1319	bool "Emulate CP15 Barrier instructions"
1320	help
1321	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1322	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1323	  strongly recommended to use the ISB, DSB, and DMB
1324	  instructions instead.
1325
1326	  Say Y here to enable software emulation of these
1327	  instructions for AArch32 userspace code. When this option is
1328	  enabled, CP15 barrier usage is traced which can help
1329	  identify software that needs updating. This feature can be
1330	  controlled at runtime with the abi.cp15_barrier sysctl.
1331
1332	  If unsure, say Y
1333
1334config SETEND_EMULATION
1335	bool "Emulate SETEND instruction"
1336	help
1337	  The SETEND instruction alters the data-endianness of the
1338	  AArch32 EL0, and is deprecated in ARMv8.
1339
1340	  Say Y here to enable software emulation of the instruction
1341	  for AArch32 userspace code. This feature can be controlled
1342	  at runtime with the abi.setend sysctl.
1343
1344	  Note: All the cpus on the system must have mixed endian support at EL0
1345	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1346	  endian - is hotplugged in after this feature has been enabled, there could
1347	  be unexpected results in the applications.
1348
1349	  If unsure, say Y
1350endif
1351
1352endif
1353
1354menu "ARMv8.1 architectural features"
1355
1356config ARM64_HW_AFDBM
1357	bool "Support for hardware updates of the Access and Dirty page flags"
1358	default y
1359	help
1360	  The ARMv8.1 architecture extensions introduce support for
1361	  hardware updates of the access and dirty information in page
1362	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1363	  capable processors, accesses to pages with PTE_AF cleared will
1364	  set this bit instead of raising an access flag fault.
1365	  Similarly, writes to read-only pages with the DBM bit set will
1366	  clear the read-only bit (AP[2]) instead of raising a
1367	  permission fault.
1368
1369	  Kernels built with this configuration option enabled continue
1370	  to work on pre-ARMv8.1 hardware and the performance impact is
1371	  minimal. If unsure, say Y.
1372
1373config ARM64_PAN
1374	bool "Enable support for Privileged Access Never (PAN)"
1375	default y
1376	help
1377	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1378	 prevents the kernel or hypervisor from accessing user-space (EL0)
1379	 memory directly.
1380
1381	 Choosing this option will cause any unprotected (not using
1382	 copy_to_user et al) memory access to fail with a permission fault.
1383
1384	 The feature is detected at runtime, and will remain as a 'nop'
1385	 instruction if the cpu does not implement the feature.
1386
1387config AS_HAS_LDAPR
1388	def_bool $(as-instr,.arch_extension rcpc)
1389
1390config ARM64_LSE_ATOMICS
1391	bool
1392	default ARM64_USE_LSE_ATOMICS
1393	depends on $(as-instr,.arch_extension lse)
1394
1395config ARM64_USE_LSE_ATOMICS
1396	bool "Atomic instructions"
1397	depends on JUMP_LABEL
1398	default y
1399	help
1400	  As part of the Large System Extensions, ARMv8.1 introduces new
1401	  atomic instructions that are designed specifically to scale in
1402	  very large systems.
1403
1404	  Say Y here to make use of these instructions for the in-kernel
1405	  atomic routines. This incurs a small overhead on CPUs that do
1406	  not support these instructions and requires the kernel to be
1407	  built with binutils >= 2.25 in order for the new instructions
1408	  to be used.
1409
1410config ARM64_VHE
1411	bool "Enable support for Virtualization Host Extensions (VHE)"
1412	default y
1413	help
1414	  Virtualization Host Extensions (VHE) allow the kernel to run
1415	  directly at EL2 (instead of EL1) on processors that support
1416	  it. This leads to better performance for KVM, as they reduce
1417	  the cost of the world switch.
1418
1419	  Selecting this option allows the VHE feature to be detected
1420	  at runtime, and does not affect processors that do not
1421	  implement this feature.
1422
1423endmenu
1424
1425menu "ARMv8.2 architectural features"
1426
1427config ARM64_PMEM
1428	bool "Enable support for persistent memory"
1429	select ARCH_HAS_PMEM_API
1430	select ARCH_HAS_UACCESS_FLUSHCACHE
1431	help
1432	  Say Y to enable support for the persistent memory API based on the
1433	  ARMv8.2 DCPoP feature.
1434
1435	  The feature is detected at runtime, and the kernel will use DC CVAC
1436	  operations if DC CVAP is not supported (following the behaviour of
1437	  DC CVAP itself if the system does not define a point of persistence).
1438
1439config ARM64_RAS_EXTN
1440	bool "Enable support for RAS CPU Extensions"
1441	default y
1442	help
1443	  CPUs that support the Reliability, Availability and Serviceability
1444	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1445	  errors, classify them and report them to software.
1446
1447	  On CPUs with these extensions system software can use additional
1448	  barriers to determine if faults are pending and read the
1449	  classification from a new set of registers.
1450
1451	  Selecting this feature will allow the kernel to use these barriers
1452	  and access the new registers if the system supports the extension.
1453	  Platform RAS features may additionally depend on firmware support.
1454
1455config ARM64_CNP
1456	bool "Enable support for Common Not Private (CNP) translations"
1457	default y
1458	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1459	help
1460	  Common Not Private (CNP) allows translation table entries to
1461	  be shared between different PEs in the same inner shareable
1462	  domain, so the hardware can use this fact to optimise the
1463	  caching of such entries in the TLB.
1464
1465	  Selecting this option allows the CNP feature to be detected
1466	  at runtime, and does not affect PEs that do not implement
1467	  this feature.
1468
1469endmenu
1470
1471menu "ARMv8.3 architectural features"
1472
1473config ARM64_PTR_AUTH
1474	bool "Enable support for pointer authentication"
1475	default y
1476	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1477	# Modern compilers insert a .note.gnu.property section note for PAC
1478	# which is only understood by binutils starting with version 2.33.1.
1479	depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1480	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1481	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1482	help
1483	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1484	  instructions for signing and authenticating pointers against secret
1485	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1486	  and other attacks.
1487
1488	  This option enables these instructions at EL0 (i.e. for userspace).
1489	  Choosing this option will cause the kernel to initialise secret keys
1490	  for each process at exec() time, with these keys being
1491	  context-switched along with the process.
1492
1493	  If the compiler supports the -mbranch-protection or
1494	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1495	  will also cause the kernel itself to be compiled with return address
1496	  protection. In this case, and if the target hardware is known to
1497	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1498	  disabled with minimal loss of protection.
1499
1500	  The feature is detected at runtime. If the feature is not present in
1501	  hardware it will not be advertised to userspace/KVM guest nor will it
1502	  be enabled.
1503
1504	  If the feature is present on the boot CPU but not on a late CPU, then
1505	  the late CPU will be parked. Also, if the boot CPU does not have
1506	  address auth and the late CPU has then the late CPU will still boot
1507	  but with the feature disabled. On such a system, this option should
1508	  not be selected.
1509
1510	  This feature works with FUNCTION_GRAPH_TRACER option only if
1511	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1512
1513config CC_HAS_BRANCH_PROT_PAC_RET
1514	# GCC 9 or later, clang 8 or later
1515	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1516
1517config CC_HAS_SIGN_RETURN_ADDRESS
1518	# GCC 7, 8
1519	def_bool $(cc-option,-msign-return-address=all)
1520
1521config AS_HAS_PAC
1522	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1523
1524config AS_HAS_CFI_NEGATE_RA_STATE
1525	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1526
1527endmenu
1528
1529menu "ARMv8.4 architectural features"
1530
1531config ARM64_AMU_EXTN
1532	bool "Enable support for the Activity Monitors Unit CPU extension"
1533	default y
1534	help
1535	  The activity monitors extension is an optional extension introduced
1536	  by the ARMv8.4 CPU architecture. This enables support for version 1
1537	  of the activity monitors architecture, AMUv1.
1538
1539	  To enable the use of this extension on CPUs that implement it, say Y.
1540
1541	  Note that for architectural reasons, firmware _must_ implement AMU
1542	  support when running on CPUs that present the activity monitors
1543	  extension. The required support is present in:
1544	    * Version 1.5 and later of the ARM Trusted Firmware
1545
1546	  For kernels that have this configuration enabled but boot with broken
1547	  firmware, you may need to say N here until the firmware is fixed.
1548	  Otherwise you may experience firmware panics or lockups when
1549	  accessing the counter registers. Even if you are not observing these
1550	  symptoms, the values returned by the register reads might not
1551	  correctly reflect reality. Most commonly, the value read will be 0,
1552	  indicating that the counter is not enabled.
1553
1554config AS_HAS_ARMV8_4
1555	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1556
1557config ARM64_TLB_RANGE
1558	bool "Enable support for tlbi range feature"
1559	default y
1560	depends on AS_HAS_ARMV8_4
1561	help
1562	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1563	  range of input addresses.
1564
1565	  The feature introduces new assembly instructions, and they were
1566	  support when binutils >= 2.30.
1567
1568endmenu
1569
1570menu "ARMv8.5 architectural features"
1571
1572config AS_HAS_ARMV8_5
1573	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1574
1575config ARM64_BTI
1576	bool "Branch Target Identification support"
1577	default y
1578	help
1579	  Branch Target Identification (part of the ARMv8.5 Extensions)
1580	  provides a mechanism to limit the set of locations to which computed
1581	  branch instructions such as BR or BLR can jump.
1582
1583	  To make use of BTI on CPUs that support it, say Y.
1584
1585	  BTI is intended to provide complementary protection to other control
1586	  flow integrity protection mechanisms, such as the Pointer
1587	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1588	  For this reason, it does not make sense to enable this option without
1589	  also enabling support for pointer authentication.  Thus, when
1590	  enabling this option you should also select ARM64_PTR_AUTH=y.
1591
1592	  Userspace binaries must also be specifically compiled to make use of
1593	  this mechanism.  If you say N here or the hardware does not support
1594	  BTI, such binaries can still run, but you get no additional
1595	  enforcement of branch destinations.
1596
1597config ARM64_BTI_KERNEL
1598	bool "Use Branch Target Identification for kernel"
1599	default y
1600	depends on ARM64_BTI
1601	depends on ARM64_PTR_AUTH
1602	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1603	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1604	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1605	depends on !(CC_IS_CLANG && GCOV_KERNEL)
1606	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1607	help
1608	  Build the kernel with Branch Target Identification annotations
1609	  and enable enforcement of this for kernel code. When this option
1610	  is enabled and the system supports BTI all kernel code including
1611	  modular code must have BTI enabled.
1612
1613config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1614	# GCC 9 or later, clang 8 or later
1615	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1616
1617config ARM64_E0PD
1618	bool "Enable support for E0PD"
1619	default y
1620	help
1621	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1622	  that EL0 accesses made via TTBR1 always fault in constant time,
1623	  providing similar benefits to KASLR as those provided by KPTI, but
1624	  with lower overhead and without disrupting legitimate access to
1625	  kernel memory such as SPE.
1626
1627	  This option enables E0PD for TTBR1 where available.
1628
1629config ARCH_RANDOM
1630	bool "Enable support for random number generation"
1631	default y
1632	help
1633	  Random number generation (part of the ARMv8.5 Extensions)
1634	  provides a high bandwidth, cryptographically secure
1635	  hardware random number generator.
1636
1637config ARM64_AS_HAS_MTE
1638	# Initial support for MTE went in binutils 2.32.0, checked with
1639	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1640	# as a late addition to the final architecture spec (LDGM/STGM)
1641	# is only supported in the newer 2.32.x and 2.33 binutils
1642	# versions, hence the extra "stgm" instruction check below.
1643	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1644
1645config ARM64_MTE
1646	bool "Memory Tagging Extension support"
1647	default y
1648	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1649	depends on AS_HAS_ARMV8_5
1650	# Required for tag checking in the uaccess routines
1651	depends on ARM64_PAN
1652	select ARCH_USES_HIGH_VMA_FLAGS
1653	help
1654	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1655	  architectural support for run-time, always-on detection of
1656	  various classes of memory error to aid with software debugging
1657	  to eliminate vulnerabilities arising from memory-unsafe
1658	  languages.
1659
1660	  This option enables the support for the Memory Tagging
1661	  Extension at EL0 (i.e. for userspace).
1662
1663	  Selecting this option allows the feature to be detected at
1664	  runtime. Any secondary CPU not implementing this feature will
1665	  not be allowed a late bring-up.
1666
1667	  Userspace binaries that want to use this feature must
1668	  explicitly opt in. The mechanism for the userspace is
1669	  described in:
1670
1671	  Documentation/arm64/memory-tagging-extension.rst.
1672
1673endmenu
1674
1675config ARM64_SVE
1676	bool "ARM Scalable Vector Extension support"
1677	default y
1678	depends on !KVM || ARM64_VHE
1679	help
1680	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1681	  execution state which complements and extends the SIMD functionality
1682	  of the base architecture to support much larger vectors and to enable
1683	  additional vectorisation opportunities.
1684
1685	  To enable use of this extension on CPUs that implement it, say Y.
1686
1687	  On CPUs that support the SVE2 extensions, this option will enable
1688	  those too.
1689
1690	  Note that for architectural reasons, firmware _must_ implement SVE
1691	  support when running on SVE capable hardware.  The required support
1692	  is present in:
1693
1694	    * version 1.5 and later of the ARM Trusted Firmware
1695	    * the AArch64 boot wrapper since commit 5e1261e08abf
1696	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1697
1698	  For other firmware implementations, consult the firmware documentation
1699	  or vendor.
1700
1701	  If you need the kernel to boot on SVE-capable hardware with broken
1702	  firmware, you may need to say N here until you get your firmware
1703	  fixed.  Otherwise, you may experience firmware panics or lockups when
1704	  booting the kernel.  If unsure and you are not observing these
1705	  symptoms, you should assume that it is safe to say Y.
1706
1707	  CPUs that support SVE are architecturally required to support the
1708	  Virtualization Host Extensions (VHE), so the kernel makes no
1709	  provision for supporting SVE alongside KVM without VHE enabled.
1710	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1711	  KVM in the same kernel image.
1712
1713config ARM64_MODULE_PLTS
1714	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1715	depends on MODULES
1716	select HAVE_MOD_ARCH_SPECIFIC
1717	help
1718	  Allocate PLTs when loading modules so that jumps and calls whose
1719	  targets are too far away for their relative offsets to be encoded
1720	  in the instructions themselves can be bounced via veneers in the
1721	  module's PLT. This allows modules to be allocated in the generic
1722	  vmalloc area after the dedicated module memory area has been
1723	  exhausted.
1724
1725	  When running with address space randomization (KASLR), the module
1726	  region itself may be too far away for ordinary relative jumps and
1727	  calls, and so in that case, module PLTs are required and cannot be
1728	  disabled.
1729
1730	  Specific errata workaround(s) might also force module PLTs to be
1731	  enabled (ARM64_ERRATUM_843419).
1732
1733config ARM64_PSEUDO_NMI
1734	bool "Support for NMI-like interrupts"
1735	select ARM_GIC_V3
1736	help
1737	  Adds support for mimicking Non-Maskable Interrupts through the use of
1738	  GIC interrupt priority. This support requires version 3 or later of
1739	  ARM GIC.
1740
1741	  This high priority configuration for interrupts needs to be
1742	  explicitly enabled by setting the kernel parameter
1743	  "irqchip.gicv3_pseudo_nmi" to 1.
1744
1745	  If unsure, say N
1746
1747if ARM64_PSEUDO_NMI
1748config ARM64_DEBUG_PRIORITY_MASKING
1749	bool "Debug interrupt priority masking"
1750	help
1751	  This adds runtime checks to functions enabling/disabling
1752	  interrupts when using priority masking. The additional checks verify
1753	  the validity of ICC_PMR_EL1 when calling concerned functions.
1754
1755	  If unsure, say N
1756endif
1757
1758config RELOCATABLE
1759	bool "Build a relocatable kernel image" if EXPERT
1760	select ARCH_HAS_RELR
1761	default y
1762	help
1763	  This builds the kernel as a Position Independent Executable (PIE),
1764	  which retains all relocation metadata required to relocate the
1765	  kernel binary at runtime to a different virtual address than the
1766	  address it was linked at.
1767	  Since AArch64 uses the RELA relocation format, this requires a
1768	  relocation pass at runtime even if the kernel is loaded at the
1769	  same address it was linked at.
1770
1771config RANDOMIZE_BASE
1772	bool "Randomize the address of the kernel image"
1773	select ARM64_MODULE_PLTS if MODULES
1774	select RELOCATABLE
1775	help
1776	  Randomizes the virtual address at which the kernel image is
1777	  loaded, as a security feature that deters exploit attempts
1778	  relying on knowledge of the location of kernel internals.
1779
1780	  It is the bootloader's job to provide entropy, by passing a
1781	  random u64 value in /chosen/kaslr-seed at kernel entry.
1782
1783	  When booting via the UEFI stub, it will invoke the firmware's
1784	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1785	  to the kernel proper. In addition, it will randomise the physical
1786	  location of the kernel Image as well.
1787
1788	  If unsure, say N.
1789
1790config RANDOMIZE_MODULE_REGION_FULL
1791	bool "Randomize the module region over a 4 GB range"
1792	depends on RANDOMIZE_BASE
1793	default y
1794	help
1795	  Randomizes the location of the module region inside a 4 GB window
1796	  covering the core kernel. This way, it is less likely for modules
1797	  to leak information about the location of core kernel data structures
1798	  but it does imply that function calls between modules and the core
1799	  kernel will need to be resolved via veneers in the module PLT.
1800
1801	  When this option is not set, the module region will be randomized over
1802	  a limited range that contains the [_stext, _etext] interval of the
1803	  core kernel, so branch relocations are always in range.
1804
1805config CC_HAVE_STACKPROTECTOR_SYSREG
1806	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1807
1808config STACKPROTECTOR_PER_TASK
1809	def_bool y
1810	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1811
1812endmenu
1813
1814menu "Boot options"
1815
1816config ARM64_ACPI_PARKING_PROTOCOL
1817	bool "Enable support for the ARM64 ACPI parking protocol"
1818	depends on ACPI
1819	help
1820	  Enable support for the ARM64 ACPI parking protocol. If disabled
1821	  the kernel will not allow booting through the ARM64 ACPI parking
1822	  protocol even if the corresponding data is present in the ACPI
1823	  MADT table.
1824
1825config CMDLINE
1826	string "Default kernel command string"
1827	default ""
1828	help
1829	  Provide a set of default command-line options at build time by
1830	  entering them here. As a minimum, you should specify the the
1831	  root device (e.g. root=/dev/nfs).
1832
1833choice
1834	prompt "Kernel command line type" if CMDLINE != ""
1835	default CMDLINE_FROM_BOOTLOADER
1836	help
1837	  Choose how the kernel will handle the provided default kernel
1838	  command line string.
1839
1840config CMDLINE_FROM_BOOTLOADER
1841	bool "Use bootloader kernel arguments if available"
1842	help
1843	  Uses the command-line options passed by the boot loader. If
1844	  the boot loader doesn't provide any, the default kernel command
1845	  string provided in CMDLINE will be used.
1846
1847config CMDLINE_EXTEND
1848	bool "Extend bootloader kernel arguments"
1849	help
1850	  The command-line arguments provided by the boot loader will be
1851	  appended to the default kernel command string.
1852
1853config CMDLINE_FORCE
1854	bool "Always use the default kernel command string"
1855	help
1856	  Always use the default kernel command string, even if the boot
1857	  loader passes other arguments to the kernel.
1858	  This is useful if you cannot or don't want to change the
1859	  command-line options your boot loader passes to the kernel.
1860
1861endchoice
1862
1863config EFI_STUB
1864	bool
1865
1866config EFI
1867	bool "UEFI runtime support"
1868	depends on OF && !CPU_BIG_ENDIAN
1869	depends on KERNEL_MODE_NEON
1870	select ARCH_SUPPORTS_ACPI
1871	select LIBFDT
1872	select UCS2_STRING
1873	select EFI_PARAMS_FROM_FDT
1874	select EFI_RUNTIME_WRAPPERS
1875	select EFI_STUB
1876	select EFI_GENERIC_STUB
1877	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1878	default y
1879	help
1880	  This option provides support for runtime services provided
1881	  by UEFI firmware (such as non-volatile variables, realtime
1882          clock, and platform reset). A UEFI stub is also provided to
1883	  allow the kernel to be booted as an EFI application. This
1884	  is only useful on systems that have UEFI firmware.
1885
1886config DMI
1887	bool "Enable support for SMBIOS (DMI) tables"
1888	depends on EFI
1889	default y
1890	help
1891	  This enables SMBIOS/DMI feature for systems.
1892
1893	  This option is only useful on systems that have UEFI firmware.
1894	  However, even with this option, the resultant kernel should
1895	  continue to boot on existing non-UEFI platforms.
1896
1897endmenu
1898
1899config SYSVIPC_COMPAT
1900	def_bool y
1901	depends on COMPAT && SYSVIPC
1902
1903config ARCH_ENABLE_HUGEPAGE_MIGRATION
1904	def_bool y
1905	depends on HUGETLB_PAGE && MIGRATION
1906
1907config ARCH_ENABLE_THP_MIGRATION
1908	def_bool y
1909	depends on TRANSPARENT_HUGEPAGE
1910
1911menu "Power management options"
1912
1913source "kernel/power/Kconfig"
1914
1915config ARCH_HIBERNATION_POSSIBLE
1916	def_bool y
1917	depends on CPU_PM
1918
1919config ARCH_HIBERNATION_HEADER
1920	def_bool y
1921	depends on HIBERNATION
1922
1923config ARCH_SUSPEND_POSSIBLE
1924	def_bool y
1925
1926endmenu
1927
1928menu "CPU Power Management"
1929
1930source "drivers/cpuidle/Kconfig"
1931
1932source "drivers/cpufreq/Kconfig"
1933
1934endmenu
1935
1936source "drivers/firmware/Kconfig"
1937
1938source "drivers/acpi/Kconfig"
1939
1940source "arch/arm64/kvm/Kconfig"
1941
1942if CRYPTO
1943source "arch/arm64/crypto/Kconfig"
1944endif
1945