1config ARM64 2 def_bool y 3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 4 select ARCH_HAS_ELF_RANDOMIZE 5 select ARCH_HAS_GCOV_PROFILE_ALL 6 select ARCH_HAS_SG_CHAIN 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_USE_CMPXCHG_LOCKREF 9 select ARCH_SUPPORTS_ATOMIC_RMW 10 select ARCH_WANT_OPTIONAL_GPIOLIB 11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 12 select ARCH_WANT_FRAME_POINTERS 13 select ARM_AMBA 14 select ARM_ARCH_TIMER 15 select ARM_GIC 16 select AUDIT_ARCH_COMPAT_GENERIC 17 select ARM_GIC_V2M if PCI_MSI 18 select ARM_GIC_V3 19 select ARM_GIC_V3_ITS if PCI_MSI 20 select BUILDTIME_EXTABLE_SORT 21 select CLONE_BACKWARDS 22 select COMMON_CLK 23 select CPU_PM if (SUSPEND || CPU_IDLE) 24 select DCACHE_WORD_ACCESS 25 select GENERIC_ALLOCATOR 26 select GENERIC_CLOCKEVENTS 27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 28 select GENERIC_CPU_AUTOPROBE 29 select GENERIC_EARLY_IOREMAP 30 select GENERIC_IRQ_PROBE 31 select GENERIC_IRQ_SHOW 32 select GENERIC_PCI_IOMAP 33 select GENERIC_SCHED_CLOCK 34 select GENERIC_SMP_IDLE_THREAD 35 select GENERIC_STRNCPY_FROM_USER 36 select GENERIC_STRNLEN_USER 37 select GENERIC_TIME_VSYSCALL 38 select HANDLE_DOMAIN_IRQ 39 select HARDIRQS_SW_RESEND 40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 41 select HAVE_ARCH_AUDITSYSCALL 42 select HAVE_ARCH_BITREVERSE 43 select HAVE_ARCH_JUMP_LABEL 44 select HAVE_ARCH_KGDB 45 select HAVE_ARCH_SECCOMP_FILTER 46 select HAVE_ARCH_TRACEHOOK 47 select HAVE_BPF_JIT 48 select HAVE_C_RECORDMCOUNT 49 select HAVE_CC_STACKPROTECTOR 50 select HAVE_CMPXCHG_DOUBLE 51 select HAVE_DEBUG_BUGVERBOSE 52 select HAVE_DEBUG_KMEMLEAK 53 select HAVE_DMA_API_DEBUG 54 select HAVE_DMA_ATTRS 55 select HAVE_DMA_CONTIGUOUS 56 select HAVE_DYNAMIC_FTRACE 57 select HAVE_EFFICIENT_UNALIGNED_ACCESS 58 select HAVE_FTRACE_MCOUNT_RECORD 59 select HAVE_FUNCTION_TRACER 60 select HAVE_FUNCTION_GRAPH_TRACER 61 select HAVE_GENERIC_DMA_COHERENT 62 select HAVE_HW_BREAKPOINT if PERF_EVENTS 63 select HAVE_MEMBLOCK 64 select HAVE_PATA_PLATFORM 65 select HAVE_PERF_EVENTS 66 select HAVE_PERF_REGS 67 select HAVE_PERF_USER_STACK_DUMP 68 select HAVE_RCU_TABLE_FREE 69 select HAVE_SYSCALL_TRACEPOINTS 70 select IRQ_DOMAIN 71 select MODULES_USE_ELF_RELA 72 select NO_BOOTMEM 73 select OF 74 select OF_EARLY_FLATTREE 75 select OF_RESERVED_MEM 76 select PERF_USE_VMALLOC 77 select POWER_RESET 78 select POWER_SUPPLY 79 select RTC_LIB 80 select SPARSE_IRQ 81 select SYSCTL_EXCEPTION_TRACE 82 select HAVE_CONTEXT_TRACKING 83 help 84 ARM 64-bit (AArch64) Linux support. 85 86config 64BIT 87 def_bool y 88 89config ARCH_PHYS_ADDR_T_64BIT 90 def_bool y 91 92config MMU 93 def_bool y 94 95config NO_IOPORT_MAP 96 def_bool y if !PCI 97 98config STACKTRACE_SUPPORT 99 def_bool y 100 101config LOCKDEP_SUPPORT 102 def_bool y 103 104config TRACE_IRQFLAGS_SUPPORT 105 def_bool y 106 107config RWSEM_XCHGADD_ALGORITHM 108 def_bool y 109 110config GENERIC_HWEIGHT 111 def_bool y 112 113config GENERIC_CSUM 114 def_bool y 115 116config GENERIC_CALIBRATE_DELAY 117 def_bool y 118 119config ZONE_DMA 120 def_bool y 121 122config HAVE_GENERIC_RCU_GUP 123 def_bool y 124 125config ARCH_DMA_ADDR_T_64BIT 126 def_bool y 127 128config NEED_DMA_MAP_STATE 129 def_bool y 130 131config NEED_SG_DMA_LENGTH 132 def_bool y 133 134config SWIOTLB 135 def_bool y 136 137config IOMMU_HELPER 138 def_bool SWIOTLB 139 140config KERNEL_MODE_NEON 141 def_bool y 142 143config FIX_EARLYCON_MEM 144 def_bool y 145 146config PGTABLE_LEVELS 147 int 148 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 149 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 150 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 151 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48 152 153source "init/Kconfig" 154 155source "kernel/Kconfig.freezer" 156 157menu "Platform selection" 158 159config ARCH_EXYNOS 160 bool 161 help 162 This enables support for Samsung Exynos SoC family 163 164config ARCH_EXYNOS7 165 bool "ARMv8 based Samsung Exynos7" 166 select ARCH_EXYNOS 167 select COMMON_CLK_SAMSUNG 168 select HAVE_S3C2410_WATCHDOG if WATCHDOG 169 select HAVE_S3C_RTC if RTC_CLASS 170 select PINCTRL 171 select PINCTRL_EXYNOS 172 173 help 174 This enables support for Samsung Exynos7 SoC family 175 176config ARCH_FSL_LS2085A 177 bool "Freescale LS2085A SOC" 178 help 179 This enables support for Freescale LS2085A SOC. 180 181config ARCH_MEDIATEK 182 bool "Mediatek MT65xx & MT81xx ARMv8 SoC" 183 select ARM_GIC 184 help 185 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs 186 187config ARCH_SEATTLE 188 bool "AMD Seattle SoC Family" 189 help 190 This enables support for AMD Seattle SOC Family 191 192config ARCH_TEGRA 193 bool "NVIDIA Tegra SoC Family" 194 select ARCH_HAS_RESET_CONTROLLER 195 select ARCH_REQUIRE_GPIOLIB 196 select CLKDEV_LOOKUP 197 select CLKSRC_MMIO 198 select CLKSRC_OF 199 select GENERIC_CLOCKEVENTS 200 select HAVE_CLK 201 select PINCTRL 202 select RESET_CONTROLLER 203 help 204 This enables support for the NVIDIA Tegra SoC family. 205 206config ARCH_TEGRA_132_SOC 207 bool "NVIDIA Tegra132 SoC" 208 depends on ARCH_TEGRA 209 select PINCTRL_TEGRA124 210 select USB_ULPI if USB_PHY 211 select USB_ULPI_VIEWPORT if USB_PHY 212 help 213 Enable support for NVIDIA Tegra132 SoC, based on the Denver 214 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC, 215 but contains an NVIDIA Denver CPU complex in place of 216 Tegra124's "4+1" Cortex-A15 CPU complex. 217 218config ARCH_THUNDER 219 bool "Cavium Inc. Thunder SoC Family" 220 help 221 This enables support for Cavium's Thunder Family of SoCs. 222 223config ARCH_VEXPRESS 224 bool "ARMv8 software model (Versatile Express)" 225 select ARCH_REQUIRE_GPIOLIB 226 select COMMON_CLK_VERSATILE 227 select POWER_RESET_VEXPRESS 228 select VEXPRESS_CONFIG 229 help 230 This enables support for the ARMv8 software model (Versatile 231 Express). 232 233config ARCH_XGENE 234 bool "AppliedMicro X-Gene SOC Family" 235 help 236 This enables support for AppliedMicro X-Gene SOC Family 237 238endmenu 239 240menu "Bus support" 241 242config PCI 243 bool "PCI support" 244 help 245 This feature enables support for PCI bus system. If you say Y 246 here, the kernel will include drivers and infrastructure code 247 to support PCI bus devices. 248 249config PCI_DOMAINS 250 def_bool PCI 251 252config PCI_DOMAINS_GENERIC 253 def_bool PCI 254 255config PCI_SYSCALL 256 def_bool PCI 257 258source "drivers/pci/Kconfig" 259source "drivers/pci/pcie/Kconfig" 260source "drivers/pci/hotplug/Kconfig" 261 262endmenu 263 264menu "Kernel Features" 265 266menu "ARM errata workarounds via the alternatives framework" 267 268config ARM64_ERRATUM_826319 269 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 270 default y 271 help 272 This option adds an alternative code sequence to work around ARM 273 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 274 AXI master interface and an L2 cache. 275 276 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 277 and is unable to accept a certain write via this interface, it will 278 not progress on read data presented on the read data channel and the 279 system can deadlock. 280 281 The workaround promotes data cache clean instructions to 282 data cache clean-and-invalidate. 283 Please note that this does not necessarily enable the workaround, 284 as it depends on the alternative framework, which will only patch 285 the kernel if an affected CPU is detected. 286 287 If unsure, say Y. 288 289config ARM64_ERRATUM_827319 290 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 291 default y 292 help 293 This option adds an alternative code sequence to work around ARM 294 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 295 master interface and an L2 cache. 296 297 Under certain conditions this erratum can cause a clean line eviction 298 to occur at the same time as another transaction to the same address 299 on the AMBA 5 CHI interface, which can cause data corruption if the 300 interconnect reorders the two transactions. 301 302 The workaround promotes data cache clean instructions to 303 data cache clean-and-invalidate. 304 Please note that this does not necessarily enable the workaround, 305 as it depends on the alternative framework, which will only patch 306 the kernel if an affected CPU is detected. 307 308 If unsure, say Y. 309 310config ARM64_ERRATUM_824069 311 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 312 default y 313 help 314 This option adds an alternative code sequence to work around ARM 315 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 316 to a coherent interconnect. 317 318 If a Cortex-A53 processor is executing a store or prefetch for 319 write instruction at the same time as a processor in another 320 cluster is executing a cache maintenance operation to the same 321 address, then this erratum might cause a clean cache line to be 322 incorrectly marked as dirty. 323 324 The workaround promotes data cache clean instructions to 325 data cache clean-and-invalidate. 326 Please note that this option does not necessarily enable the 327 workaround, as it depends on the alternative framework, which will 328 only patch the kernel if an affected CPU is detected. 329 330 If unsure, say Y. 331 332config ARM64_ERRATUM_819472 333 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 334 default y 335 help 336 This option adds an alternative code sequence to work around ARM 337 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 338 present when it is connected to a coherent interconnect. 339 340 If the processor is executing a load and store exclusive sequence at 341 the same time as a processor in another cluster is executing a cache 342 maintenance operation to the same address, then this erratum might 343 cause data corruption. 344 345 The workaround promotes data cache clean instructions to 346 data cache clean-and-invalidate. 347 Please note that this does not necessarily enable the workaround, 348 as it depends on the alternative framework, which will only patch 349 the kernel if an affected CPU is detected. 350 351 If unsure, say Y. 352 353config ARM64_ERRATUM_832075 354 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 355 default y 356 help 357 This option adds an alternative code sequence to work around ARM 358 erratum 832075 on Cortex-A57 parts up to r1p2. 359 360 Affected Cortex-A57 parts might deadlock when exclusive load/store 361 instructions to Write-Back memory are mixed with Device loads. 362 363 The workaround is to promote device loads to use Load-Acquire 364 semantics. 365 Please note that this does not necessarily enable the workaround, 366 as it depends on the alternative framework, which will only patch 367 the kernel if an affected CPU is detected. 368 369 If unsure, say Y. 370 371config ARM64_ERRATUM_845719 372 bool "Cortex-A53: 845719: a load might read incorrect data" 373 depends on COMPAT 374 default y 375 help 376 This option adds an alternative code sequence to work around ARM 377 erratum 845719 on Cortex-A53 parts up to r0p4. 378 379 When running a compat (AArch32) userspace on an affected Cortex-A53 380 part, a load at EL0 from a virtual address that matches the bottom 32 381 bits of the virtual address used by a recent load at (AArch64) EL1 382 might return incorrect data. 383 384 The workaround is to write the contextidr_el1 register on exception 385 return to a 32-bit task. 386 Please note that this does not necessarily enable the workaround, 387 as it depends on the alternative framework, which will only patch 388 the kernel if an affected CPU is detected. 389 390 If unsure, say Y. 391 392endmenu 393 394 395choice 396 prompt "Page size" 397 default ARM64_4K_PAGES 398 help 399 Page size (translation granule) configuration. 400 401config ARM64_4K_PAGES 402 bool "4KB" 403 help 404 This feature enables 4KB pages support. 405 406config ARM64_64K_PAGES 407 bool "64KB" 408 help 409 This feature enables 64KB pages support (4KB by default) 410 allowing only two levels of page tables and faster TLB 411 look-up. AArch32 emulation is not available when this feature 412 is enabled. 413 414endchoice 415 416choice 417 prompt "Virtual address space size" 418 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 419 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 420 help 421 Allows choosing one of multiple possible virtual address 422 space sizes. The level of translation table is determined by 423 a combination of page size and virtual address space size. 424 425config ARM64_VA_BITS_39 426 bool "39-bit" 427 depends on ARM64_4K_PAGES 428 429config ARM64_VA_BITS_42 430 bool "42-bit" 431 depends on ARM64_64K_PAGES 432 433config ARM64_VA_BITS_48 434 bool "48-bit" 435 436endchoice 437 438config ARM64_VA_BITS 439 int 440 default 39 if ARM64_VA_BITS_39 441 default 42 if ARM64_VA_BITS_42 442 default 48 if ARM64_VA_BITS_48 443 444config CPU_BIG_ENDIAN 445 bool "Build big-endian kernel" 446 help 447 Say Y if you plan on running a kernel in big-endian mode. 448 449config SMP 450 bool "Symmetric Multi-Processing" 451 help 452 This enables support for systems with more than one CPU. If 453 you say N here, the kernel will run on single and 454 multiprocessor machines, but will use only one CPU of a 455 multiprocessor machine. If you say Y here, the kernel will run 456 on many, but not all, single processor machines. On a single 457 processor machine, the kernel will run faster if you say N 458 here. 459 460 If you don't know what to do here, say N. 461 462config SCHED_MC 463 bool "Multi-core scheduler support" 464 depends on SMP 465 help 466 Multi-core scheduler support improves the CPU scheduler's decision 467 making when dealing with multi-core CPU chips at a cost of slightly 468 increased overhead in some places. If unsure say N here. 469 470config SCHED_SMT 471 bool "SMT scheduler support" 472 depends on SMP 473 help 474 Improves the CPU scheduler's decision making when dealing with 475 MultiThreading at a cost of slightly increased overhead in some 476 places. If unsure say N here. 477 478config NR_CPUS 479 int "Maximum number of CPUs (2-4096)" 480 range 2 4096 481 depends on SMP 482 # These have to remain sorted largest to smallest 483 default "64" 484 485config HOTPLUG_CPU 486 bool "Support for hot-pluggable CPUs" 487 depends on SMP 488 help 489 Say Y here to experiment with turning CPUs off and on. CPUs 490 can be controlled through /sys/devices/system/cpu. 491 492source kernel/Kconfig.preempt 493 494config UP_LATE_INIT 495 def_bool y 496 depends on !SMP 497 498config HZ 499 int 500 default 100 501 502config ARCH_HAS_HOLES_MEMORYMODEL 503 def_bool y if SPARSEMEM 504 505config ARCH_SPARSEMEM_ENABLE 506 def_bool y 507 select SPARSEMEM_VMEMMAP_ENABLE 508 509config ARCH_SPARSEMEM_DEFAULT 510 def_bool ARCH_SPARSEMEM_ENABLE 511 512config ARCH_SELECT_MEMORY_MODEL 513 def_bool ARCH_SPARSEMEM_ENABLE 514 515config HAVE_ARCH_PFN_VALID 516 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 517 518config HW_PERF_EVENTS 519 bool "Enable hardware performance counter support for perf events" 520 depends on PERF_EVENTS 521 default y 522 help 523 Enable hardware performance counter support for perf events. If 524 disabled, perf events will use software events only. 525 526config SYS_SUPPORTS_HUGETLBFS 527 def_bool y 528 529config ARCH_WANT_GENERAL_HUGETLB 530 def_bool y 531 532config ARCH_WANT_HUGE_PMD_SHARE 533 def_bool y if !ARM64_64K_PAGES 534 535config HAVE_ARCH_TRANSPARENT_HUGEPAGE 536 def_bool y 537 538config ARCH_HAS_CACHE_LINE_SIZE 539 def_bool y 540 541source "mm/Kconfig" 542 543config SECCOMP 544 bool "Enable seccomp to safely compute untrusted bytecode" 545 ---help--- 546 This kernel feature is useful for number crunching applications 547 that may need to compute untrusted bytecode during their 548 execution. By using pipes or other transports made available to 549 the process as file descriptors supporting the read/write 550 syscalls, it's possible to isolate those applications in 551 their own address space using seccomp. Once seccomp is 552 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 553 and the task is only allowed to execute a few safe syscalls 554 defined by each seccomp mode. 555 556config XEN_DOM0 557 def_bool y 558 depends on XEN 559 560config XEN 561 bool "Xen guest support on ARM64" 562 depends on ARM64 && OF 563 select SWIOTLB_XEN 564 help 565 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 566 567config FORCE_MAX_ZONEORDER 568 int 569 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 570 default "11" 571 572menuconfig ARMV8_DEPRECATED 573 bool "Emulate deprecated/obsolete ARMv8 instructions" 574 depends on COMPAT 575 help 576 Legacy software support may require certain instructions 577 that have been deprecated or obsoleted in the architecture. 578 579 Enable this config to enable selective emulation of these 580 features. 581 582 If unsure, say Y 583 584if ARMV8_DEPRECATED 585 586config SWP_EMULATION 587 bool "Emulate SWP/SWPB instructions" 588 help 589 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 590 they are always undefined. Say Y here to enable software 591 emulation of these instructions for userspace using LDXR/STXR. 592 593 In some older versions of glibc [<=2.8] SWP is used during futex 594 trylock() operations with the assumption that the code will not 595 be preempted. This invalid assumption may be more likely to fail 596 with SWP emulation enabled, leading to deadlock of the user 597 application. 598 599 NOTE: when accessing uncached shared regions, LDXR/STXR rely 600 on an external transaction monitoring block called a global 601 monitor to maintain update atomicity. If your system does not 602 implement a global monitor, this option can cause programs that 603 perform SWP operations to uncached memory to deadlock. 604 605 If unsure, say Y 606 607config CP15_BARRIER_EMULATION 608 bool "Emulate CP15 Barrier instructions" 609 help 610 The CP15 barrier instructions - CP15ISB, CP15DSB, and 611 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 612 strongly recommended to use the ISB, DSB, and DMB 613 instructions instead. 614 615 Say Y here to enable software emulation of these 616 instructions for AArch32 userspace code. When this option is 617 enabled, CP15 barrier usage is traced which can help 618 identify software that needs updating. 619 620 If unsure, say Y 621 622config SETEND_EMULATION 623 bool "Emulate SETEND instruction" 624 help 625 The SETEND instruction alters the data-endianness of the 626 AArch32 EL0, and is deprecated in ARMv8. 627 628 Say Y here to enable software emulation of the instruction 629 for AArch32 userspace code. 630 631 Note: All the cpus on the system must have mixed endian support at EL0 632 for this feature to be enabled. If a new CPU - which doesn't support mixed 633 endian - is hotplugged in after this feature has been enabled, there could 634 be unexpected results in the applications. 635 636 If unsure, say Y 637endif 638 639endmenu 640 641menu "Boot options" 642 643config CMDLINE 644 string "Default kernel command string" 645 default "" 646 help 647 Provide a set of default command-line options at build time by 648 entering them here. As a minimum, you should specify the the 649 root device (e.g. root=/dev/nfs). 650 651config CMDLINE_FORCE 652 bool "Always use the default kernel command string" 653 help 654 Always use the default kernel command string, even if the boot 655 loader passes other arguments to the kernel. 656 This is useful if you cannot or don't want to change the 657 command-line options your boot loader passes to the kernel. 658 659config EFI_STUB 660 bool 661 662config EFI 663 bool "UEFI runtime support" 664 depends on OF && !CPU_BIG_ENDIAN 665 select LIBFDT 666 select UCS2_STRING 667 select EFI_PARAMS_FROM_FDT 668 select EFI_RUNTIME_WRAPPERS 669 select EFI_STUB 670 select EFI_ARMSTUB 671 default y 672 help 673 This option provides support for runtime services provided 674 by UEFI firmware (such as non-volatile variables, realtime 675 clock, and platform reset). A UEFI stub is also provided to 676 allow the kernel to be booted as an EFI application. This 677 is only useful on systems that have UEFI firmware. 678 679config DMI 680 bool "Enable support for SMBIOS (DMI) tables" 681 depends on EFI 682 default y 683 help 684 This enables SMBIOS/DMI feature for systems. 685 686 This option is only useful on systems that have UEFI firmware. 687 However, even with this option, the resultant kernel should 688 continue to boot on existing non-UEFI platforms. 689 690endmenu 691 692menu "Userspace binary formats" 693 694source "fs/Kconfig.binfmt" 695 696config COMPAT 697 bool "Kernel support for 32-bit EL0" 698 depends on !ARM64_64K_PAGES || EXPERT 699 select COMPAT_BINFMT_ELF 700 select HAVE_UID16 701 select OLD_SIGSUSPEND3 702 select COMPAT_OLD_SIGACTION 703 help 704 This option enables support for a 32-bit EL0 running under a 64-bit 705 kernel at EL1. AArch32-specific components such as system calls, 706 the user helper functions, VFP support and the ptrace interface are 707 handled appropriately by the kernel. 708 709 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you 710 will only be able to execute AArch32 binaries that were compiled with 711 64k aligned segments. 712 713 If you want to execute 32-bit userspace applications, say Y. 714 715config SYSVIPC_COMPAT 716 def_bool y 717 depends on COMPAT && SYSVIPC 718 719endmenu 720 721menu "Power management options" 722 723source "kernel/power/Kconfig" 724 725config ARCH_SUSPEND_POSSIBLE 726 def_bool y 727 728endmenu 729 730menu "CPU Power Management" 731 732source "drivers/cpuidle/Kconfig" 733 734source "drivers/cpufreq/Kconfig" 735 736endmenu 737 738source "net/Kconfig" 739 740source "drivers/Kconfig" 741 742source "drivers/firmware/Kconfig" 743 744source "fs/Kconfig" 745 746source "arch/arm64/kvm/Kconfig" 747 748source "arch/arm64/Kconfig.debug" 749 750source "security/Kconfig" 751 752source "crypto/Kconfig" 753if CRYPTO 754source "arch/arm64/crypto/Kconfig" 755endif 756 757source "lib/Kconfig" 758