1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ARCH_HAS_DEVMEM_IS_ALLOWED 7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 8 select ARCH_HAS_ELF_RANDOMIZE 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_HAS_SG_CHAIN 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_SUPPORTS_ATOMIC_RMW 14 select ARCH_WANT_OPTIONAL_GPIOLIB 15 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 16 select ARCH_WANT_FRAME_POINTERS 17 select ARCH_HAS_UBSAN_SANITIZE_ALL 18 select ARM_AMBA 19 select ARM_ARCH_TIMER 20 select ARM_GIC 21 select AUDIT_ARCH_COMPAT_GENERIC 22 select ARM_GIC_V2M if PCI_MSI 23 select ARM_GIC_V3 24 select ARM_GIC_V3_ITS if PCI_MSI 25 select ARM_PSCI_FW 26 select BUILDTIME_EXTABLE_SORT 27 select CLONE_BACKWARDS 28 select COMMON_CLK 29 select CPU_PM if (SUSPEND || CPU_IDLE) 30 select DCACHE_WORD_ACCESS 31 select EDAC_SUPPORT 32 select FRAME_POINTER 33 select GENERIC_ALLOCATOR 34 select GENERIC_CLOCKEVENTS 35 select GENERIC_CLOCKEVENTS_BROADCAST 36 select GENERIC_CPU_AUTOPROBE 37 select GENERIC_EARLY_IOREMAP 38 select GENERIC_IDLE_POLL_SETUP 39 select GENERIC_IRQ_PROBE 40 select GENERIC_IRQ_SHOW 41 select GENERIC_IRQ_SHOW_LEVEL 42 select GENERIC_PCI_IOMAP 43 select GENERIC_SCHED_CLOCK 44 select GENERIC_SMP_IDLE_THREAD 45 select GENERIC_STRNCPY_FROM_USER 46 select GENERIC_STRNLEN_USER 47 select GENERIC_TIME_VSYSCALL 48 select HANDLE_DOMAIN_IRQ 49 select HARDIRQS_SW_RESEND 50 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 51 select HAVE_ARCH_AUDITSYSCALL 52 select HAVE_ARCH_BITREVERSE 53 select HAVE_ARCH_HUGE_VMAP 54 select HAVE_ARCH_JUMP_LABEL 55 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 56 select HAVE_ARCH_KGDB 57 select HAVE_ARCH_MMAP_RND_BITS 58 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 59 select HAVE_ARCH_SECCOMP_FILTER 60 select HAVE_ARCH_TRACEHOOK 61 select HAVE_BPF_JIT 62 select HAVE_C_RECORDMCOUNT 63 select HAVE_CC_STACKPROTECTOR 64 select HAVE_CMPXCHG_DOUBLE 65 select HAVE_CMPXCHG_LOCAL 66 select HAVE_DEBUG_BUGVERBOSE 67 select HAVE_DEBUG_KMEMLEAK 68 select HAVE_DMA_API_DEBUG 69 select HAVE_DMA_CONTIGUOUS 70 select HAVE_DYNAMIC_FTRACE 71 select HAVE_EFFICIENT_UNALIGNED_ACCESS 72 select HAVE_FTRACE_MCOUNT_RECORD 73 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_GRAPH_TRACER 75 select HAVE_GENERIC_DMA_COHERENT 76 select HAVE_HW_BREAKPOINT if PERF_EVENTS 77 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_MEMBLOCK 79 select HAVE_PATA_PLATFORM 80 select HAVE_PERF_EVENTS 81 select HAVE_PERF_REGS 82 select HAVE_PERF_USER_STACK_DUMP 83 select HAVE_RCU_TABLE_FREE 84 select HAVE_SYSCALL_TRACEPOINTS 85 select IOMMU_DMA if IOMMU_SUPPORT 86 select IRQ_DOMAIN 87 select IRQ_FORCED_THREADING 88 select MODULES_USE_ELF_RELA 89 select NO_BOOTMEM 90 select OF 91 select OF_EARLY_FLATTREE 92 select OF_RESERVED_MEM 93 select PERF_USE_VMALLOC 94 select POWER_RESET 95 select POWER_SUPPLY 96 select RTC_LIB 97 select SPARSE_IRQ 98 select SYSCTL_EXCEPTION_TRACE 99 select HAVE_CONTEXT_TRACKING 100 select HAVE_ARM_SMCCC 101 help 102 ARM 64-bit (AArch64) Linux support. 103 104config 64BIT 105 def_bool y 106 107config ARCH_PHYS_ADDR_T_64BIT 108 def_bool y 109 110config MMU 111 def_bool y 112 113config ARCH_MMAP_RND_BITS_MIN 114 default 14 if ARM64_64K_PAGES 115 default 16 if ARM64_16K_PAGES 116 default 18 117 118# max bits determined by the following formula: 119# VA_BITS - PAGE_SHIFT - 3 120config ARCH_MMAP_RND_BITS_MAX 121 default 19 if ARM64_VA_BITS=36 122 default 24 if ARM64_VA_BITS=39 123 default 27 if ARM64_VA_BITS=42 124 default 30 if ARM64_VA_BITS=47 125 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 126 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 127 default 33 if ARM64_VA_BITS=48 128 default 14 if ARM64_64K_PAGES 129 default 16 if ARM64_16K_PAGES 130 default 18 131 132config ARCH_MMAP_RND_COMPAT_BITS_MIN 133 default 7 if ARM64_64K_PAGES 134 default 9 if ARM64_16K_PAGES 135 default 11 136 137config ARCH_MMAP_RND_COMPAT_BITS_MAX 138 default 16 139 140config NO_IOPORT_MAP 141 def_bool y if !PCI 142 143config STACKTRACE_SUPPORT 144 def_bool y 145 146config ILLEGAL_POINTER_VALUE 147 hex 148 default 0xdead000000000000 149 150config LOCKDEP_SUPPORT 151 def_bool y 152 153config TRACE_IRQFLAGS_SUPPORT 154 def_bool y 155 156config RWSEM_XCHGADD_ALGORITHM 157 def_bool y 158 159config GENERIC_BUG 160 def_bool y 161 depends on BUG 162 163config GENERIC_BUG_RELATIVE_POINTERS 164 def_bool y 165 depends on GENERIC_BUG 166 167config GENERIC_HWEIGHT 168 def_bool y 169 170config GENERIC_CSUM 171 def_bool y 172 173config GENERIC_CALIBRATE_DELAY 174 def_bool y 175 176config ZONE_DMA 177 def_bool y 178 179config HAVE_GENERIC_RCU_GUP 180 def_bool y 181 182config ARCH_DMA_ADDR_T_64BIT 183 def_bool y 184 185config NEED_DMA_MAP_STATE 186 def_bool y 187 188config NEED_SG_DMA_LENGTH 189 def_bool y 190 191config SMP 192 def_bool y 193 194config SWIOTLB 195 def_bool y 196 197config IOMMU_HELPER 198 def_bool SWIOTLB 199 200config KERNEL_MODE_NEON 201 def_bool y 202 203config FIX_EARLYCON_MEM 204 def_bool y 205 206config PGTABLE_LEVELS 207 int 208 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 209 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 210 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 211 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 212 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 213 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 214 215source "init/Kconfig" 216 217source "kernel/Kconfig.freezer" 218 219source "arch/arm64/Kconfig.platforms" 220 221menu "Bus support" 222 223config PCI 224 bool "PCI support" 225 help 226 This feature enables support for PCI bus system. If you say Y 227 here, the kernel will include drivers and infrastructure code 228 to support PCI bus devices. 229 230config PCI_DOMAINS 231 def_bool PCI 232 233config PCI_DOMAINS_GENERIC 234 def_bool PCI 235 236config PCI_SYSCALL 237 def_bool PCI 238 239source "drivers/pci/Kconfig" 240 241endmenu 242 243menu "Kernel Features" 244 245menu "ARM errata workarounds via the alternatives framework" 246 247config ARM64_ERRATUM_826319 248 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 249 default y 250 help 251 This option adds an alternative code sequence to work around ARM 252 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 253 AXI master interface and an L2 cache. 254 255 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 256 and is unable to accept a certain write via this interface, it will 257 not progress on read data presented on the read data channel and the 258 system can deadlock. 259 260 The workaround promotes data cache clean instructions to 261 data cache clean-and-invalidate. 262 Please note that this does not necessarily enable the workaround, 263 as it depends on the alternative framework, which will only patch 264 the kernel if an affected CPU is detected. 265 266 If unsure, say Y. 267 268config ARM64_ERRATUM_827319 269 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 270 default y 271 help 272 This option adds an alternative code sequence to work around ARM 273 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 274 master interface and an L2 cache. 275 276 Under certain conditions this erratum can cause a clean line eviction 277 to occur at the same time as another transaction to the same address 278 on the AMBA 5 CHI interface, which can cause data corruption if the 279 interconnect reorders the two transactions. 280 281 The workaround promotes data cache clean instructions to 282 data cache clean-and-invalidate. 283 Please note that this does not necessarily enable the workaround, 284 as it depends on the alternative framework, which will only patch 285 the kernel if an affected CPU is detected. 286 287 If unsure, say Y. 288 289config ARM64_ERRATUM_824069 290 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 291 default y 292 help 293 This option adds an alternative code sequence to work around ARM 294 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 295 to a coherent interconnect. 296 297 If a Cortex-A53 processor is executing a store or prefetch for 298 write instruction at the same time as a processor in another 299 cluster is executing a cache maintenance operation to the same 300 address, then this erratum might cause a clean cache line to be 301 incorrectly marked as dirty. 302 303 The workaround promotes data cache clean instructions to 304 data cache clean-and-invalidate. 305 Please note that this option does not necessarily enable the 306 workaround, as it depends on the alternative framework, which will 307 only patch the kernel if an affected CPU is detected. 308 309 If unsure, say Y. 310 311config ARM64_ERRATUM_819472 312 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 313 default y 314 help 315 This option adds an alternative code sequence to work around ARM 316 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 317 present when it is connected to a coherent interconnect. 318 319 If the processor is executing a load and store exclusive sequence at 320 the same time as a processor in another cluster is executing a cache 321 maintenance operation to the same address, then this erratum might 322 cause data corruption. 323 324 The workaround promotes data cache clean instructions to 325 data cache clean-and-invalidate. 326 Please note that this does not necessarily enable the workaround, 327 as it depends on the alternative framework, which will only patch 328 the kernel if an affected CPU is detected. 329 330 If unsure, say Y. 331 332config ARM64_ERRATUM_832075 333 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 334 default y 335 help 336 This option adds an alternative code sequence to work around ARM 337 erratum 832075 on Cortex-A57 parts up to r1p2. 338 339 Affected Cortex-A57 parts might deadlock when exclusive load/store 340 instructions to Write-Back memory are mixed with Device loads. 341 342 The workaround is to promote device loads to use Load-Acquire 343 semantics. 344 Please note that this does not necessarily enable the workaround, 345 as it depends on the alternative framework, which will only patch 346 the kernel if an affected CPU is detected. 347 348 If unsure, say Y. 349 350config ARM64_ERRATUM_834220 351 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 352 depends on KVM 353 default y 354 help 355 This option adds an alternative code sequence to work around ARM 356 erratum 834220 on Cortex-A57 parts up to r1p2. 357 358 Affected Cortex-A57 parts might report a Stage 2 translation 359 fault as the result of a Stage 1 fault for load crossing a 360 page boundary when there is a permission or device memory 361 alignment fault at Stage 1 and a translation fault at Stage 2. 362 363 The workaround is to verify that the Stage 1 translation 364 doesn't generate a fault before handling the Stage 2 fault. 365 Please note that this does not necessarily enable the workaround, 366 as it depends on the alternative framework, which will only patch 367 the kernel if an affected CPU is detected. 368 369 If unsure, say Y. 370 371config ARM64_ERRATUM_845719 372 bool "Cortex-A53: 845719: a load might read incorrect data" 373 depends on COMPAT 374 default y 375 help 376 This option adds an alternative code sequence to work around ARM 377 erratum 845719 on Cortex-A53 parts up to r0p4. 378 379 When running a compat (AArch32) userspace on an affected Cortex-A53 380 part, a load at EL0 from a virtual address that matches the bottom 32 381 bits of the virtual address used by a recent load at (AArch64) EL1 382 might return incorrect data. 383 384 The workaround is to write the contextidr_el1 register on exception 385 return to a 32-bit task. 386 Please note that this does not necessarily enable the workaround, 387 as it depends on the alternative framework, which will only patch 388 the kernel if an affected CPU is detected. 389 390 If unsure, say Y. 391 392config ARM64_ERRATUM_843419 393 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 394 depends on MODULES 395 default y 396 select ARM64_MODULE_CMODEL_LARGE 397 help 398 This option builds kernel modules using the large memory model in 399 order to avoid the use of the ADRP instruction, which can cause 400 a subsequent memory access to use an incorrect address on Cortex-A53 401 parts up to r0p4. 402 403 Note that the kernel itself must be linked with a version of ld 404 which fixes potentially affected ADRP instructions through the 405 use of veneers. 406 407 If unsure, say Y. 408 409config CAVIUM_ERRATUM_22375 410 bool "Cavium erratum 22375, 24313" 411 default y 412 help 413 Enable workaround for erratum 22375, 24313. 414 415 This implements two gicv3-its errata workarounds for ThunderX. Both 416 with small impact affecting only ITS table allocation. 417 418 erratum 22375: only alloc 8MB table size 419 erratum 24313: ignore memory access type 420 421 The fixes are in ITS initialization and basically ignore memory access 422 type and table size provided by the TYPER and BASER registers. 423 424 If unsure, say Y. 425 426config CAVIUM_ERRATUM_23154 427 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 428 default y 429 help 430 The gicv3 of ThunderX requires a modified version for 431 reading the IAR status to ensure data synchronization 432 (access to icc_iar1_el1 is not sync'ed before and after). 433 434 If unsure, say Y. 435 436config CAVIUM_ERRATUM_27456 437 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 438 default y 439 help 440 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 441 instructions may cause the icache to become corrupted if it 442 contains data for a non-current ASID. The fix is to 443 invalidate the icache when changing the mm context. 444 445 If unsure, say Y. 446 447endmenu 448 449 450choice 451 prompt "Page size" 452 default ARM64_4K_PAGES 453 help 454 Page size (translation granule) configuration. 455 456config ARM64_4K_PAGES 457 bool "4KB" 458 help 459 This feature enables 4KB pages support. 460 461config ARM64_16K_PAGES 462 bool "16KB" 463 help 464 The system will use 16KB pages support. AArch32 emulation 465 requires applications compiled with 16K (or a multiple of 16K) 466 aligned segments. 467 468config ARM64_64K_PAGES 469 bool "64KB" 470 help 471 This feature enables 64KB pages support (4KB by default) 472 allowing only two levels of page tables and faster TLB 473 look-up. AArch32 emulation requires applications compiled 474 with 64K aligned segments. 475 476endchoice 477 478choice 479 prompt "Virtual address space size" 480 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 481 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 482 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 483 help 484 Allows choosing one of multiple possible virtual address 485 space sizes. The level of translation table is determined by 486 a combination of page size and virtual address space size. 487 488config ARM64_VA_BITS_36 489 bool "36-bit" if EXPERT 490 depends on ARM64_16K_PAGES 491 492config ARM64_VA_BITS_39 493 bool "39-bit" 494 depends on ARM64_4K_PAGES 495 496config ARM64_VA_BITS_42 497 bool "42-bit" 498 depends on ARM64_64K_PAGES 499 500config ARM64_VA_BITS_47 501 bool "47-bit" 502 depends on ARM64_16K_PAGES 503 504config ARM64_VA_BITS_48 505 bool "48-bit" 506 507endchoice 508 509config ARM64_VA_BITS 510 int 511 default 36 if ARM64_VA_BITS_36 512 default 39 if ARM64_VA_BITS_39 513 default 42 if ARM64_VA_BITS_42 514 default 47 if ARM64_VA_BITS_47 515 default 48 if ARM64_VA_BITS_48 516 517config CPU_BIG_ENDIAN 518 bool "Build big-endian kernel" 519 help 520 Say Y if you plan on running a kernel in big-endian mode. 521 522config SCHED_MC 523 bool "Multi-core scheduler support" 524 help 525 Multi-core scheduler support improves the CPU scheduler's decision 526 making when dealing with multi-core CPU chips at a cost of slightly 527 increased overhead in some places. If unsure say N here. 528 529config SCHED_SMT 530 bool "SMT scheduler support" 531 help 532 Improves the CPU scheduler's decision making when dealing with 533 MultiThreading at a cost of slightly increased overhead in some 534 places. If unsure say N here. 535 536config NR_CPUS 537 int "Maximum number of CPUs (2-4096)" 538 range 2 4096 539 # These have to remain sorted largest to smallest 540 default "64" 541 542config HOTPLUG_CPU 543 bool "Support for hot-pluggable CPUs" 544 select GENERIC_IRQ_MIGRATION 545 help 546 Say Y here to experiment with turning CPUs off and on. CPUs 547 can be controlled through /sys/devices/system/cpu. 548 549source kernel/Kconfig.preempt 550source kernel/Kconfig.hz 551 552config ARCH_SUPPORTS_DEBUG_PAGEALLOC 553 def_bool y 554 555config ARCH_HAS_HOLES_MEMORYMODEL 556 def_bool y if SPARSEMEM 557 558config ARCH_SPARSEMEM_ENABLE 559 def_bool y 560 select SPARSEMEM_VMEMMAP_ENABLE 561 562config ARCH_SPARSEMEM_DEFAULT 563 def_bool ARCH_SPARSEMEM_ENABLE 564 565config ARCH_SELECT_MEMORY_MODEL 566 def_bool ARCH_SPARSEMEM_ENABLE 567 568config HAVE_ARCH_PFN_VALID 569 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 570 571config HW_PERF_EVENTS 572 def_bool y 573 depends on ARM_PMU 574 575config SYS_SUPPORTS_HUGETLBFS 576 def_bool y 577 578config ARCH_WANT_HUGE_PMD_SHARE 579 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 580 581config HAVE_ARCH_TRANSPARENT_HUGEPAGE 582 def_bool y 583 584config ARCH_HAS_CACHE_LINE_SIZE 585 def_bool y 586 587source "mm/Kconfig" 588 589config SECCOMP 590 bool "Enable seccomp to safely compute untrusted bytecode" 591 ---help--- 592 This kernel feature is useful for number crunching applications 593 that may need to compute untrusted bytecode during their 594 execution. By using pipes or other transports made available to 595 the process as file descriptors supporting the read/write 596 syscalls, it's possible to isolate those applications in 597 their own address space using seccomp. Once seccomp is 598 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 599 and the task is only allowed to execute a few safe syscalls 600 defined by each seccomp mode. 601 602config PARAVIRT 603 bool "Enable paravirtualization code" 604 help 605 This changes the kernel so it can modify itself when it is run 606 under a hypervisor, potentially improving performance significantly 607 over full virtualization. 608 609config PARAVIRT_TIME_ACCOUNTING 610 bool "Paravirtual steal time accounting" 611 select PARAVIRT 612 default n 613 help 614 Select this option to enable fine granularity task steal time 615 accounting. Time spent executing other tasks in parallel with 616 the current vCPU is discounted from the vCPU power. To account for 617 that, there can be a small performance impact. 618 619 If in doubt, say N here. 620 621config XEN_DOM0 622 def_bool y 623 depends on XEN 624 625config XEN 626 bool "Xen guest support on ARM64" 627 depends on ARM64 && OF 628 select SWIOTLB_XEN 629 select PARAVIRT 630 help 631 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 632 633config FORCE_MAX_ZONEORDER 634 int 635 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 636 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 637 default "11" 638 help 639 The kernel memory allocator divides physically contiguous memory 640 blocks into "zones", where each zone is a power of two number of 641 pages. This option selects the largest power of two that the kernel 642 keeps in the memory allocator. If you need to allocate very large 643 blocks of physically contiguous memory, then you may need to 644 increase this value. 645 646 This config option is actually maximum order plus one. For example, 647 a value of 11 means that the largest free memory block is 2^10 pages. 648 649 We make sure that we can allocate upto a HugePage size for each configuration. 650 Hence we have : 651 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 652 653 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 654 4M allocations matching the default size used by generic code. 655 656menuconfig ARMV8_DEPRECATED 657 bool "Emulate deprecated/obsolete ARMv8 instructions" 658 depends on COMPAT 659 help 660 Legacy software support may require certain instructions 661 that have been deprecated or obsoleted in the architecture. 662 663 Enable this config to enable selective emulation of these 664 features. 665 666 If unsure, say Y 667 668if ARMV8_DEPRECATED 669 670config SWP_EMULATION 671 bool "Emulate SWP/SWPB instructions" 672 help 673 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 674 they are always undefined. Say Y here to enable software 675 emulation of these instructions for userspace using LDXR/STXR. 676 677 In some older versions of glibc [<=2.8] SWP is used during futex 678 trylock() operations with the assumption that the code will not 679 be preempted. This invalid assumption may be more likely to fail 680 with SWP emulation enabled, leading to deadlock of the user 681 application. 682 683 NOTE: when accessing uncached shared regions, LDXR/STXR rely 684 on an external transaction monitoring block called a global 685 monitor to maintain update atomicity. If your system does not 686 implement a global monitor, this option can cause programs that 687 perform SWP operations to uncached memory to deadlock. 688 689 If unsure, say Y 690 691config CP15_BARRIER_EMULATION 692 bool "Emulate CP15 Barrier instructions" 693 help 694 The CP15 barrier instructions - CP15ISB, CP15DSB, and 695 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 696 strongly recommended to use the ISB, DSB, and DMB 697 instructions instead. 698 699 Say Y here to enable software emulation of these 700 instructions for AArch32 userspace code. When this option is 701 enabled, CP15 barrier usage is traced which can help 702 identify software that needs updating. 703 704 If unsure, say Y 705 706config SETEND_EMULATION 707 bool "Emulate SETEND instruction" 708 help 709 The SETEND instruction alters the data-endianness of the 710 AArch32 EL0, and is deprecated in ARMv8. 711 712 Say Y here to enable software emulation of the instruction 713 for AArch32 userspace code. 714 715 Note: All the cpus on the system must have mixed endian support at EL0 716 for this feature to be enabled. If a new CPU - which doesn't support mixed 717 endian - is hotplugged in after this feature has been enabled, there could 718 be unexpected results in the applications. 719 720 If unsure, say Y 721endif 722 723menu "ARMv8.1 architectural features" 724 725config ARM64_HW_AFDBM 726 bool "Support for hardware updates of the Access and Dirty page flags" 727 default y 728 help 729 The ARMv8.1 architecture extensions introduce support for 730 hardware updates of the access and dirty information in page 731 table entries. When enabled in TCR_EL1 (HA and HD bits) on 732 capable processors, accesses to pages with PTE_AF cleared will 733 set this bit instead of raising an access flag fault. 734 Similarly, writes to read-only pages with the DBM bit set will 735 clear the read-only bit (AP[2]) instead of raising a 736 permission fault. 737 738 Kernels built with this configuration option enabled continue 739 to work on pre-ARMv8.1 hardware and the performance impact is 740 minimal. If unsure, say Y. 741 742config ARM64_PAN 743 bool "Enable support for Privileged Access Never (PAN)" 744 default y 745 help 746 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 747 prevents the kernel or hypervisor from accessing user-space (EL0) 748 memory directly. 749 750 Choosing this option will cause any unprotected (not using 751 copy_to_user et al) memory access to fail with a permission fault. 752 753 The feature is detected at runtime, and will remain as a 'nop' 754 instruction if the cpu does not implement the feature. 755 756config ARM64_LSE_ATOMICS 757 bool "Atomic instructions" 758 help 759 As part of the Large System Extensions, ARMv8.1 introduces new 760 atomic instructions that are designed specifically to scale in 761 very large systems. 762 763 Say Y here to make use of these instructions for the in-kernel 764 atomic routines. This incurs a small overhead on CPUs that do 765 not support these instructions and requires the kernel to be 766 built with binutils >= 2.25. 767 768config ARM64_VHE 769 bool "Enable support for Virtualization Host Extensions (VHE)" 770 default y 771 help 772 Virtualization Host Extensions (VHE) allow the kernel to run 773 directly at EL2 (instead of EL1) on processors that support 774 it. This leads to better performance for KVM, as they reduce 775 the cost of the world switch. 776 777 Selecting this option allows the VHE feature to be detected 778 at runtime, and does not affect processors that do not 779 implement this feature. 780 781endmenu 782 783menu "ARMv8.2 architectural features" 784 785config ARM64_UAO 786 bool "Enable support for User Access Override (UAO)" 787 default y 788 help 789 User Access Override (UAO; part of the ARMv8.2 Extensions) 790 causes the 'unprivileged' variant of the load/store instructions to 791 be overriden to be privileged. 792 793 This option changes get_user() and friends to use the 'unprivileged' 794 variant of the load/store instructions. This ensures that user-space 795 really did have access to the supplied memory. When addr_limit is 796 set to kernel memory the UAO bit will be set, allowing privileged 797 access to kernel memory. 798 799 Choosing this option will cause copy_to_user() et al to use user-space 800 memory permissions. 801 802 The feature is detected at runtime, the kernel will use the 803 regular load/store instructions if the cpu does not implement the 804 feature. 805 806endmenu 807 808config ARM64_MODULE_CMODEL_LARGE 809 bool 810 811config ARM64_MODULE_PLTS 812 bool 813 select ARM64_MODULE_CMODEL_LARGE 814 select HAVE_MOD_ARCH_SPECIFIC 815 816config RELOCATABLE 817 bool 818 help 819 This builds the kernel as a Position Independent Executable (PIE), 820 which retains all relocation metadata required to relocate the 821 kernel binary at runtime to a different virtual address than the 822 address it was linked at. 823 Since AArch64 uses the RELA relocation format, this requires a 824 relocation pass at runtime even if the kernel is loaded at the 825 same address it was linked at. 826 827config RANDOMIZE_BASE 828 bool "Randomize the address of the kernel image" 829 select ARM64_MODULE_PLTS 830 select RELOCATABLE 831 help 832 Randomizes the virtual address at which the kernel image is 833 loaded, as a security feature that deters exploit attempts 834 relying on knowledge of the location of kernel internals. 835 836 It is the bootloader's job to provide entropy, by passing a 837 random u64 value in /chosen/kaslr-seed at kernel entry. 838 839 When booting via the UEFI stub, it will invoke the firmware's 840 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 841 to the kernel proper. In addition, it will randomise the physical 842 location of the kernel Image as well. 843 844 If unsure, say N. 845 846config RANDOMIZE_MODULE_REGION_FULL 847 bool "Randomize the module region independently from the core kernel" 848 depends on RANDOMIZE_BASE 849 default y 850 help 851 Randomizes the location of the module region without considering the 852 location of the core kernel. This way, it is impossible for modules 853 to leak information about the location of core kernel data structures 854 but it does imply that function calls between modules and the core 855 kernel will need to be resolved via veneers in the module PLT. 856 857 When this option is not set, the module region will be randomized over 858 a limited range that contains the [_stext, _etext] interval of the 859 core kernel, so branch relocations are always in range. 860 861endmenu 862 863menu "Boot options" 864 865config ARM64_ACPI_PARKING_PROTOCOL 866 bool "Enable support for the ARM64 ACPI parking protocol" 867 depends on ACPI 868 help 869 Enable support for the ARM64 ACPI parking protocol. If disabled 870 the kernel will not allow booting through the ARM64 ACPI parking 871 protocol even if the corresponding data is present in the ACPI 872 MADT table. 873 874config CMDLINE 875 string "Default kernel command string" 876 default "" 877 help 878 Provide a set of default command-line options at build time by 879 entering them here. As a minimum, you should specify the the 880 root device (e.g. root=/dev/nfs). 881 882config CMDLINE_FORCE 883 bool "Always use the default kernel command string" 884 help 885 Always use the default kernel command string, even if the boot 886 loader passes other arguments to the kernel. 887 This is useful if you cannot or don't want to change the 888 command-line options your boot loader passes to the kernel. 889 890config EFI_STUB 891 bool 892 893config EFI 894 bool "UEFI runtime support" 895 depends on OF && !CPU_BIG_ENDIAN 896 select LIBFDT 897 select UCS2_STRING 898 select EFI_PARAMS_FROM_FDT 899 select EFI_RUNTIME_WRAPPERS 900 select EFI_STUB 901 select EFI_ARMSTUB 902 default y 903 help 904 This option provides support for runtime services provided 905 by UEFI firmware (such as non-volatile variables, realtime 906 clock, and platform reset). A UEFI stub is also provided to 907 allow the kernel to be booted as an EFI application. This 908 is only useful on systems that have UEFI firmware. 909 910config DMI 911 bool "Enable support for SMBIOS (DMI) tables" 912 depends on EFI 913 default y 914 help 915 This enables SMBIOS/DMI feature for systems. 916 917 This option is only useful on systems that have UEFI firmware. 918 However, even with this option, the resultant kernel should 919 continue to boot on existing non-UEFI platforms. 920 921endmenu 922 923menu "Userspace binary formats" 924 925source "fs/Kconfig.binfmt" 926 927config COMPAT 928 bool "Kernel support for 32-bit EL0" 929 depends on ARM64_4K_PAGES || EXPERT 930 select COMPAT_BINFMT_ELF 931 select HAVE_UID16 932 select OLD_SIGSUSPEND3 933 select COMPAT_OLD_SIGACTION 934 help 935 This option enables support for a 32-bit EL0 running under a 64-bit 936 kernel at EL1. AArch32-specific components such as system calls, 937 the user helper functions, VFP support and the ptrace interface are 938 handled appropriately by the kernel. 939 940 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 941 that you will only be able to execute AArch32 binaries that were compiled 942 with page size aligned segments. 943 944 If you want to execute 32-bit userspace applications, say Y. 945 946config SYSVIPC_COMPAT 947 def_bool y 948 depends on COMPAT && SYSVIPC 949 950endmenu 951 952menu "Power management options" 953 954source "kernel/power/Kconfig" 955 956config ARCH_SUSPEND_POSSIBLE 957 def_bool y 958 959endmenu 960 961menu "CPU Power Management" 962 963source "drivers/cpuidle/Kconfig" 964 965source "drivers/cpufreq/Kconfig" 966 967endmenu 968 969source "net/Kconfig" 970 971source "drivers/Kconfig" 972 973source "drivers/firmware/Kconfig" 974 975source "drivers/acpi/Kconfig" 976 977source "fs/Kconfig" 978 979source "arch/arm64/kvm/Kconfig" 980 981source "arch/arm64/Kconfig.debug" 982 983source "security/Kconfig" 984 985source "crypto/Kconfig" 986if CRYPTO 987source "arch/arm64/crypto/Kconfig" 988endif 989 990source "lib/Kconfig" 991