1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_VM_GET_PAGE_PROT 49 select ARCH_HAS_ZONE_DMA_SET if EXPERT 50 select ARCH_HAVE_ELF_PROT 51 select ARCH_HAVE_NMI_SAFE_CMPXCHG 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 96 select ARCH_WANT_DEFAULT_BPF_JIT 97 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 98 select ARCH_WANT_FRAME_POINTERS 99 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 100 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 101 select ARCH_WANT_LD_ORPHAN_WARN 102 select ARCH_WANTS_NO_INSTR 103 select ARCH_HAS_UBSAN_SANITIZE_ALL 104 select ARM_AMBA 105 select ARM_ARCH_TIMER 106 select ARM_GIC 107 select AUDIT_ARCH_COMPAT_GENERIC 108 select ARM_GIC_V2M if PCI 109 select ARM_GIC_V3 110 select ARM_GIC_V3_ITS if PCI 111 select ARM_PSCI_FW 112 select BUILDTIME_TABLE_SORT 113 select CLONE_BACKWARDS 114 select COMMON_CLK 115 select CPU_PM if (SUSPEND || CPU_IDLE) 116 select CRC32 117 select DCACHE_WORD_ACCESS 118 select DMA_DIRECT_REMAP 119 select EDAC_SUPPORT 120 select FRAME_POINTER 121 select GENERIC_ALLOCATOR 122 select GENERIC_ARCH_TOPOLOGY 123 select GENERIC_CLOCKEVENTS_BROADCAST 124 select GENERIC_CPU_AUTOPROBE 125 select GENERIC_CPU_VULNERABILITIES 126 select GENERIC_EARLY_IOREMAP 127 select GENERIC_IDLE_POLL_SETUP 128 select GENERIC_IRQ_IPI 129 select GENERIC_IRQ_PROBE 130 select GENERIC_IRQ_SHOW 131 select GENERIC_IRQ_SHOW_LEVEL 132 select GENERIC_LIB_DEVMEM_IS_ALLOWED 133 select GENERIC_PCI_IOMAP 134 select GENERIC_PTDUMP 135 select GENERIC_SCHED_CLOCK 136 select GENERIC_SMP_IDLE_THREAD 137 select GENERIC_TIME_VSYSCALL 138 select GENERIC_GETTIMEOFDAY 139 select GENERIC_VDSO_TIME_NS 140 select HARDIRQS_SW_RESEND 141 select HAVE_MOVE_PMD 142 select HAVE_MOVE_PUD 143 select HAVE_PCI 144 select HAVE_ACPI_APEI if (ACPI && EFI) 145 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 146 select HAVE_ARCH_AUDITSYSCALL 147 select HAVE_ARCH_BITREVERSE 148 select HAVE_ARCH_COMPILER_H 149 select HAVE_ARCH_HUGE_VMAP 150 select HAVE_ARCH_JUMP_LABEL 151 select HAVE_ARCH_JUMP_LABEL_RELATIVE 152 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 153 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 154 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 155 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 156 # Some instrumentation may be unsound, hence EXPERT 157 select HAVE_ARCH_KCSAN if EXPERT 158 select HAVE_ARCH_KFENCE 159 select HAVE_ARCH_KGDB 160 select HAVE_ARCH_MMAP_RND_BITS 161 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 162 select HAVE_ARCH_PREL32_RELOCATIONS 163 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 164 select HAVE_ARCH_SECCOMP_FILTER 165 select HAVE_ARCH_STACKLEAK 166 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 167 select HAVE_ARCH_TRACEHOOK 168 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 169 select HAVE_ARCH_VMAP_STACK 170 select HAVE_ARM_SMCCC 171 select HAVE_ASM_MODVERSIONS 172 select HAVE_EBPF_JIT 173 select HAVE_C_RECORDMCOUNT 174 select HAVE_CMPXCHG_DOUBLE 175 select HAVE_CMPXCHG_LOCAL 176 select HAVE_CONTEXT_TRACKING 177 select HAVE_DEBUG_KMEMLEAK 178 select HAVE_DMA_CONTIGUOUS 179 select HAVE_DYNAMIC_FTRACE 180 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 181 if DYNAMIC_FTRACE_WITH_REGS 182 select HAVE_EFFICIENT_UNALIGNED_ACCESS 183 select HAVE_FAST_GUP 184 select HAVE_FTRACE_MCOUNT_RECORD 185 select HAVE_FUNCTION_TRACER 186 select HAVE_FUNCTION_ERROR_INJECTION 187 select HAVE_FUNCTION_GRAPH_TRACER 188 select HAVE_GCC_PLUGINS 189 select HAVE_HW_BREAKPOINT if PERF_EVENTS 190 select HAVE_IRQ_TIME_ACCOUNTING 191 select HAVE_KVM 192 select HAVE_NMI 193 select HAVE_PATA_PLATFORM 194 select HAVE_PERF_EVENTS 195 select HAVE_PERF_REGS 196 select HAVE_PERF_USER_STACK_DUMP 197 select HAVE_PREEMPT_DYNAMIC_KEY 198 select HAVE_REGS_AND_STACK_ACCESS_API 199 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 200 select HAVE_FUNCTION_ARG_ACCESS_API 201 select MMU_GATHER_RCU_TABLE_FREE 202 select HAVE_RSEQ 203 select HAVE_STACKPROTECTOR 204 select HAVE_SYSCALL_TRACEPOINTS 205 select HAVE_KPROBES 206 select HAVE_KRETPROBES 207 select HAVE_GENERIC_VDSO 208 select IOMMU_DMA if IOMMU_SUPPORT 209 select IRQ_DOMAIN 210 select IRQ_FORCED_THREADING 211 select KASAN_VMALLOC if KASAN 212 select MODULES_USE_ELF_RELA 213 select NEED_DMA_MAP_STATE 214 select NEED_SG_DMA_LENGTH 215 select OF 216 select OF_EARLY_FLATTREE 217 select PCI_DOMAINS_GENERIC if PCI 218 select PCI_ECAM if (ACPI && PCI) 219 select PCI_SYSCALL if PCI 220 select POWER_RESET 221 select POWER_SUPPLY 222 select SPARSE_IRQ 223 select SWIOTLB 224 select SYSCTL_EXCEPTION_TRACE 225 select THREAD_INFO_IN_TASK 226 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 227 select TRACE_IRQFLAGS_SUPPORT 228 help 229 ARM 64-bit (AArch64) Linux support. 230 231config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 232 def_bool CC_IS_CLANG 233 # https://github.com/ClangBuiltLinux/linux/issues/1507 234 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 235 select HAVE_DYNAMIC_FTRACE_WITH_REGS 236 237config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 238 def_bool CC_IS_GCC 239 depends on $(cc-option,-fpatchable-function-entry=2) 240 select HAVE_DYNAMIC_FTRACE_WITH_REGS 241 242config 64BIT 243 def_bool y 244 245config MMU 246 def_bool y 247 248config ARM64_PAGE_SHIFT 249 int 250 default 16 if ARM64_64K_PAGES 251 default 14 if ARM64_16K_PAGES 252 default 12 253 254config ARM64_CONT_PTE_SHIFT 255 int 256 default 5 if ARM64_64K_PAGES 257 default 7 if ARM64_16K_PAGES 258 default 4 259 260config ARM64_CONT_PMD_SHIFT 261 int 262 default 5 if ARM64_64K_PAGES 263 default 5 if ARM64_16K_PAGES 264 default 4 265 266config ARCH_MMAP_RND_BITS_MIN 267 default 14 if ARM64_64K_PAGES 268 default 16 if ARM64_16K_PAGES 269 default 18 270 271# max bits determined by the following formula: 272# VA_BITS - PAGE_SHIFT - 3 273config ARCH_MMAP_RND_BITS_MAX 274 default 19 if ARM64_VA_BITS=36 275 default 24 if ARM64_VA_BITS=39 276 default 27 if ARM64_VA_BITS=42 277 default 30 if ARM64_VA_BITS=47 278 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 279 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 280 default 33 if ARM64_VA_BITS=48 281 default 14 if ARM64_64K_PAGES 282 default 16 if ARM64_16K_PAGES 283 default 18 284 285config ARCH_MMAP_RND_COMPAT_BITS_MIN 286 default 7 if ARM64_64K_PAGES 287 default 9 if ARM64_16K_PAGES 288 default 11 289 290config ARCH_MMAP_RND_COMPAT_BITS_MAX 291 default 16 292 293config NO_IOPORT_MAP 294 def_bool y if !PCI 295 296config STACKTRACE_SUPPORT 297 def_bool y 298 299config ILLEGAL_POINTER_VALUE 300 hex 301 default 0xdead000000000000 302 303config LOCKDEP_SUPPORT 304 def_bool y 305 306config GENERIC_BUG 307 def_bool y 308 depends on BUG 309 310config GENERIC_BUG_RELATIVE_POINTERS 311 def_bool y 312 depends on GENERIC_BUG 313 314config GENERIC_HWEIGHT 315 def_bool y 316 317config GENERIC_CSUM 318 def_bool y 319 320config GENERIC_CALIBRATE_DELAY 321 def_bool y 322 323config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 324 def_bool y 325 326config SMP 327 def_bool y 328 329config KERNEL_MODE_NEON 330 def_bool y 331 332config FIX_EARLYCON_MEM 333 def_bool y 334 335config PGTABLE_LEVELS 336 int 337 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 338 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 339 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 340 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 341 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 342 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 343 344config ARCH_SUPPORTS_UPROBES 345 def_bool y 346 347config ARCH_PROC_KCORE_TEXT 348 def_bool y 349 350config BROKEN_GAS_INST 351 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 352 353config KASAN_SHADOW_OFFSET 354 hex 355 depends on KASAN_GENERIC || KASAN_SW_TAGS 356 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 357 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 358 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 359 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 360 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 361 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 362 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 363 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 364 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 365 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 366 default 0xffffffffffffffff 367 368source "arch/arm64/Kconfig.platforms" 369 370menu "Kernel Features" 371 372menu "ARM errata workarounds via the alternatives framework" 373 374config ARM64_WORKAROUND_CLEAN_CACHE 375 bool 376 377config ARM64_ERRATUM_826319 378 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 379 default y 380 select ARM64_WORKAROUND_CLEAN_CACHE 381 help 382 This option adds an alternative code sequence to work around ARM 383 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 384 AXI master interface and an L2 cache. 385 386 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 387 and is unable to accept a certain write via this interface, it will 388 not progress on read data presented on the read data channel and the 389 system can deadlock. 390 391 The workaround promotes data cache clean instructions to 392 data cache clean-and-invalidate. 393 Please note that this does not necessarily enable the workaround, 394 as it depends on the alternative framework, which will only patch 395 the kernel if an affected CPU is detected. 396 397 If unsure, say Y. 398 399config ARM64_ERRATUM_827319 400 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 401 default y 402 select ARM64_WORKAROUND_CLEAN_CACHE 403 help 404 This option adds an alternative code sequence to work around ARM 405 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 406 master interface and an L2 cache. 407 408 Under certain conditions this erratum can cause a clean line eviction 409 to occur at the same time as another transaction to the same address 410 on the AMBA 5 CHI interface, which can cause data corruption if the 411 interconnect reorders the two transactions. 412 413 The workaround promotes data cache clean instructions to 414 data cache clean-and-invalidate. 415 Please note that this does not necessarily enable the workaround, 416 as it depends on the alternative framework, which will only patch 417 the kernel if an affected CPU is detected. 418 419 If unsure, say Y. 420 421config ARM64_ERRATUM_824069 422 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 423 default y 424 select ARM64_WORKAROUND_CLEAN_CACHE 425 help 426 This option adds an alternative code sequence to work around ARM 427 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 428 to a coherent interconnect. 429 430 If a Cortex-A53 processor is executing a store or prefetch for 431 write instruction at the same time as a processor in another 432 cluster is executing a cache maintenance operation to the same 433 address, then this erratum might cause a clean cache line to be 434 incorrectly marked as dirty. 435 436 The workaround promotes data cache clean instructions to 437 data cache clean-and-invalidate. 438 Please note that this option does not necessarily enable the 439 workaround, as it depends on the alternative framework, which will 440 only patch the kernel if an affected CPU is detected. 441 442 If unsure, say Y. 443 444config ARM64_ERRATUM_819472 445 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 446 default y 447 select ARM64_WORKAROUND_CLEAN_CACHE 448 help 449 This option adds an alternative code sequence to work around ARM 450 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 451 present when it is connected to a coherent interconnect. 452 453 If the processor is executing a load and store exclusive sequence at 454 the same time as a processor in another cluster is executing a cache 455 maintenance operation to the same address, then this erratum might 456 cause data corruption. 457 458 The workaround promotes data cache clean instructions to 459 data cache clean-and-invalidate. 460 Please note that this does not necessarily enable the workaround, 461 as it depends on the alternative framework, which will only patch 462 the kernel if an affected CPU is detected. 463 464 If unsure, say Y. 465 466config ARM64_ERRATUM_832075 467 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 468 default y 469 help 470 This option adds an alternative code sequence to work around ARM 471 erratum 832075 on Cortex-A57 parts up to r1p2. 472 473 Affected Cortex-A57 parts might deadlock when exclusive load/store 474 instructions to Write-Back memory are mixed with Device loads. 475 476 The workaround is to promote device loads to use Load-Acquire 477 semantics. 478 Please note that this does not necessarily enable the workaround, 479 as it depends on the alternative framework, which will only patch 480 the kernel if an affected CPU is detected. 481 482 If unsure, say Y. 483 484config ARM64_ERRATUM_834220 485 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 486 depends on KVM 487 default y 488 help 489 This option adds an alternative code sequence to work around ARM 490 erratum 834220 on Cortex-A57 parts up to r1p2. 491 492 Affected Cortex-A57 parts might report a Stage 2 translation 493 fault as the result of a Stage 1 fault for load crossing a 494 page boundary when there is a permission or device memory 495 alignment fault at Stage 1 and a translation fault at Stage 2. 496 497 The workaround is to verify that the Stage 1 translation 498 doesn't generate a fault before handling the Stage 2 fault. 499 Please note that this does not necessarily enable the workaround, 500 as it depends on the alternative framework, which will only patch 501 the kernel if an affected CPU is detected. 502 503 If unsure, say Y. 504 505config ARM64_ERRATUM_845719 506 bool "Cortex-A53: 845719: a load might read incorrect data" 507 depends on COMPAT 508 default y 509 help 510 This option adds an alternative code sequence to work around ARM 511 erratum 845719 on Cortex-A53 parts up to r0p4. 512 513 When running a compat (AArch32) userspace on an affected Cortex-A53 514 part, a load at EL0 from a virtual address that matches the bottom 32 515 bits of the virtual address used by a recent load at (AArch64) EL1 516 might return incorrect data. 517 518 The workaround is to write the contextidr_el1 register on exception 519 return to a 32-bit task. 520 Please note that this does not necessarily enable the workaround, 521 as it depends on the alternative framework, which will only patch 522 the kernel if an affected CPU is detected. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_843419 527 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 528 default y 529 select ARM64_MODULE_PLTS if MODULES 530 help 531 This option links the kernel with '--fix-cortex-a53-843419' and 532 enables PLT support to replace certain ADRP instructions, which can 533 cause subsequent memory accesses to use an incorrect address on 534 Cortex-A53 parts up to r0p4. 535 536 If unsure, say Y. 537 538config ARM64_LD_HAS_FIX_ERRATUM_843419 539 def_bool $(ld-option,--fix-cortex-a53-843419) 540 541config ARM64_ERRATUM_1024718 542 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 543 default y 544 help 545 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 546 547 Affected Cortex-A55 cores (all revisions) could cause incorrect 548 update of the hardware dirty bit when the DBM/AP bits are updated 549 without a break-before-make. The workaround is to disable the usage 550 of hardware DBM locally on the affected cores. CPUs not affected by 551 this erratum will continue to use the feature. 552 553 If unsure, say Y. 554 555config ARM64_ERRATUM_1418040 556 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 557 default y 558 depends on COMPAT 559 help 560 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 561 errata 1188873 and 1418040. 562 563 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 564 cause register corruption when accessing the timer registers 565 from AArch32 userspace. 566 567 If unsure, say Y. 568 569config ARM64_WORKAROUND_SPECULATIVE_AT 570 bool 571 572config ARM64_ERRATUM_1165522 573 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 574 default y 575 select ARM64_WORKAROUND_SPECULATIVE_AT 576 help 577 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 578 579 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 580 corrupted TLBs by speculating an AT instruction during a guest 581 context switch. 582 583 If unsure, say Y. 584 585config ARM64_ERRATUM_1319367 586 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 587 default y 588 select ARM64_WORKAROUND_SPECULATIVE_AT 589 help 590 This option adds work arounds for ARM Cortex-A57 erratum 1319537 591 and A72 erratum 1319367 592 593 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 594 speculating an AT instruction during a guest context switch. 595 596 If unsure, say Y. 597 598config ARM64_ERRATUM_1530923 599 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 600 default y 601 select ARM64_WORKAROUND_SPECULATIVE_AT 602 help 603 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 604 605 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 606 corrupted TLBs by speculating an AT instruction during a guest 607 context switch. 608 609 If unsure, say Y. 610 611config ARM64_WORKAROUND_REPEAT_TLBI 612 bool 613 614config ARM64_ERRATUM_1286807 615 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 616 default y 617 select ARM64_WORKAROUND_REPEAT_TLBI 618 help 619 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 620 621 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 622 address for a cacheable mapping of a location is being 623 accessed by a core while another core is remapping the virtual 624 address to a new physical page using the recommended 625 break-before-make sequence, then under very rare circumstances 626 TLBI+DSB completes before a read using the translation being 627 invalidated has been observed by other observers. The 628 workaround repeats the TLBI+DSB operation. 629 630config ARM64_ERRATUM_1463225 631 bool "Cortex-A76: Software Step might prevent interrupt recognition" 632 default y 633 help 634 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 635 636 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 637 of a system call instruction (SVC) can prevent recognition of 638 subsequent interrupts when software stepping is disabled in the 639 exception handler of the system call and either kernel debugging 640 is enabled or VHE is in use. 641 642 Work around the erratum by triggering a dummy step exception 643 when handling a system call from a task that is being stepped 644 in a VHE configuration of the kernel. 645 646 If unsure, say Y. 647 648config ARM64_ERRATUM_1542419 649 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 650 default y 651 help 652 This option adds a workaround for ARM Neoverse-N1 erratum 653 1542419. 654 655 Affected Neoverse-N1 cores could execute a stale instruction when 656 modified by another CPU. The workaround depends on a firmware 657 counterpart. 658 659 Workaround the issue by hiding the DIC feature from EL0. This 660 forces user-space to perform cache maintenance. 661 662 If unsure, say Y. 663 664config ARM64_ERRATUM_1508412 665 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 666 default y 667 help 668 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 669 670 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 671 of a store-exclusive or read of PAR_EL1 and a load with device or 672 non-cacheable memory attributes. The workaround depends on a firmware 673 counterpart. 674 675 KVM guests must also have the workaround implemented or they can 676 deadlock the system. 677 678 Work around the issue by inserting DMB SY barriers around PAR_EL1 679 register reads and warning KVM users. The DMB barrier is sufficient 680 to prevent a speculative PAR_EL1 read. 681 682 If unsure, say Y. 683 684config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 685 bool 686 687config ARM64_ERRATUM_2051678 688 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 689 default y 690 help 691 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 692 Affected Cortex-A510 might not respect the ordering rules for 693 hardware update of the page table's dirty bit. The workaround 694 is to not enable the feature on affected CPUs. 695 696 If unsure, say Y. 697 698config ARM64_ERRATUM_2077057 699 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 700 default y 701 help 702 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 703 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 704 expected, but a Pointer Authentication trap is taken instead. The 705 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 706 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 707 708 This can only happen when EL2 is stepping EL1. 709 710 When these conditions occur, the SPSR_EL2 value is unchanged from the 711 previous guest entry, and can be restored from the in-memory copy. 712 713 If unsure, say Y. 714 715config ARM64_ERRATUM_2119858 716 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 717 default y 718 depends on CORESIGHT_TRBE 719 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 720 help 721 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 722 723 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 724 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 725 the event of a WRAP event. 726 727 Work around the issue by always making sure we move the TRBPTR_EL1 by 728 256 bytes before enabling the buffer and filling the first 256 bytes of 729 the buffer with ETM ignore packets upon disabling. 730 731 If unsure, say Y. 732 733config ARM64_ERRATUM_2139208 734 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 735 default y 736 depends on CORESIGHT_TRBE 737 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 738 help 739 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 740 741 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 742 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 743 the event of a WRAP event. 744 745 Work around the issue by always making sure we move the TRBPTR_EL1 by 746 256 bytes before enabling the buffer and filling the first 256 bytes of 747 the buffer with ETM ignore packets upon disabling. 748 749 If unsure, say Y. 750 751config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 752 bool 753 754config ARM64_ERRATUM_2054223 755 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 756 default y 757 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 758 help 759 Enable workaround for ARM Cortex-A710 erratum 2054223 760 761 Affected cores may fail to flush the trace data on a TSB instruction, when 762 the PE is in trace prohibited state. This will cause losing a few bytes 763 of the trace cached. 764 765 Workaround is to issue two TSB consecutively on affected cores. 766 767 If unsure, say Y. 768 769config ARM64_ERRATUM_2067961 770 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 771 default y 772 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 773 help 774 Enable workaround for ARM Neoverse-N2 erratum 2067961 775 776 Affected cores may fail to flush the trace data on a TSB instruction, when 777 the PE is in trace prohibited state. This will cause losing a few bytes 778 of the trace cached. 779 780 Workaround is to issue two TSB consecutively on affected cores. 781 782 If unsure, say Y. 783 784config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 785 bool 786 787config ARM64_ERRATUM_2253138 788 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 789 depends on CORESIGHT_TRBE 790 default y 791 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 792 help 793 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 794 795 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 796 for TRBE. Under some conditions, the TRBE might generate a write to the next 797 virtually addressed page following the last page of the TRBE address space 798 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 799 800 Work around this in the driver by always making sure that there is a 801 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 802 803 If unsure, say Y. 804 805config ARM64_ERRATUM_2224489 806 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 807 depends on CORESIGHT_TRBE 808 default y 809 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 810 help 811 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 812 813 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 814 for TRBE. Under some conditions, the TRBE might generate a write to the next 815 virtually addressed page following the last page of the TRBE address space 816 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 817 818 Work around this in the driver by always making sure that there is a 819 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 820 821 If unsure, say Y. 822 823config ARM64_ERRATUM_2064142 824 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 825 depends on CORESIGHT_TRBE 826 default y 827 help 828 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 829 830 Affected Cortex-A510 core might fail to write into system registers after the 831 TRBE has been disabled. Under some conditions after the TRBE has been disabled 832 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 833 and TRBTRG_EL1 will be ignored and will not be effected. 834 835 Work around this in the driver by executing TSB CSYNC and DSB after collection 836 is stopped and before performing a system register write to one of the affected 837 registers. 838 839 If unsure, say Y. 840 841config ARM64_ERRATUM_2038923 842 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 843 depends on CORESIGHT_TRBE 844 default y 845 help 846 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 847 848 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 849 prohibited within the CPU. As a result, the trace buffer or trace buffer state 850 might be corrupted. This happens after TRBE buffer has been enabled by setting 851 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 852 execution changes from a context, in which trace is prohibited to one where it 853 isn't, or vice versa. In these mentioned conditions, the view of whether trace 854 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 855 the trace buffer state might be corrupted. 856 857 Work around this in the driver by preventing an inconsistent view of whether the 858 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 859 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 860 two ISB instructions if no ERET is to take place. 861 862 If unsure, say Y. 863 864config ARM64_ERRATUM_1902691 865 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 866 depends on CORESIGHT_TRBE 867 default y 868 help 869 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 870 871 Affected Cortex-A510 core might cause trace data corruption, when being written 872 into the memory. Effectively TRBE is broken and hence cannot be used to capture 873 trace data. 874 875 Work around this problem in the driver by just preventing TRBE initialization on 876 affected cpus. The firmware must have disabled the access to TRBE for the kernel 877 on such implementations. This will cover the kernel for any firmware that doesn't 878 do this already. 879 880 If unsure, say Y. 881 882config CAVIUM_ERRATUM_22375 883 bool "Cavium erratum 22375, 24313" 884 default y 885 help 886 Enable workaround for errata 22375 and 24313. 887 888 This implements two gicv3-its errata workarounds for ThunderX. Both 889 with a small impact affecting only ITS table allocation. 890 891 erratum 22375: only alloc 8MB table size 892 erratum 24313: ignore memory access type 893 894 The fixes are in ITS initialization and basically ignore memory access 895 type and table size provided by the TYPER and BASER registers. 896 897 If unsure, say Y. 898 899config CAVIUM_ERRATUM_23144 900 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 901 depends on NUMA 902 default y 903 help 904 ITS SYNC command hang for cross node io and collections/cpu mapping. 905 906 If unsure, say Y. 907 908config CAVIUM_ERRATUM_23154 909 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 910 default y 911 help 912 The ThunderX GICv3 implementation requires a modified version for 913 reading the IAR status to ensure data synchronization 914 (access to icc_iar1_el1 is not sync'ed before and after). 915 916 It also suffers from erratum 38545 (also present on Marvell's 917 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 918 spuriously presented to the CPU interface. 919 920 If unsure, say Y. 921 922config CAVIUM_ERRATUM_27456 923 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 924 default y 925 help 926 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 927 instructions may cause the icache to become corrupted if it 928 contains data for a non-current ASID. The fix is to 929 invalidate the icache when changing the mm context. 930 931 If unsure, say Y. 932 933config CAVIUM_ERRATUM_30115 934 bool "Cavium erratum 30115: Guest may disable interrupts in host" 935 default y 936 help 937 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 938 1.2, and T83 Pass 1.0, KVM guest execution may disable 939 interrupts in host. Trapping both GICv3 group-0 and group-1 940 accesses sidesteps the issue. 941 942 If unsure, say Y. 943 944config CAVIUM_TX2_ERRATUM_219 945 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 946 default y 947 help 948 On Cavium ThunderX2, a load, store or prefetch instruction between a 949 TTBR update and the corresponding context synchronizing operation can 950 cause a spurious Data Abort to be delivered to any hardware thread in 951 the CPU core. 952 953 Work around the issue by avoiding the problematic code sequence and 954 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 955 trap handler performs the corresponding register access, skips the 956 instruction and ensures context synchronization by virtue of the 957 exception return. 958 959 If unsure, say Y. 960 961config FUJITSU_ERRATUM_010001 962 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 963 default y 964 help 965 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 966 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 967 accesses may cause undefined fault (Data abort, DFSC=0b111111). 968 This fault occurs under a specific hardware condition when a 969 load/store instruction performs an address translation using: 970 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 971 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 972 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 973 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 974 975 The workaround is to ensure these bits are clear in TCR_ELx. 976 The workaround only affects the Fujitsu-A64FX. 977 978 If unsure, say Y. 979 980config HISILICON_ERRATUM_161600802 981 bool "Hip07 161600802: Erroneous redistributor VLPI base" 982 default y 983 help 984 The HiSilicon Hip07 SoC uses the wrong redistributor base 985 when issued ITS commands such as VMOVP and VMAPP, and requires 986 a 128kB offset to be applied to the target address in this commands. 987 988 If unsure, say Y. 989 990config QCOM_FALKOR_ERRATUM_1003 991 bool "Falkor E1003: Incorrect translation due to ASID change" 992 default y 993 help 994 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 995 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 996 in TTBR1_EL1, this situation only occurs in the entry trampoline and 997 then only for entries in the walk cache, since the leaf translation 998 is unchanged. Work around the erratum by invalidating the walk cache 999 entries for the trampoline before entering the kernel proper. 1000 1001config QCOM_FALKOR_ERRATUM_1009 1002 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1003 default y 1004 select ARM64_WORKAROUND_REPEAT_TLBI 1005 help 1006 On Falkor v1, the CPU may prematurely complete a DSB following a 1007 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1008 one more time to fix the issue. 1009 1010 If unsure, say Y. 1011 1012config QCOM_QDF2400_ERRATUM_0065 1013 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1014 default y 1015 help 1016 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1017 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1018 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1019 1020 If unsure, say Y. 1021 1022config QCOM_FALKOR_ERRATUM_E1041 1023 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1024 default y 1025 help 1026 Falkor CPU may speculatively fetch instructions from an improper 1027 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1028 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1029 1030 If unsure, say Y. 1031 1032config NVIDIA_CARMEL_CNP_ERRATUM 1033 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1034 default y 1035 help 1036 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1037 invalidate shared TLB entries installed by a different core, as it would 1038 on standard ARM cores. 1039 1040 If unsure, say Y. 1041 1042config SOCIONEXT_SYNQUACER_PREITS 1043 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1044 default y 1045 help 1046 Socionext Synquacer SoCs implement a separate h/w block to generate 1047 MSI doorbell writes with non-zero values for the device ID. 1048 1049 If unsure, say Y. 1050 1051endmenu 1052 1053 1054choice 1055 prompt "Page size" 1056 default ARM64_4K_PAGES 1057 help 1058 Page size (translation granule) configuration. 1059 1060config ARM64_4K_PAGES 1061 bool "4KB" 1062 help 1063 This feature enables 4KB pages support. 1064 1065config ARM64_16K_PAGES 1066 bool "16KB" 1067 help 1068 The system will use 16KB pages support. AArch32 emulation 1069 requires applications compiled with 16K (or a multiple of 16K) 1070 aligned segments. 1071 1072config ARM64_64K_PAGES 1073 bool "64KB" 1074 help 1075 This feature enables 64KB pages support (4KB by default) 1076 allowing only two levels of page tables and faster TLB 1077 look-up. AArch32 emulation requires applications compiled 1078 with 64K aligned segments. 1079 1080endchoice 1081 1082choice 1083 prompt "Virtual address space size" 1084 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1085 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1086 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1087 help 1088 Allows choosing one of multiple possible virtual address 1089 space sizes. The level of translation table is determined by 1090 a combination of page size and virtual address space size. 1091 1092config ARM64_VA_BITS_36 1093 bool "36-bit" if EXPERT 1094 depends on ARM64_16K_PAGES 1095 1096config ARM64_VA_BITS_39 1097 bool "39-bit" 1098 depends on ARM64_4K_PAGES 1099 1100config ARM64_VA_BITS_42 1101 bool "42-bit" 1102 depends on ARM64_64K_PAGES 1103 1104config ARM64_VA_BITS_47 1105 bool "47-bit" 1106 depends on ARM64_16K_PAGES 1107 1108config ARM64_VA_BITS_48 1109 bool "48-bit" 1110 1111config ARM64_VA_BITS_52 1112 bool "52-bit" 1113 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1114 help 1115 Enable 52-bit virtual addressing for userspace when explicitly 1116 requested via a hint to mmap(). The kernel will also use 52-bit 1117 virtual addresses for its own mappings (provided HW support for 1118 this feature is available, otherwise it reverts to 48-bit). 1119 1120 NOTE: Enabling 52-bit virtual addressing in conjunction with 1121 ARMv8.3 Pointer Authentication will result in the PAC being 1122 reduced from 7 bits to 3 bits, which may have a significant 1123 impact on its susceptibility to brute-force attacks. 1124 1125 If unsure, select 48-bit virtual addressing instead. 1126 1127endchoice 1128 1129config ARM64_FORCE_52BIT 1130 bool "Force 52-bit virtual addresses for userspace" 1131 depends on ARM64_VA_BITS_52 && EXPERT 1132 help 1133 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1134 to maintain compatibility with older software by providing 48-bit VAs 1135 unless a hint is supplied to mmap. 1136 1137 This configuration option disables the 48-bit compatibility logic, and 1138 forces all userspace addresses to be 52-bit on HW that supports it. One 1139 should only enable this configuration option for stress testing userspace 1140 memory management code. If unsure say N here. 1141 1142config ARM64_VA_BITS 1143 int 1144 default 36 if ARM64_VA_BITS_36 1145 default 39 if ARM64_VA_BITS_39 1146 default 42 if ARM64_VA_BITS_42 1147 default 47 if ARM64_VA_BITS_47 1148 default 48 if ARM64_VA_BITS_48 1149 default 52 if ARM64_VA_BITS_52 1150 1151choice 1152 prompt "Physical address space size" 1153 default ARM64_PA_BITS_48 1154 help 1155 Choose the maximum physical address range that the kernel will 1156 support. 1157 1158config ARM64_PA_BITS_48 1159 bool "48-bit" 1160 1161config ARM64_PA_BITS_52 1162 bool "52-bit (ARMv8.2)" 1163 depends on ARM64_64K_PAGES 1164 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1165 help 1166 Enable support for a 52-bit physical address space, introduced as 1167 part of the ARMv8.2-LPA extension. 1168 1169 With this enabled, the kernel will also continue to work on CPUs that 1170 do not support ARMv8.2-LPA, but with some added memory overhead (and 1171 minor performance overhead). 1172 1173endchoice 1174 1175config ARM64_PA_BITS 1176 int 1177 default 48 if ARM64_PA_BITS_48 1178 default 52 if ARM64_PA_BITS_52 1179 1180choice 1181 prompt "Endianness" 1182 default CPU_LITTLE_ENDIAN 1183 help 1184 Select the endianness of data accesses performed by the CPU. Userspace 1185 applications will need to be compiled and linked for the endianness 1186 that is selected here. 1187 1188config CPU_BIG_ENDIAN 1189 bool "Build big-endian kernel" 1190 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1191 help 1192 Say Y if you plan on running a kernel with a big-endian userspace. 1193 1194config CPU_LITTLE_ENDIAN 1195 bool "Build little-endian kernel" 1196 help 1197 Say Y if you plan on running a kernel with a little-endian userspace. 1198 This is usually the case for distributions targeting arm64. 1199 1200endchoice 1201 1202config SCHED_MC 1203 bool "Multi-core scheduler support" 1204 help 1205 Multi-core scheduler support improves the CPU scheduler's decision 1206 making when dealing with multi-core CPU chips at a cost of slightly 1207 increased overhead in some places. If unsure say N here. 1208 1209config SCHED_CLUSTER 1210 bool "Cluster scheduler support" 1211 help 1212 Cluster scheduler support improves the CPU scheduler's decision 1213 making when dealing with machines that have clusters of CPUs. 1214 Cluster usually means a couple of CPUs which are placed closely 1215 by sharing mid-level caches, last-level cache tags or internal 1216 busses. 1217 1218config SCHED_SMT 1219 bool "SMT scheduler support" 1220 help 1221 Improves the CPU scheduler's decision making when dealing with 1222 MultiThreading at a cost of slightly increased overhead in some 1223 places. If unsure say N here. 1224 1225config NR_CPUS 1226 int "Maximum number of CPUs (2-4096)" 1227 range 2 4096 1228 default "256" 1229 1230config HOTPLUG_CPU 1231 bool "Support for hot-pluggable CPUs" 1232 select GENERIC_IRQ_MIGRATION 1233 help 1234 Say Y here to experiment with turning CPUs off and on. CPUs 1235 can be controlled through /sys/devices/system/cpu. 1236 1237# Common NUMA Features 1238config NUMA 1239 bool "NUMA Memory Allocation and Scheduler Support" 1240 select GENERIC_ARCH_NUMA 1241 select ACPI_NUMA if ACPI 1242 select OF_NUMA 1243 select HAVE_SETUP_PER_CPU_AREA 1244 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1245 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1246 select USE_PERCPU_NUMA_NODE_ID 1247 help 1248 Enable NUMA (Non-Uniform Memory Access) support. 1249 1250 The kernel will try to allocate memory used by a CPU on the 1251 local memory of the CPU and add some more 1252 NUMA awareness to the kernel. 1253 1254config NODES_SHIFT 1255 int "Maximum NUMA Nodes (as a power of 2)" 1256 range 1 10 1257 default "4" 1258 depends on NUMA 1259 help 1260 Specify the maximum number of NUMA Nodes available on the target 1261 system. Increases memory reserved to accommodate various tables. 1262 1263source "kernel/Kconfig.hz" 1264 1265config ARCH_SPARSEMEM_ENABLE 1266 def_bool y 1267 select SPARSEMEM_VMEMMAP_ENABLE 1268 select SPARSEMEM_VMEMMAP 1269 1270config HW_PERF_EVENTS 1271 def_bool y 1272 depends on ARM_PMU 1273 1274# Supported by clang >= 7.0 or GCC >= 12.0.0 1275config CC_HAVE_SHADOW_CALL_STACK 1276 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1277 1278config PARAVIRT 1279 bool "Enable paravirtualization code" 1280 help 1281 This changes the kernel so it can modify itself when it is run 1282 under a hypervisor, potentially improving performance significantly 1283 over full virtualization. 1284 1285config PARAVIRT_TIME_ACCOUNTING 1286 bool "Paravirtual steal time accounting" 1287 select PARAVIRT 1288 help 1289 Select this option to enable fine granularity task steal time 1290 accounting. Time spent executing other tasks in parallel with 1291 the current vCPU is discounted from the vCPU power. To account for 1292 that, there can be a small performance impact. 1293 1294 If in doubt, say N here. 1295 1296config KEXEC 1297 depends on PM_SLEEP_SMP 1298 select KEXEC_CORE 1299 bool "kexec system call" 1300 help 1301 kexec is a system call that implements the ability to shutdown your 1302 current kernel, and to start another kernel. It is like a reboot 1303 but it is independent of the system firmware. And like a reboot 1304 you can start any kernel with it, not just Linux. 1305 1306config KEXEC_FILE 1307 bool "kexec file based system call" 1308 select KEXEC_CORE 1309 select HAVE_IMA_KEXEC if IMA 1310 help 1311 This is new version of kexec system call. This system call is 1312 file based and takes file descriptors as system call argument 1313 for kernel and initramfs as opposed to list of segments as 1314 accepted by previous system call. 1315 1316config KEXEC_SIG 1317 bool "Verify kernel signature during kexec_file_load() syscall" 1318 depends on KEXEC_FILE 1319 help 1320 Select this option to verify a signature with loaded kernel 1321 image. If configured, any attempt of loading a image without 1322 valid signature will fail. 1323 1324 In addition to that option, you need to enable signature 1325 verification for the corresponding kernel image type being 1326 loaded in order for this to work. 1327 1328config KEXEC_IMAGE_VERIFY_SIG 1329 bool "Enable Image signature verification support" 1330 default y 1331 depends on KEXEC_SIG 1332 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1333 help 1334 Enable Image signature verification support. 1335 1336comment "Support for PE file signature verification disabled" 1337 depends on KEXEC_SIG 1338 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1339 1340config CRASH_DUMP 1341 bool "Build kdump crash kernel" 1342 help 1343 Generate crash dump after being started by kexec. This should 1344 be normally only set in special crash dump kernels which are 1345 loaded in the main kernel with kexec-tools into a specially 1346 reserved region and then later executed after a crash by 1347 kdump/kexec. 1348 1349 For more details see Documentation/admin-guide/kdump/kdump.rst 1350 1351config TRANS_TABLE 1352 def_bool y 1353 depends on HIBERNATION || KEXEC_CORE 1354 1355config XEN_DOM0 1356 def_bool y 1357 depends on XEN 1358 1359config XEN 1360 bool "Xen guest support on ARM64" 1361 depends on ARM64 && OF 1362 select SWIOTLB_XEN 1363 select PARAVIRT 1364 help 1365 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1366 1367config FORCE_MAX_ZONEORDER 1368 int 1369 default "14" if ARM64_64K_PAGES 1370 default "12" if ARM64_16K_PAGES 1371 default "11" 1372 help 1373 The kernel memory allocator divides physically contiguous memory 1374 blocks into "zones", where each zone is a power of two number of 1375 pages. This option selects the largest power of two that the kernel 1376 keeps in the memory allocator. If you need to allocate very large 1377 blocks of physically contiguous memory, then you may need to 1378 increase this value. 1379 1380 This config option is actually maximum order plus one. For example, 1381 a value of 11 means that the largest free memory block is 2^10 pages. 1382 1383 We make sure that we can allocate upto a HugePage size for each configuration. 1384 Hence we have : 1385 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1386 1387 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1388 4M allocations matching the default size used by generic code. 1389 1390config UNMAP_KERNEL_AT_EL0 1391 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1392 default y 1393 help 1394 Speculation attacks against some high-performance processors can 1395 be used to bypass MMU permission checks and leak kernel data to 1396 userspace. This can be defended against by unmapping the kernel 1397 when running in userspace, mapping it back in on exception entry 1398 via a trampoline page in the vector table. 1399 1400 If unsure, say Y. 1401 1402config MITIGATE_SPECTRE_BRANCH_HISTORY 1403 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1404 default y 1405 help 1406 Speculation attacks against some high-performance processors can 1407 make use of branch history to influence future speculation. 1408 When taking an exception from user-space, a sequence of branches 1409 or a firmware call overwrites the branch history. 1410 1411config RODATA_FULL_DEFAULT_ENABLED 1412 bool "Apply r/o permissions of VM areas also to their linear aliases" 1413 default y 1414 help 1415 Apply read-only attributes of VM areas to the linear alias of 1416 the backing pages as well. This prevents code or read-only data 1417 from being modified (inadvertently or intentionally) via another 1418 mapping of the same memory page. This additional enhancement can 1419 be turned off at runtime by passing rodata=[off|on] (and turned on 1420 with rodata=full if this option is set to 'n') 1421 1422 This requires the linear region to be mapped down to pages, 1423 which may adversely affect performance in some cases. 1424 1425config ARM64_SW_TTBR0_PAN 1426 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1427 help 1428 Enabling this option prevents the kernel from accessing 1429 user-space memory directly by pointing TTBR0_EL1 to a reserved 1430 zeroed area and reserved ASID. The user access routines 1431 restore the valid TTBR0_EL1 temporarily. 1432 1433config ARM64_TAGGED_ADDR_ABI 1434 bool "Enable the tagged user addresses syscall ABI" 1435 default y 1436 help 1437 When this option is enabled, user applications can opt in to a 1438 relaxed ABI via prctl() allowing tagged addresses to be passed 1439 to system calls as pointer arguments. For details, see 1440 Documentation/arm64/tagged-address-abi.rst. 1441 1442menuconfig COMPAT 1443 bool "Kernel support for 32-bit EL0" 1444 depends on ARM64_4K_PAGES || EXPERT 1445 select HAVE_UID16 1446 select OLD_SIGSUSPEND3 1447 select COMPAT_OLD_SIGACTION 1448 help 1449 This option enables support for a 32-bit EL0 running under a 64-bit 1450 kernel at EL1. AArch32-specific components such as system calls, 1451 the user helper functions, VFP support and the ptrace interface are 1452 handled appropriately by the kernel. 1453 1454 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1455 that you will only be able to execute AArch32 binaries that were compiled 1456 with page size aligned segments. 1457 1458 If you want to execute 32-bit userspace applications, say Y. 1459 1460if COMPAT 1461 1462config KUSER_HELPERS 1463 bool "Enable kuser helpers page for 32-bit applications" 1464 default y 1465 help 1466 Warning: disabling this option may break 32-bit user programs. 1467 1468 Provide kuser helpers to compat tasks. The kernel provides 1469 helper code to userspace in read only form at a fixed location 1470 to allow userspace to be independent of the CPU type fitted to 1471 the system. This permits binaries to be run on ARMv4 through 1472 to ARMv8 without modification. 1473 1474 See Documentation/arm/kernel_user_helpers.rst for details. 1475 1476 However, the fixed address nature of these helpers can be used 1477 by ROP (return orientated programming) authors when creating 1478 exploits. 1479 1480 If all of the binaries and libraries which run on your platform 1481 are built specifically for your platform, and make no use of 1482 these helpers, then you can turn this option off to hinder 1483 such exploits. However, in that case, if a binary or library 1484 relying on those helpers is run, it will not function correctly. 1485 1486 Say N here only if you are absolutely certain that you do not 1487 need these helpers; otherwise, the safe option is to say Y. 1488 1489config COMPAT_VDSO 1490 bool "Enable vDSO for 32-bit applications" 1491 depends on !CPU_BIG_ENDIAN 1492 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1493 select GENERIC_COMPAT_VDSO 1494 default y 1495 help 1496 Place in the process address space of 32-bit applications an 1497 ELF shared object providing fast implementations of gettimeofday 1498 and clock_gettime. 1499 1500 You must have a 32-bit build of glibc 2.22 or later for programs 1501 to seamlessly take advantage of this. 1502 1503config THUMB2_COMPAT_VDSO 1504 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1505 depends on COMPAT_VDSO 1506 default y 1507 help 1508 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1509 otherwise with '-marm'. 1510 1511menuconfig ARMV8_DEPRECATED 1512 bool "Emulate deprecated/obsolete ARMv8 instructions" 1513 depends on SYSCTL 1514 help 1515 Legacy software support may require certain instructions 1516 that have been deprecated or obsoleted in the architecture. 1517 1518 Enable this config to enable selective emulation of these 1519 features. 1520 1521 If unsure, say Y 1522 1523if ARMV8_DEPRECATED 1524 1525config SWP_EMULATION 1526 bool "Emulate SWP/SWPB instructions" 1527 help 1528 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1529 they are always undefined. Say Y here to enable software 1530 emulation of these instructions for userspace using LDXR/STXR. 1531 This feature can be controlled at runtime with the abi.swp 1532 sysctl which is disabled by default. 1533 1534 In some older versions of glibc [<=2.8] SWP is used during futex 1535 trylock() operations with the assumption that the code will not 1536 be preempted. This invalid assumption may be more likely to fail 1537 with SWP emulation enabled, leading to deadlock of the user 1538 application. 1539 1540 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1541 on an external transaction monitoring block called a global 1542 monitor to maintain update atomicity. If your system does not 1543 implement a global monitor, this option can cause programs that 1544 perform SWP operations to uncached memory to deadlock. 1545 1546 If unsure, say Y 1547 1548config CP15_BARRIER_EMULATION 1549 bool "Emulate CP15 Barrier instructions" 1550 help 1551 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1552 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1553 strongly recommended to use the ISB, DSB, and DMB 1554 instructions instead. 1555 1556 Say Y here to enable software emulation of these 1557 instructions for AArch32 userspace code. When this option is 1558 enabled, CP15 barrier usage is traced which can help 1559 identify software that needs updating. This feature can be 1560 controlled at runtime with the abi.cp15_barrier sysctl. 1561 1562 If unsure, say Y 1563 1564config SETEND_EMULATION 1565 bool "Emulate SETEND instruction" 1566 help 1567 The SETEND instruction alters the data-endianness of the 1568 AArch32 EL0, and is deprecated in ARMv8. 1569 1570 Say Y here to enable software emulation of the instruction 1571 for AArch32 userspace code. This feature can be controlled 1572 at runtime with the abi.setend sysctl. 1573 1574 Note: All the cpus on the system must have mixed endian support at EL0 1575 for this feature to be enabled. If a new CPU - which doesn't support mixed 1576 endian - is hotplugged in after this feature has been enabled, there could 1577 be unexpected results in the applications. 1578 1579 If unsure, say Y 1580endif 1581 1582endif 1583 1584menu "ARMv8.1 architectural features" 1585 1586config ARM64_HW_AFDBM 1587 bool "Support for hardware updates of the Access and Dirty page flags" 1588 default y 1589 help 1590 The ARMv8.1 architecture extensions introduce support for 1591 hardware updates of the access and dirty information in page 1592 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1593 capable processors, accesses to pages with PTE_AF cleared will 1594 set this bit instead of raising an access flag fault. 1595 Similarly, writes to read-only pages with the DBM bit set will 1596 clear the read-only bit (AP[2]) instead of raising a 1597 permission fault. 1598 1599 Kernels built with this configuration option enabled continue 1600 to work on pre-ARMv8.1 hardware and the performance impact is 1601 minimal. If unsure, say Y. 1602 1603config ARM64_PAN 1604 bool "Enable support for Privileged Access Never (PAN)" 1605 default y 1606 help 1607 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1608 prevents the kernel or hypervisor from accessing user-space (EL0) 1609 memory directly. 1610 1611 Choosing this option will cause any unprotected (not using 1612 copy_to_user et al) memory access to fail with a permission fault. 1613 1614 The feature is detected at runtime, and will remain as a 'nop' 1615 instruction if the cpu does not implement the feature. 1616 1617config AS_HAS_LDAPR 1618 def_bool $(as-instr,.arch_extension rcpc) 1619 1620config AS_HAS_LSE_ATOMICS 1621 def_bool $(as-instr,.arch_extension lse) 1622 1623config ARM64_LSE_ATOMICS 1624 bool 1625 default ARM64_USE_LSE_ATOMICS 1626 depends on AS_HAS_LSE_ATOMICS 1627 1628config ARM64_USE_LSE_ATOMICS 1629 bool "Atomic instructions" 1630 depends on JUMP_LABEL 1631 default y 1632 help 1633 As part of the Large System Extensions, ARMv8.1 introduces new 1634 atomic instructions that are designed specifically to scale in 1635 very large systems. 1636 1637 Say Y here to make use of these instructions for the in-kernel 1638 atomic routines. This incurs a small overhead on CPUs that do 1639 not support these instructions and requires the kernel to be 1640 built with binutils >= 2.25 in order for the new instructions 1641 to be used. 1642 1643endmenu 1644 1645menu "ARMv8.2 architectural features" 1646 1647config AS_HAS_ARMV8_2 1648 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1649 1650config AS_HAS_SHA3 1651 def_bool $(as-instr,.arch armv8.2-a+sha3) 1652 1653config ARM64_PMEM 1654 bool "Enable support for persistent memory" 1655 select ARCH_HAS_PMEM_API 1656 select ARCH_HAS_UACCESS_FLUSHCACHE 1657 help 1658 Say Y to enable support for the persistent memory API based on the 1659 ARMv8.2 DCPoP feature. 1660 1661 The feature is detected at runtime, and the kernel will use DC CVAC 1662 operations if DC CVAP is not supported (following the behaviour of 1663 DC CVAP itself if the system does not define a point of persistence). 1664 1665config ARM64_RAS_EXTN 1666 bool "Enable support for RAS CPU Extensions" 1667 default y 1668 help 1669 CPUs that support the Reliability, Availability and Serviceability 1670 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1671 errors, classify them and report them to software. 1672 1673 On CPUs with these extensions system software can use additional 1674 barriers to determine if faults are pending and read the 1675 classification from a new set of registers. 1676 1677 Selecting this feature will allow the kernel to use these barriers 1678 and access the new registers if the system supports the extension. 1679 Platform RAS features may additionally depend on firmware support. 1680 1681config ARM64_CNP 1682 bool "Enable support for Common Not Private (CNP) translations" 1683 default y 1684 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1685 help 1686 Common Not Private (CNP) allows translation table entries to 1687 be shared between different PEs in the same inner shareable 1688 domain, so the hardware can use this fact to optimise the 1689 caching of such entries in the TLB. 1690 1691 Selecting this option allows the CNP feature to be detected 1692 at runtime, and does not affect PEs that do not implement 1693 this feature. 1694 1695endmenu 1696 1697menu "ARMv8.3 architectural features" 1698 1699config ARM64_PTR_AUTH 1700 bool "Enable support for pointer authentication" 1701 default y 1702 help 1703 Pointer authentication (part of the ARMv8.3 Extensions) provides 1704 instructions for signing and authenticating pointers against secret 1705 keys, which can be used to mitigate Return Oriented Programming (ROP) 1706 and other attacks. 1707 1708 This option enables these instructions at EL0 (i.e. for userspace). 1709 Choosing this option will cause the kernel to initialise secret keys 1710 for each process at exec() time, with these keys being 1711 context-switched along with the process. 1712 1713 The feature is detected at runtime. If the feature is not present in 1714 hardware it will not be advertised to userspace/KVM guest nor will it 1715 be enabled. 1716 1717 If the feature is present on the boot CPU but not on a late CPU, then 1718 the late CPU will be parked. Also, if the boot CPU does not have 1719 address auth and the late CPU has then the late CPU will still boot 1720 but with the feature disabled. On such a system, this option should 1721 not be selected. 1722 1723config ARM64_PTR_AUTH_KERNEL 1724 bool "Use pointer authentication for kernel" 1725 default y 1726 depends on ARM64_PTR_AUTH 1727 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1728 # Modern compilers insert a .note.gnu.property section note for PAC 1729 # which is only understood by binutils starting with version 2.33.1. 1730 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1731 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1732 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1733 help 1734 If the compiler supports the -mbranch-protection or 1735 -msign-return-address flag (e.g. GCC 7 or later), then this option 1736 will cause the kernel itself to be compiled with return address 1737 protection. In this case, and if the target hardware is known to 1738 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1739 disabled with minimal loss of protection. 1740 1741 This feature works with FUNCTION_GRAPH_TRACER option only if 1742 DYNAMIC_FTRACE_WITH_REGS is enabled. 1743 1744config CC_HAS_BRANCH_PROT_PAC_RET 1745 # GCC 9 or later, clang 8 or later 1746 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1747 1748config CC_HAS_SIGN_RETURN_ADDRESS 1749 # GCC 7, 8 1750 def_bool $(cc-option,-msign-return-address=all) 1751 1752config AS_HAS_PAC 1753 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1754 1755config AS_HAS_CFI_NEGATE_RA_STATE 1756 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1757 1758endmenu 1759 1760menu "ARMv8.4 architectural features" 1761 1762config ARM64_AMU_EXTN 1763 bool "Enable support for the Activity Monitors Unit CPU extension" 1764 default y 1765 help 1766 The activity monitors extension is an optional extension introduced 1767 by the ARMv8.4 CPU architecture. This enables support for version 1 1768 of the activity monitors architecture, AMUv1. 1769 1770 To enable the use of this extension on CPUs that implement it, say Y. 1771 1772 Note that for architectural reasons, firmware _must_ implement AMU 1773 support when running on CPUs that present the activity monitors 1774 extension. The required support is present in: 1775 * Version 1.5 and later of the ARM Trusted Firmware 1776 1777 For kernels that have this configuration enabled but boot with broken 1778 firmware, you may need to say N here until the firmware is fixed. 1779 Otherwise you may experience firmware panics or lockups when 1780 accessing the counter registers. Even if you are not observing these 1781 symptoms, the values returned by the register reads might not 1782 correctly reflect reality. Most commonly, the value read will be 0, 1783 indicating that the counter is not enabled. 1784 1785config AS_HAS_ARMV8_4 1786 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1787 1788config ARM64_TLB_RANGE 1789 bool "Enable support for tlbi range feature" 1790 default y 1791 depends on AS_HAS_ARMV8_4 1792 help 1793 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1794 range of input addresses. 1795 1796 The feature introduces new assembly instructions, and they were 1797 support when binutils >= 2.30. 1798 1799endmenu 1800 1801menu "ARMv8.5 architectural features" 1802 1803config AS_HAS_ARMV8_5 1804 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1805 1806config ARM64_BTI 1807 bool "Branch Target Identification support" 1808 default y 1809 help 1810 Branch Target Identification (part of the ARMv8.5 Extensions) 1811 provides a mechanism to limit the set of locations to which computed 1812 branch instructions such as BR or BLR can jump. 1813 1814 To make use of BTI on CPUs that support it, say Y. 1815 1816 BTI is intended to provide complementary protection to other control 1817 flow integrity protection mechanisms, such as the Pointer 1818 authentication mechanism provided as part of the ARMv8.3 Extensions. 1819 For this reason, it does not make sense to enable this option without 1820 also enabling support for pointer authentication. Thus, when 1821 enabling this option you should also select ARM64_PTR_AUTH=y. 1822 1823 Userspace binaries must also be specifically compiled to make use of 1824 this mechanism. If you say N here or the hardware does not support 1825 BTI, such binaries can still run, but you get no additional 1826 enforcement of branch destinations. 1827 1828config ARM64_BTI_KERNEL 1829 bool "Use Branch Target Identification for kernel" 1830 default y 1831 depends on ARM64_BTI 1832 depends on ARM64_PTR_AUTH_KERNEL 1833 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1834 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1835 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1836 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1837 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1838 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1839 help 1840 Build the kernel with Branch Target Identification annotations 1841 and enable enforcement of this for kernel code. When this option 1842 is enabled and the system supports BTI all kernel code including 1843 modular code must have BTI enabled. 1844 1845config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1846 # GCC 9 or later, clang 8 or later 1847 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1848 1849config ARM64_E0PD 1850 bool "Enable support for E0PD" 1851 default y 1852 help 1853 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1854 that EL0 accesses made via TTBR1 always fault in constant time, 1855 providing similar benefits to KASLR as those provided by KPTI, but 1856 with lower overhead and without disrupting legitimate access to 1857 kernel memory such as SPE. 1858 1859 This option enables E0PD for TTBR1 where available. 1860 1861config ARCH_RANDOM 1862 bool "Enable support for random number generation" 1863 default y 1864 help 1865 Random number generation (part of the ARMv8.5 Extensions) 1866 provides a high bandwidth, cryptographically secure 1867 hardware random number generator. 1868 1869config ARM64_AS_HAS_MTE 1870 # Initial support for MTE went in binutils 2.32.0, checked with 1871 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1872 # as a late addition to the final architecture spec (LDGM/STGM) 1873 # is only supported in the newer 2.32.x and 2.33 binutils 1874 # versions, hence the extra "stgm" instruction check below. 1875 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1876 1877config ARM64_MTE 1878 bool "Memory Tagging Extension support" 1879 default y 1880 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1881 depends on AS_HAS_ARMV8_5 1882 depends on AS_HAS_LSE_ATOMICS 1883 # Required for tag checking in the uaccess routines 1884 depends on ARM64_PAN 1885 select ARCH_USES_HIGH_VMA_FLAGS 1886 help 1887 Memory Tagging (part of the ARMv8.5 Extensions) provides 1888 architectural support for run-time, always-on detection of 1889 various classes of memory error to aid with software debugging 1890 to eliminate vulnerabilities arising from memory-unsafe 1891 languages. 1892 1893 This option enables the support for the Memory Tagging 1894 Extension at EL0 (i.e. for userspace). 1895 1896 Selecting this option allows the feature to be detected at 1897 runtime. Any secondary CPU not implementing this feature will 1898 not be allowed a late bring-up. 1899 1900 Userspace binaries that want to use this feature must 1901 explicitly opt in. The mechanism for the userspace is 1902 described in: 1903 1904 Documentation/arm64/memory-tagging-extension.rst. 1905 1906endmenu 1907 1908menu "ARMv8.7 architectural features" 1909 1910config ARM64_EPAN 1911 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1912 default y 1913 depends on ARM64_PAN 1914 help 1915 Enhanced Privileged Access Never (EPAN) allows Privileged 1916 Access Never to be used with Execute-only mappings. 1917 1918 The feature is detected at runtime, and will remain disabled 1919 if the cpu does not implement the feature. 1920endmenu 1921 1922config ARM64_SVE 1923 bool "ARM Scalable Vector Extension support" 1924 default y 1925 help 1926 The Scalable Vector Extension (SVE) is an extension to the AArch64 1927 execution state which complements and extends the SIMD functionality 1928 of the base architecture to support much larger vectors and to enable 1929 additional vectorisation opportunities. 1930 1931 To enable use of this extension on CPUs that implement it, say Y. 1932 1933 On CPUs that support the SVE2 extensions, this option will enable 1934 those too. 1935 1936 Note that for architectural reasons, firmware _must_ implement SVE 1937 support when running on SVE capable hardware. The required support 1938 is present in: 1939 1940 * version 1.5 and later of the ARM Trusted Firmware 1941 * the AArch64 boot wrapper since commit 5e1261e08abf 1942 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1943 1944 For other firmware implementations, consult the firmware documentation 1945 or vendor. 1946 1947 If you need the kernel to boot on SVE-capable hardware with broken 1948 firmware, you may need to say N here until you get your firmware 1949 fixed. Otherwise, you may experience firmware panics or lockups when 1950 booting the kernel. If unsure and you are not observing these 1951 symptoms, you should assume that it is safe to say Y. 1952 1953config ARM64_MODULE_PLTS 1954 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1955 depends on MODULES 1956 select HAVE_MOD_ARCH_SPECIFIC 1957 help 1958 Allocate PLTs when loading modules so that jumps and calls whose 1959 targets are too far away for their relative offsets to be encoded 1960 in the instructions themselves can be bounced via veneers in the 1961 module's PLT. This allows modules to be allocated in the generic 1962 vmalloc area after the dedicated module memory area has been 1963 exhausted. 1964 1965 When running with address space randomization (KASLR), the module 1966 region itself may be too far away for ordinary relative jumps and 1967 calls, and so in that case, module PLTs are required and cannot be 1968 disabled. 1969 1970 Specific errata workaround(s) might also force module PLTs to be 1971 enabled (ARM64_ERRATUM_843419). 1972 1973config ARM64_PSEUDO_NMI 1974 bool "Support for NMI-like interrupts" 1975 select ARM_GIC_V3 1976 help 1977 Adds support for mimicking Non-Maskable Interrupts through the use of 1978 GIC interrupt priority. This support requires version 3 or later of 1979 ARM GIC. 1980 1981 This high priority configuration for interrupts needs to be 1982 explicitly enabled by setting the kernel parameter 1983 "irqchip.gicv3_pseudo_nmi" to 1. 1984 1985 If unsure, say N 1986 1987if ARM64_PSEUDO_NMI 1988config ARM64_DEBUG_PRIORITY_MASKING 1989 bool "Debug interrupt priority masking" 1990 help 1991 This adds runtime checks to functions enabling/disabling 1992 interrupts when using priority masking. The additional checks verify 1993 the validity of ICC_PMR_EL1 when calling concerned functions. 1994 1995 If unsure, say N 1996endif 1997 1998config RELOCATABLE 1999 bool "Build a relocatable kernel image" if EXPERT 2000 select ARCH_HAS_RELR 2001 default y 2002 help 2003 This builds the kernel as a Position Independent Executable (PIE), 2004 which retains all relocation metadata required to relocate the 2005 kernel binary at runtime to a different virtual address than the 2006 address it was linked at. 2007 Since AArch64 uses the RELA relocation format, this requires a 2008 relocation pass at runtime even if the kernel is loaded at the 2009 same address it was linked at. 2010 2011config RANDOMIZE_BASE 2012 bool "Randomize the address of the kernel image" 2013 select ARM64_MODULE_PLTS if MODULES 2014 select RELOCATABLE 2015 help 2016 Randomizes the virtual address at which the kernel image is 2017 loaded, as a security feature that deters exploit attempts 2018 relying on knowledge of the location of kernel internals. 2019 2020 It is the bootloader's job to provide entropy, by passing a 2021 random u64 value in /chosen/kaslr-seed at kernel entry. 2022 2023 When booting via the UEFI stub, it will invoke the firmware's 2024 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2025 to the kernel proper. In addition, it will randomise the physical 2026 location of the kernel Image as well. 2027 2028 If unsure, say N. 2029 2030config RANDOMIZE_MODULE_REGION_FULL 2031 bool "Randomize the module region over a 2 GB range" 2032 depends on RANDOMIZE_BASE 2033 default y 2034 help 2035 Randomizes the location of the module region inside a 2 GB window 2036 covering the core kernel. This way, it is less likely for modules 2037 to leak information about the location of core kernel data structures 2038 but it does imply that function calls between modules and the core 2039 kernel will need to be resolved via veneers in the module PLT. 2040 2041 When this option is not set, the module region will be randomized over 2042 a limited range that contains the [_stext, _etext] interval of the 2043 core kernel, so branch relocations are almost always in range unless 2044 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2045 particular case of region exhaustion, modules might be able to fall 2046 back to a larger 2GB area. 2047 2048config CC_HAVE_STACKPROTECTOR_SYSREG 2049 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2050 2051config STACKPROTECTOR_PER_TASK 2052 def_bool y 2053 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2054 2055endmenu 2056 2057menu "Boot options" 2058 2059config ARM64_ACPI_PARKING_PROTOCOL 2060 bool "Enable support for the ARM64 ACPI parking protocol" 2061 depends on ACPI 2062 help 2063 Enable support for the ARM64 ACPI parking protocol. If disabled 2064 the kernel will not allow booting through the ARM64 ACPI parking 2065 protocol even if the corresponding data is present in the ACPI 2066 MADT table. 2067 2068config CMDLINE 2069 string "Default kernel command string" 2070 default "" 2071 help 2072 Provide a set of default command-line options at build time by 2073 entering them here. As a minimum, you should specify the the 2074 root device (e.g. root=/dev/nfs). 2075 2076choice 2077 prompt "Kernel command line type" if CMDLINE != "" 2078 default CMDLINE_FROM_BOOTLOADER 2079 help 2080 Choose how the kernel will handle the provided default kernel 2081 command line string. 2082 2083config CMDLINE_FROM_BOOTLOADER 2084 bool "Use bootloader kernel arguments if available" 2085 help 2086 Uses the command-line options passed by the boot loader. If 2087 the boot loader doesn't provide any, the default kernel command 2088 string provided in CMDLINE will be used. 2089 2090config CMDLINE_FORCE 2091 bool "Always use the default kernel command string" 2092 help 2093 Always use the default kernel command string, even if the boot 2094 loader passes other arguments to the kernel. 2095 This is useful if you cannot or don't want to change the 2096 command-line options your boot loader passes to the kernel. 2097 2098endchoice 2099 2100config EFI_STUB 2101 bool 2102 2103config EFI 2104 bool "UEFI runtime support" 2105 depends on OF && !CPU_BIG_ENDIAN 2106 depends on KERNEL_MODE_NEON 2107 select ARCH_SUPPORTS_ACPI 2108 select LIBFDT 2109 select UCS2_STRING 2110 select EFI_PARAMS_FROM_FDT 2111 select EFI_RUNTIME_WRAPPERS 2112 select EFI_STUB 2113 select EFI_GENERIC_STUB 2114 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2115 default y 2116 help 2117 This option provides support for runtime services provided 2118 by UEFI firmware (such as non-volatile variables, realtime 2119 clock, and platform reset). A UEFI stub is also provided to 2120 allow the kernel to be booted as an EFI application. This 2121 is only useful on systems that have UEFI firmware. 2122 2123config DMI 2124 bool "Enable support for SMBIOS (DMI) tables" 2125 depends on EFI 2126 default y 2127 help 2128 This enables SMBIOS/DMI feature for systems. 2129 2130 This option is only useful on systems that have UEFI firmware. 2131 However, even with this option, the resultant kernel should 2132 continue to boot on existing non-UEFI platforms. 2133 2134endmenu 2135 2136config SYSVIPC_COMPAT 2137 def_bool y 2138 depends on COMPAT && SYSVIPC 2139 2140menu "Power management options" 2141 2142source "kernel/power/Kconfig" 2143 2144config ARCH_HIBERNATION_POSSIBLE 2145 def_bool y 2146 depends on CPU_PM 2147 2148config ARCH_HIBERNATION_HEADER 2149 def_bool y 2150 depends on HIBERNATION 2151 2152config ARCH_SUSPEND_POSSIBLE 2153 def_bool y 2154 2155endmenu 2156 2157menu "CPU Power Management" 2158 2159source "drivers/cpuidle/Kconfig" 2160 2161source "drivers/cpufreq/Kconfig" 2162 2163endmenu 2164 2165source "drivers/acpi/Kconfig" 2166 2167source "arch/arm64/kvm/Kconfig" 2168 2169if CRYPTO 2170source "arch/arm64/crypto/Kconfig" 2171endif 2172