1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_STATE 14 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 15 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 16 select ARCH_ENABLE_MEMORY_HOTPLUG 17 select ARCH_ENABLE_MEMORY_HOTREMOVE 18 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 19 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 20 select ARCH_HAS_CACHE_LINE_SIZE 21 select ARCH_HAS_DEBUG_VIRTUAL 22 select ARCH_HAS_DEBUG_VM_PGTABLE 23 select ARCH_HAS_DMA_PREP_COHERENT 24 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 25 select ARCH_HAS_FAST_MULTIPLIER 26 select ARCH_HAS_FORTIFY_SOURCE 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_HAS_GIGANTIC_PAGE 29 select ARCH_HAS_KCOV 30 select ARCH_HAS_KEEPINITRD 31 select ARCH_HAS_MEMBARRIER_SYNC_CORE 32 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 33 select ARCH_HAS_PTE_DEVMAP 34 select ARCH_HAS_PTE_SPECIAL 35 select ARCH_HAS_SETUP_DMA_OPS 36 select ARCH_HAS_SET_DIRECT_MAP 37 select ARCH_HAS_SET_MEMORY 38 select ARCH_STACKWALK 39 select ARCH_HAS_STRICT_KERNEL_RWX 40 select ARCH_HAS_STRICT_MODULE_RWX 41 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 42 select ARCH_HAS_SYNC_DMA_FOR_CPU 43 select ARCH_HAS_SYSCALL_WRAPPER 44 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 45 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 46 select ARCH_HAS_ZONE_DMA_SET if EXPERT 47 select ARCH_HAVE_ELF_PROT 48 select ARCH_HAVE_NMI_SAFE_CMPXCHG 49 select ARCH_INLINE_READ_LOCK if !PREEMPTION 50 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 51 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 52 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 53 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 54 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 55 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 57 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 58 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 59 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 61 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 62 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 63 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 65 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 66 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 67 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 68 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 69 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 71 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 72 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 73 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 75 select ARCH_KEEP_MEMBLOCK 76 select ARCH_USE_CMPXCHG_LOCKREF 77 select ARCH_USE_GNU_PROPERTY 78 select ARCH_USE_MEMTEST 79 select ARCH_USE_QUEUED_RWLOCKS 80 select ARCH_USE_QUEUED_SPINLOCKS 81 select ARCH_USE_SYM_ANNOTATIONS 82 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 83 select ARCH_SUPPORTS_HUGETLBFS 84 select ARCH_SUPPORTS_MEMORY_FAILURE 85 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 86 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 87 select ARCH_SUPPORTS_LTO_CLANG_THIN 88 select ARCH_SUPPORTS_CFI_CLANG 89 select ARCH_SUPPORTS_ATOMIC_RMW 90 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 91 select ARCH_SUPPORTS_NUMA_BALANCING 92 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 93 select ARCH_WANT_DEFAULT_BPF_JIT 94 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 95 select ARCH_WANT_FRAME_POINTERS 96 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 97 select ARCH_WANT_LD_ORPHAN_WARN 98 select ARCH_WANTS_NO_INSTR 99 select ARCH_HAS_UBSAN_SANITIZE_ALL 100 select ARM_AMBA 101 select ARM_ARCH_TIMER 102 select ARM_GIC 103 select AUDIT_ARCH_COMPAT_GENERIC 104 select ARM_GIC_V2M if PCI 105 select ARM_GIC_V3 106 select ARM_GIC_V3_ITS if PCI 107 select ARM_PSCI_FW 108 select BUILDTIME_TABLE_SORT 109 select CLONE_BACKWARDS 110 select COMMON_CLK 111 select CPU_PM if (SUSPEND || CPU_IDLE) 112 select CRC32 113 select DCACHE_WORD_ACCESS 114 select DMA_DIRECT_REMAP 115 select EDAC_SUPPORT 116 select FRAME_POINTER 117 select GENERIC_ALLOCATOR 118 select GENERIC_ARCH_TOPOLOGY 119 select GENERIC_CLOCKEVENTS_BROADCAST 120 select GENERIC_CPU_AUTOPROBE 121 select GENERIC_CPU_VULNERABILITIES 122 select GENERIC_EARLY_IOREMAP 123 select GENERIC_IDLE_POLL_SETUP 124 select GENERIC_IRQ_IPI 125 select GENERIC_IRQ_PROBE 126 select GENERIC_IRQ_SHOW 127 select GENERIC_IRQ_SHOW_LEVEL 128 select GENERIC_LIB_DEVMEM_IS_ALLOWED 129 select GENERIC_PCI_IOMAP 130 select GENERIC_PTDUMP 131 select GENERIC_SCHED_CLOCK 132 select GENERIC_SMP_IDLE_THREAD 133 select GENERIC_TIME_VSYSCALL 134 select GENERIC_GETTIMEOFDAY 135 select GENERIC_VDSO_TIME_NS 136 select HARDIRQS_SW_RESEND 137 select HAVE_MOVE_PMD 138 select HAVE_MOVE_PUD 139 select HAVE_PCI 140 select HAVE_ACPI_APEI if (ACPI && EFI) 141 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 142 select HAVE_ARCH_AUDITSYSCALL 143 select HAVE_ARCH_BITREVERSE 144 select HAVE_ARCH_COMPILER_H 145 select HAVE_ARCH_HUGE_VMAP 146 select HAVE_ARCH_JUMP_LABEL 147 select HAVE_ARCH_JUMP_LABEL_RELATIVE 148 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 149 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 150 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 151 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 152 # Some instrumentation may be unsound, hence EXPERT 153 select HAVE_ARCH_KCSAN if EXPERT 154 select HAVE_ARCH_KFENCE 155 select HAVE_ARCH_KGDB 156 select HAVE_ARCH_MMAP_RND_BITS 157 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 158 select HAVE_ARCH_PREL32_RELOCATIONS 159 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 160 select HAVE_ARCH_SECCOMP_FILTER 161 select HAVE_ARCH_STACKLEAK 162 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 163 select HAVE_ARCH_TRACEHOOK 164 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 165 select HAVE_ARCH_VMAP_STACK 166 select HAVE_ARM_SMCCC 167 select HAVE_ASM_MODVERSIONS 168 select HAVE_EBPF_JIT 169 select HAVE_C_RECORDMCOUNT 170 select HAVE_CMPXCHG_DOUBLE 171 select HAVE_CMPXCHG_LOCAL 172 select HAVE_CONTEXT_TRACKING 173 select HAVE_DEBUG_KMEMLEAK 174 select HAVE_DMA_CONTIGUOUS 175 select HAVE_DYNAMIC_FTRACE 176 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 177 if $(cc-option,-fpatchable-function-entry=2) 178 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 179 if DYNAMIC_FTRACE_WITH_REGS 180 select HAVE_EFFICIENT_UNALIGNED_ACCESS 181 select HAVE_FAST_GUP 182 select HAVE_FTRACE_MCOUNT_RECORD 183 select HAVE_FUNCTION_TRACER 184 select HAVE_FUNCTION_ERROR_INJECTION 185 select HAVE_FUNCTION_GRAPH_TRACER 186 select HAVE_GCC_PLUGINS 187 select HAVE_HW_BREAKPOINT if PERF_EVENTS 188 select HAVE_IRQ_TIME_ACCOUNTING 189 select HAVE_KVM 190 select HAVE_NMI 191 select HAVE_PATA_PLATFORM 192 select HAVE_PERF_EVENTS 193 select HAVE_PERF_REGS 194 select HAVE_PERF_USER_STACK_DUMP 195 select HAVE_REGS_AND_STACK_ACCESS_API 196 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 197 select HAVE_FUNCTION_ARG_ACCESS_API 198 select MMU_GATHER_RCU_TABLE_FREE 199 select HAVE_RSEQ 200 select HAVE_STACKPROTECTOR 201 select HAVE_SYSCALL_TRACEPOINTS 202 select HAVE_KPROBES 203 select HAVE_KRETPROBES 204 select HAVE_GENERIC_VDSO 205 select IOMMU_DMA if IOMMU_SUPPORT 206 select IRQ_DOMAIN 207 select IRQ_FORCED_THREADING 208 select KASAN_VMALLOC if KASAN_GENERIC 209 select MODULES_USE_ELF_RELA 210 select NEED_DMA_MAP_STATE 211 select NEED_SG_DMA_LENGTH 212 select OF 213 select OF_EARLY_FLATTREE 214 select PCI_DOMAINS_GENERIC if PCI 215 select PCI_ECAM if (ACPI && PCI) 216 select PCI_SYSCALL if PCI 217 select POWER_RESET 218 select POWER_SUPPLY 219 select SPARSE_IRQ 220 select SWIOTLB 221 select SYSCTL_EXCEPTION_TRACE 222 select THREAD_INFO_IN_TASK 223 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 224 select TRACE_IRQFLAGS_SUPPORT 225 help 226 ARM 64-bit (AArch64) Linux support. 227 228config 64BIT 229 def_bool y 230 231config MMU 232 def_bool y 233 234config ARM64_PAGE_SHIFT 235 int 236 default 16 if ARM64_64K_PAGES 237 default 14 if ARM64_16K_PAGES 238 default 12 239 240config ARM64_CONT_PTE_SHIFT 241 int 242 default 5 if ARM64_64K_PAGES 243 default 7 if ARM64_16K_PAGES 244 default 4 245 246config ARM64_CONT_PMD_SHIFT 247 int 248 default 5 if ARM64_64K_PAGES 249 default 5 if ARM64_16K_PAGES 250 default 4 251 252config ARCH_MMAP_RND_BITS_MIN 253 default 14 if ARM64_64K_PAGES 254 default 16 if ARM64_16K_PAGES 255 default 18 256 257# max bits determined by the following formula: 258# VA_BITS - PAGE_SHIFT - 3 259config ARCH_MMAP_RND_BITS_MAX 260 default 19 if ARM64_VA_BITS=36 261 default 24 if ARM64_VA_BITS=39 262 default 27 if ARM64_VA_BITS=42 263 default 30 if ARM64_VA_BITS=47 264 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 265 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 266 default 33 if ARM64_VA_BITS=48 267 default 14 if ARM64_64K_PAGES 268 default 16 if ARM64_16K_PAGES 269 default 18 270 271config ARCH_MMAP_RND_COMPAT_BITS_MIN 272 default 7 if ARM64_64K_PAGES 273 default 9 if ARM64_16K_PAGES 274 default 11 275 276config ARCH_MMAP_RND_COMPAT_BITS_MAX 277 default 16 278 279config NO_IOPORT_MAP 280 def_bool y if !PCI 281 282config STACKTRACE_SUPPORT 283 def_bool y 284 285config ILLEGAL_POINTER_VALUE 286 hex 287 default 0xdead000000000000 288 289config LOCKDEP_SUPPORT 290 def_bool y 291 292config GENERIC_BUG 293 def_bool y 294 depends on BUG 295 296config GENERIC_BUG_RELATIVE_POINTERS 297 def_bool y 298 depends on GENERIC_BUG 299 300config GENERIC_HWEIGHT 301 def_bool y 302 303config GENERIC_CSUM 304 def_bool y 305 306config GENERIC_CALIBRATE_DELAY 307 def_bool y 308 309config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 310 def_bool y 311 312config SMP 313 def_bool y 314 315config KERNEL_MODE_NEON 316 def_bool y 317 318config FIX_EARLYCON_MEM 319 def_bool y 320 321config PGTABLE_LEVELS 322 int 323 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 324 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 325 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 326 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 327 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 328 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 329 330config ARCH_SUPPORTS_UPROBES 331 def_bool y 332 333config ARCH_PROC_KCORE_TEXT 334 def_bool y 335 336config BROKEN_GAS_INST 337 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 338 339config KASAN_SHADOW_OFFSET 340 hex 341 depends on KASAN_GENERIC || KASAN_SW_TAGS 342 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 343 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 344 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 345 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 346 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 347 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 348 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 349 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 350 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 351 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 352 default 0xffffffffffffffff 353 354source "arch/arm64/Kconfig.platforms" 355 356menu "Kernel Features" 357 358menu "ARM errata workarounds via the alternatives framework" 359 360config ARM64_WORKAROUND_CLEAN_CACHE 361 bool 362 363config ARM64_ERRATUM_826319 364 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 365 default y 366 select ARM64_WORKAROUND_CLEAN_CACHE 367 help 368 This option adds an alternative code sequence to work around ARM 369 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 370 AXI master interface and an L2 cache. 371 372 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 373 and is unable to accept a certain write via this interface, it will 374 not progress on read data presented on the read data channel and the 375 system can deadlock. 376 377 The workaround promotes data cache clean instructions to 378 data cache clean-and-invalidate. 379 Please note that this does not necessarily enable the workaround, 380 as it depends on the alternative framework, which will only patch 381 the kernel if an affected CPU is detected. 382 383 If unsure, say Y. 384 385config ARM64_ERRATUM_827319 386 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 387 default y 388 select ARM64_WORKAROUND_CLEAN_CACHE 389 help 390 This option adds an alternative code sequence to work around ARM 391 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 392 master interface and an L2 cache. 393 394 Under certain conditions this erratum can cause a clean line eviction 395 to occur at the same time as another transaction to the same address 396 on the AMBA 5 CHI interface, which can cause data corruption if the 397 interconnect reorders the two transactions. 398 399 The workaround promotes data cache clean instructions to 400 data cache clean-and-invalidate. 401 Please note that this does not necessarily enable the workaround, 402 as it depends on the alternative framework, which will only patch 403 the kernel if an affected CPU is detected. 404 405 If unsure, say Y. 406 407config ARM64_ERRATUM_824069 408 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 409 default y 410 select ARM64_WORKAROUND_CLEAN_CACHE 411 help 412 This option adds an alternative code sequence to work around ARM 413 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 414 to a coherent interconnect. 415 416 If a Cortex-A53 processor is executing a store or prefetch for 417 write instruction at the same time as a processor in another 418 cluster is executing a cache maintenance operation to the same 419 address, then this erratum might cause a clean cache line to be 420 incorrectly marked as dirty. 421 422 The workaround promotes data cache clean instructions to 423 data cache clean-and-invalidate. 424 Please note that this option does not necessarily enable the 425 workaround, as it depends on the alternative framework, which will 426 only patch the kernel if an affected CPU is detected. 427 428 If unsure, say Y. 429 430config ARM64_ERRATUM_819472 431 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 432 default y 433 select ARM64_WORKAROUND_CLEAN_CACHE 434 help 435 This option adds an alternative code sequence to work around ARM 436 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 437 present when it is connected to a coherent interconnect. 438 439 If the processor is executing a load and store exclusive sequence at 440 the same time as a processor in another cluster is executing a cache 441 maintenance operation to the same address, then this erratum might 442 cause data corruption. 443 444 The workaround promotes data cache clean instructions to 445 data cache clean-and-invalidate. 446 Please note that this does not necessarily enable the workaround, 447 as it depends on the alternative framework, which will only patch 448 the kernel if an affected CPU is detected. 449 450 If unsure, say Y. 451 452config ARM64_ERRATUM_832075 453 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 454 default y 455 help 456 This option adds an alternative code sequence to work around ARM 457 erratum 832075 on Cortex-A57 parts up to r1p2. 458 459 Affected Cortex-A57 parts might deadlock when exclusive load/store 460 instructions to Write-Back memory are mixed with Device loads. 461 462 The workaround is to promote device loads to use Load-Acquire 463 semantics. 464 Please note that this does not necessarily enable the workaround, 465 as it depends on the alternative framework, which will only patch 466 the kernel if an affected CPU is detected. 467 468 If unsure, say Y. 469 470config ARM64_ERRATUM_834220 471 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 472 depends on KVM 473 default y 474 help 475 This option adds an alternative code sequence to work around ARM 476 erratum 834220 on Cortex-A57 parts up to r1p2. 477 478 Affected Cortex-A57 parts might report a Stage 2 translation 479 fault as the result of a Stage 1 fault for load crossing a 480 page boundary when there is a permission or device memory 481 alignment fault at Stage 1 and a translation fault at Stage 2. 482 483 The workaround is to verify that the Stage 1 translation 484 doesn't generate a fault before handling the Stage 2 fault. 485 Please note that this does not necessarily enable the workaround, 486 as it depends on the alternative framework, which will only patch 487 the kernel if an affected CPU is detected. 488 489 If unsure, say Y. 490 491config ARM64_ERRATUM_845719 492 bool "Cortex-A53: 845719: a load might read incorrect data" 493 depends on COMPAT 494 default y 495 help 496 This option adds an alternative code sequence to work around ARM 497 erratum 845719 on Cortex-A53 parts up to r0p4. 498 499 When running a compat (AArch32) userspace on an affected Cortex-A53 500 part, a load at EL0 from a virtual address that matches the bottom 32 501 bits of the virtual address used by a recent load at (AArch64) EL1 502 might return incorrect data. 503 504 The workaround is to write the contextidr_el1 register on exception 505 return to a 32-bit task. 506 Please note that this does not necessarily enable the workaround, 507 as it depends on the alternative framework, which will only patch 508 the kernel if an affected CPU is detected. 509 510 If unsure, say Y. 511 512config ARM64_ERRATUM_843419 513 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 514 default y 515 select ARM64_MODULE_PLTS if MODULES 516 help 517 This option links the kernel with '--fix-cortex-a53-843419' and 518 enables PLT support to replace certain ADRP instructions, which can 519 cause subsequent memory accesses to use an incorrect address on 520 Cortex-A53 parts up to r0p4. 521 522 If unsure, say Y. 523 524config ARM64_LD_HAS_FIX_ERRATUM_843419 525 def_bool $(ld-option,--fix-cortex-a53-843419) 526 527config ARM64_ERRATUM_1024718 528 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 529 default y 530 help 531 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 532 533 Affected Cortex-A55 cores (all revisions) could cause incorrect 534 update of the hardware dirty bit when the DBM/AP bits are updated 535 without a break-before-make. The workaround is to disable the usage 536 of hardware DBM locally on the affected cores. CPUs not affected by 537 this erratum will continue to use the feature. 538 539 If unsure, say Y. 540 541config ARM64_ERRATUM_1418040 542 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 543 default y 544 depends on COMPAT 545 help 546 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 547 errata 1188873 and 1418040. 548 549 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 550 cause register corruption when accessing the timer registers 551 from AArch32 userspace. 552 553 If unsure, say Y. 554 555config ARM64_WORKAROUND_SPECULATIVE_AT 556 bool 557 558config ARM64_ERRATUM_1165522 559 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 560 default y 561 select ARM64_WORKAROUND_SPECULATIVE_AT 562 help 563 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 564 565 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 566 corrupted TLBs by speculating an AT instruction during a guest 567 context switch. 568 569 If unsure, say Y. 570 571config ARM64_ERRATUM_1319367 572 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 573 default y 574 select ARM64_WORKAROUND_SPECULATIVE_AT 575 help 576 This option adds work arounds for ARM Cortex-A57 erratum 1319537 577 and A72 erratum 1319367 578 579 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 580 speculating an AT instruction during a guest context switch. 581 582 If unsure, say Y. 583 584config ARM64_ERRATUM_1530923 585 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 586 default y 587 select ARM64_WORKAROUND_SPECULATIVE_AT 588 help 589 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 590 591 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 592 corrupted TLBs by speculating an AT instruction during a guest 593 context switch. 594 595 If unsure, say Y. 596 597config ARM64_WORKAROUND_REPEAT_TLBI 598 bool 599 600config ARM64_ERRATUM_1286807 601 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 602 default y 603 select ARM64_WORKAROUND_REPEAT_TLBI 604 help 605 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 606 607 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 608 address for a cacheable mapping of a location is being 609 accessed by a core while another core is remapping the virtual 610 address to a new physical page using the recommended 611 break-before-make sequence, then under very rare circumstances 612 TLBI+DSB completes before a read using the translation being 613 invalidated has been observed by other observers. The 614 workaround repeats the TLBI+DSB operation. 615 616config ARM64_ERRATUM_1463225 617 bool "Cortex-A76: Software Step might prevent interrupt recognition" 618 default y 619 help 620 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 621 622 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 623 of a system call instruction (SVC) can prevent recognition of 624 subsequent interrupts when software stepping is disabled in the 625 exception handler of the system call and either kernel debugging 626 is enabled or VHE is in use. 627 628 Work around the erratum by triggering a dummy step exception 629 when handling a system call from a task that is being stepped 630 in a VHE configuration of the kernel. 631 632 If unsure, say Y. 633 634config ARM64_ERRATUM_1542419 635 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 636 default y 637 help 638 This option adds a workaround for ARM Neoverse-N1 erratum 639 1542419. 640 641 Affected Neoverse-N1 cores could execute a stale instruction when 642 modified by another CPU. The workaround depends on a firmware 643 counterpart. 644 645 Workaround the issue by hiding the DIC feature from EL0. This 646 forces user-space to perform cache maintenance. 647 648 If unsure, say Y. 649 650config ARM64_ERRATUM_1508412 651 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 652 default y 653 help 654 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 655 656 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 657 of a store-exclusive or read of PAR_EL1 and a load with device or 658 non-cacheable memory attributes. The workaround depends on a firmware 659 counterpart. 660 661 KVM guests must also have the workaround implemented or they can 662 deadlock the system. 663 664 Work around the issue by inserting DMB SY barriers around PAR_EL1 665 register reads and warning KVM users. The DMB barrier is sufficient 666 to prevent a speculative PAR_EL1 read. 667 668 If unsure, say Y. 669 670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 671 bool 672 673config ARM64_ERRATUM_2051678 674 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 675 help 676 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 677 Affected Coretex-A510 might not respect the ordering rules for 678 hardware update of the page table's dirty bit. The workaround 679 is to not enable the feature on affected CPUs. 680 681 If unsure, say Y. 682 683config ARM64_ERRATUM_2119858 684 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 685 default y 686 depends on CORESIGHT_TRBE 687 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 688 help 689 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 690 691 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 692 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 693 the event of a WRAP event. 694 695 Work around the issue by always making sure we move the TRBPTR_EL1 by 696 256 bytes before enabling the buffer and filling the first 256 bytes of 697 the buffer with ETM ignore packets upon disabling. 698 699 If unsure, say Y. 700 701config ARM64_ERRATUM_2139208 702 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 703 default y 704 depends on CORESIGHT_TRBE 705 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 706 help 707 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 708 709 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 710 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 711 the event of a WRAP event. 712 713 Work around the issue by always making sure we move the TRBPTR_EL1 by 714 256 bytes before enabling the buffer and filling the first 256 bytes of 715 the buffer with ETM ignore packets upon disabling. 716 717 If unsure, say Y. 718 719config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 720 bool 721 722config ARM64_ERRATUM_2054223 723 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 724 default y 725 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 726 help 727 Enable workaround for ARM Cortex-A710 erratum 2054223 728 729 Affected cores may fail to flush the trace data on a TSB instruction, when 730 the PE is in trace prohibited state. This will cause losing a few bytes 731 of the trace cached. 732 733 Workaround is to issue two TSB consecutively on affected cores. 734 735 If unsure, say Y. 736 737config ARM64_ERRATUM_2067961 738 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 739 default y 740 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 741 help 742 Enable workaround for ARM Neoverse-N2 erratum 2067961 743 744 Affected cores may fail to flush the trace data on a TSB instruction, when 745 the PE is in trace prohibited state. This will cause losing a few bytes 746 of the trace cached. 747 748 Workaround is to issue two TSB consecutively on affected cores. 749 750 If unsure, say Y. 751 752config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 753 bool 754 755config ARM64_ERRATUM_2253138 756 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 757 depends on CORESIGHT_TRBE 758 default y 759 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 760 help 761 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 762 763 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 764 for TRBE. Under some conditions, the TRBE might generate a write to the next 765 virtually addressed page following the last page of the TRBE address space 766 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 767 768 Work around this in the driver by always making sure that there is a 769 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 770 771 If unsure, say Y. 772 773config ARM64_ERRATUM_2224489 774 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 775 depends on CORESIGHT_TRBE 776 default y 777 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 778 help 779 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 780 781 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 782 for TRBE. Under some conditions, the TRBE might generate a write to the next 783 virtually addressed page following the last page of the TRBE address space 784 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 785 786 Work around this in the driver by always making sure that there is a 787 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 788 789 If unsure, say Y. 790 791config ARM64_ERRATUM_2064142 792 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 793 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 794 default y 795 help 796 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 797 798 Affected Cortex-A510 core might fail to write into system registers after the 799 TRBE has been disabled. Under some conditions after the TRBE has been disabled 800 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 801 and TRBTRG_EL1 will be ignored and will not be effected. 802 803 Work around this in the driver by executing TSB CSYNC and DSB after collection 804 is stopped and before performing a system register write to one of the affected 805 registers. 806 807 If unsure, say Y. 808 809config ARM64_ERRATUM_2038923 810 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 811 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 812 default y 813 help 814 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 815 816 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 817 prohibited within the CPU. As a result, the trace buffer or trace buffer state 818 might be corrupted. This happens after TRBE buffer has been enabled by setting 819 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 820 execution changes from a context, in which trace is prohibited to one where it 821 isn't, or vice versa. In these mentioned conditions, the view of whether trace 822 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 823 the trace buffer state might be corrupted. 824 825 Work around this in the driver by preventing an inconsistent view of whether the 826 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 827 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 828 two ISB instructions if no ERET is to take place. 829 830 If unsure, say Y. 831 832config ARM64_ERRATUM_1902691 833 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 834 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 835 default y 836 help 837 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 838 839 Affected Cortex-A510 core might cause trace data corruption, when being written 840 into the memory. Effectively TRBE is broken and hence cannot be used to capture 841 trace data. 842 843 Work around this problem in the driver by just preventing TRBE initialization on 844 affected cpus. The firmware must have disabled the access to TRBE for the kernel 845 on such implementations. This will cover the kernel for any firmware that doesn't 846 do this already. 847 848 If unsure, say Y. 849 850config CAVIUM_ERRATUM_22375 851 bool "Cavium erratum 22375, 24313" 852 default y 853 help 854 Enable workaround for errata 22375 and 24313. 855 856 This implements two gicv3-its errata workarounds for ThunderX. Both 857 with a small impact affecting only ITS table allocation. 858 859 erratum 22375: only alloc 8MB table size 860 erratum 24313: ignore memory access type 861 862 The fixes are in ITS initialization and basically ignore memory access 863 type and table size provided by the TYPER and BASER registers. 864 865 If unsure, say Y. 866 867config CAVIUM_ERRATUM_23144 868 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 869 depends on NUMA 870 default y 871 help 872 ITS SYNC command hang for cross node io and collections/cpu mapping. 873 874 If unsure, say Y. 875 876config CAVIUM_ERRATUM_23154 877 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 878 default y 879 help 880 The gicv3 of ThunderX requires a modified version for 881 reading the IAR status to ensure data synchronization 882 (access to icc_iar1_el1 is not sync'ed before and after). 883 884 If unsure, say Y. 885 886config CAVIUM_ERRATUM_27456 887 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 888 default y 889 help 890 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 891 instructions may cause the icache to become corrupted if it 892 contains data for a non-current ASID. The fix is to 893 invalidate the icache when changing the mm context. 894 895 If unsure, say Y. 896 897config CAVIUM_ERRATUM_30115 898 bool "Cavium erratum 30115: Guest may disable interrupts in host" 899 default y 900 help 901 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 902 1.2, and T83 Pass 1.0, KVM guest execution may disable 903 interrupts in host. Trapping both GICv3 group-0 and group-1 904 accesses sidesteps the issue. 905 906 If unsure, say Y. 907 908config CAVIUM_TX2_ERRATUM_219 909 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 910 default y 911 help 912 On Cavium ThunderX2, a load, store or prefetch instruction between a 913 TTBR update and the corresponding context synchronizing operation can 914 cause a spurious Data Abort to be delivered to any hardware thread in 915 the CPU core. 916 917 Work around the issue by avoiding the problematic code sequence and 918 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 919 trap handler performs the corresponding register access, skips the 920 instruction and ensures context synchronization by virtue of the 921 exception return. 922 923 If unsure, say Y. 924 925config FUJITSU_ERRATUM_010001 926 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 927 default y 928 help 929 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 930 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 931 accesses may cause undefined fault (Data abort, DFSC=0b111111). 932 This fault occurs under a specific hardware condition when a 933 load/store instruction performs an address translation using: 934 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 935 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 936 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 937 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 938 939 The workaround is to ensure these bits are clear in TCR_ELx. 940 The workaround only affects the Fujitsu-A64FX. 941 942 If unsure, say Y. 943 944config HISILICON_ERRATUM_161600802 945 bool "Hip07 161600802: Erroneous redistributor VLPI base" 946 default y 947 help 948 The HiSilicon Hip07 SoC uses the wrong redistributor base 949 when issued ITS commands such as VMOVP and VMAPP, and requires 950 a 128kB offset to be applied to the target address in this commands. 951 952 If unsure, say Y. 953 954config QCOM_FALKOR_ERRATUM_1003 955 bool "Falkor E1003: Incorrect translation due to ASID change" 956 default y 957 help 958 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 959 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 960 in TTBR1_EL1, this situation only occurs in the entry trampoline and 961 then only for entries in the walk cache, since the leaf translation 962 is unchanged. Work around the erratum by invalidating the walk cache 963 entries for the trampoline before entering the kernel proper. 964 965config QCOM_FALKOR_ERRATUM_1009 966 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 967 default y 968 select ARM64_WORKAROUND_REPEAT_TLBI 969 help 970 On Falkor v1, the CPU may prematurely complete a DSB following a 971 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 972 one more time to fix the issue. 973 974 If unsure, say Y. 975 976config QCOM_QDF2400_ERRATUM_0065 977 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 978 default y 979 help 980 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 981 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 982 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 983 984 If unsure, say Y. 985 986config QCOM_FALKOR_ERRATUM_E1041 987 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 988 default y 989 help 990 Falkor CPU may speculatively fetch instructions from an improper 991 memory location when MMU translation is changed from SCTLR_ELn[M]=1 992 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 993 994 If unsure, say Y. 995 996config NVIDIA_CARMEL_CNP_ERRATUM 997 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 998 default y 999 help 1000 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1001 invalidate shared TLB entries installed by a different core, as it would 1002 on standard ARM cores. 1003 1004 If unsure, say Y. 1005 1006config SOCIONEXT_SYNQUACER_PREITS 1007 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1008 default y 1009 help 1010 Socionext Synquacer SoCs implement a separate h/w block to generate 1011 MSI doorbell writes with non-zero values for the device ID. 1012 1013 If unsure, say Y. 1014 1015endmenu 1016 1017 1018choice 1019 prompt "Page size" 1020 default ARM64_4K_PAGES 1021 help 1022 Page size (translation granule) configuration. 1023 1024config ARM64_4K_PAGES 1025 bool "4KB" 1026 help 1027 This feature enables 4KB pages support. 1028 1029config ARM64_16K_PAGES 1030 bool "16KB" 1031 help 1032 The system will use 16KB pages support. AArch32 emulation 1033 requires applications compiled with 16K (or a multiple of 16K) 1034 aligned segments. 1035 1036config ARM64_64K_PAGES 1037 bool "64KB" 1038 help 1039 This feature enables 64KB pages support (4KB by default) 1040 allowing only two levels of page tables and faster TLB 1041 look-up. AArch32 emulation requires applications compiled 1042 with 64K aligned segments. 1043 1044endchoice 1045 1046choice 1047 prompt "Virtual address space size" 1048 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1049 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1050 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1051 help 1052 Allows choosing one of multiple possible virtual address 1053 space sizes. The level of translation table is determined by 1054 a combination of page size and virtual address space size. 1055 1056config ARM64_VA_BITS_36 1057 bool "36-bit" if EXPERT 1058 depends on ARM64_16K_PAGES 1059 1060config ARM64_VA_BITS_39 1061 bool "39-bit" 1062 depends on ARM64_4K_PAGES 1063 1064config ARM64_VA_BITS_42 1065 bool "42-bit" 1066 depends on ARM64_64K_PAGES 1067 1068config ARM64_VA_BITS_47 1069 bool "47-bit" 1070 depends on ARM64_16K_PAGES 1071 1072config ARM64_VA_BITS_48 1073 bool "48-bit" 1074 1075config ARM64_VA_BITS_52 1076 bool "52-bit" 1077 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1078 help 1079 Enable 52-bit virtual addressing for userspace when explicitly 1080 requested via a hint to mmap(). The kernel will also use 52-bit 1081 virtual addresses for its own mappings (provided HW support for 1082 this feature is available, otherwise it reverts to 48-bit). 1083 1084 NOTE: Enabling 52-bit virtual addressing in conjunction with 1085 ARMv8.3 Pointer Authentication will result in the PAC being 1086 reduced from 7 bits to 3 bits, which may have a significant 1087 impact on its susceptibility to brute-force attacks. 1088 1089 If unsure, select 48-bit virtual addressing instead. 1090 1091endchoice 1092 1093config ARM64_FORCE_52BIT 1094 bool "Force 52-bit virtual addresses for userspace" 1095 depends on ARM64_VA_BITS_52 && EXPERT 1096 help 1097 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1098 to maintain compatibility with older software by providing 48-bit VAs 1099 unless a hint is supplied to mmap. 1100 1101 This configuration option disables the 48-bit compatibility logic, and 1102 forces all userspace addresses to be 52-bit on HW that supports it. One 1103 should only enable this configuration option for stress testing userspace 1104 memory management code. If unsure say N here. 1105 1106config ARM64_VA_BITS 1107 int 1108 default 36 if ARM64_VA_BITS_36 1109 default 39 if ARM64_VA_BITS_39 1110 default 42 if ARM64_VA_BITS_42 1111 default 47 if ARM64_VA_BITS_47 1112 default 48 if ARM64_VA_BITS_48 1113 default 52 if ARM64_VA_BITS_52 1114 1115choice 1116 prompt "Physical address space size" 1117 default ARM64_PA_BITS_48 1118 help 1119 Choose the maximum physical address range that the kernel will 1120 support. 1121 1122config ARM64_PA_BITS_48 1123 bool "48-bit" 1124 1125config ARM64_PA_BITS_52 1126 bool "52-bit (ARMv8.2)" 1127 depends on ARM64_64K_PAGES 1128 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1129 help 1130 Enable support for a 52-bit physical address space, introduced as 1131 part of the ARMv8.2-LPA extension. 1132 1133 With this enabled, the kernel will also continue to work on CPUs that 1134 do not support ARMv8.2-LPA, but with some added memory overhead (and 1135 minor performance overhead). 1136 1137endchoice 1138 1139config ARM64_PA_BITS 1140 int 1141 default 48 if ARM64_PA_BITS_48 1142 default 52 if ARM64_PA_BITS_52 1143 1144choice 1145 prompt "Endianness" 1146 default CPU_LITTLE_ENDIAN 1147 help 1148 Select the endianness of data accesses performed by the CPU. Userspace 1149 applications will need to be compiled and linked for the endianness 1150 that is selected here. 1151 1152config CPU_BIG_ENDIAN 1153 bool "Build big-endian kernel" 1154 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1155 help 1156 Say Y if you plan on running a kernel with a big-endian userspace. 1157 1158config CPU_LITTLE_ENDIAN 1159 bool "Build little-endian kernel" 1160 help 1161 Say Y if you plan on running a kernel with a little-endian userspace. 1162 This is usually the case for distributions targeting arm64. 1163 1164endchoice 1165 1166config SCHED_MC 1167 bool "Multi-core scheduler support" 1168 help 1169 Multi-core scheduler support improves the CPU scheduler's decision 1170 making when dealing with multi-core CPU chips at a cost of slightly 1171 increased overhead in some places. If unsure say N here. 1172 1173config SCHED_CLUSTER 1174 bool "Cluster scheduler support" 1175 help 1176 Cluster scheduler support improves the CPU scheduler's decision 1177 making when dealing with machines that have clusters of CPUs. 1178 Cluster usually means a couple of CPUs which are placed closely 1179 by sharing mid-level caches, last-level cache tags or internal 1180 busses. 1181 1182config SCHED_SMT 1183 bool "SMT scheduler support" 1184 help 1185 Improves the CPU scheduler's decision making when dealing with 1186 MultiThreading at a cost of slightly increased overhead in some 1187 places. If unsure say N here. 1188 1189config NR_CPUS 1190 int "Maximum number of CPUs (2-4096)" 1191 range 2 4096 1192 default "256" 1193 1194config HOTPLUG_CPU 1195 bool "Support for hot-pluggable CPUs" 1196 select GENERIC_IRQ_MIGRATION 1197 help 1198 Say Y here to experiment with turning CPUs off and on. CPUs 1199 can be controlled through /sys/devices/system/cpu. 1200 1201# Common NUMA Features 1202config NUMA 1203 bool "NUMA Memory Allocation and Scheduler Support" 1204 select GENERIC_ARCH_NUMA 1205 select ACPI_NUMA if ACPI 1206 select OF_NUMA 1207 select HAVE_SETUP_PER_CPU_AREA 1208 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1209 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1210 select USE_PERCPU_NUMA_NODE_ID 1211 help 1212 Enable NUMA (Non-Uniform Memory Access) support. 1213 1214 The kernel will try to allocate memory used by a CPU on the 1215 local memory of the CPU and add some more 1216 NUMA awareness to the kernel. 1217 1218config NODES_SHIFT 1219 int "Maximum NUMA Nodes (as a power of 2)" 1220 range 1 10 1221 default "4" 1222 depends on NUMA 1223 help 1224 Specify the maximum number of NUMA Nodes available on the target 1225 system. Increases memory reserved to accommodate various tables. 1226 1227source "kernel/Kconfig.hz" 1228 1229config ARCH_SPARSEMEM_ENABLE 1230 def_bool y 1231 select SPARSEMEM_VMEMMAP_ENABLE 1232 select SPARSEMEM_VMEMMAP 1233 1234config HW_PERF_EVENTS 1235 def_bool y 1236 depends on ARM_PMU 1237 1238config ARCH_HAS_FILTER_PGPROT 1239 def_bool y 1240 1241# Supported by clang >= 7.0 1242config CC_HAVE_SHADOW_CALL_STACK 1243 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1244 1245config PARAVIRT 1246 bool "Enable paravirtualization code" 1247 help 1248 This changes the kernel so it can modify itself when it is run 1249 under a hypervisor, potentially improving performance significantly 1250 over full virtualization. 1251 1252config PARAVIRT_TIME_ACCOUNTING 1253 bool "Paravirtual steal time accounting" 1254 select PARAVIRT 1255 help 1256 Select this option to enable fine granularity task steal time 1257 accounting. Time spent executing other tasks in parallel with 1258 the current vCPU is discounted from the vCPU power. To account for 1259 that, there can be a small performance impact. 1260 1261 If in doubt, say N here. 1262 1263config KEXEC 1264 depends on PM_SLEEP_SMP 1265 select KEXEC_CORE 1266 bool "kexec system call" 1267 help 1268 kexec is a system call that implements the ability to shutdown your 1269 current kernel, and to start another kernel. It is like a reboot 1270 but it is independent of the system firmware. And like a reboot 1271 you can start any kernel with it, not just Linux. 1272 1273config KEXEC_FILE 1274 bool "kexec file based system call" 1275 select KEXEC_CORE 1276 select HAVE_IMA_KEXEC if IMA 1277 help 1278 This is new version of kexec system call. This system call is 1279 file based and takes file descriptors as system call argument 1280 for kernel and initramfs as opposed to list of segments as 1281 accepted by previous system call. 1282 1283config KEXEC_SIG 1284 bool "Verify kernel signature during kexec_file_load() syscall" 1285 depends on KEXEC_FILE 1286 help 1287 Select this option to verify a signature with loaded kernel 1288 image. If configured, any attempt of loading a image without 1289 valid signature will fail. 1290 1291 In addition to that option, you need to enable signature 1292 verification for the corresponding kernel image type being 1293 loaded in order for this to work. 1294 1295config KEXEC_IMAGE_VERIFY_SIG 1296 bool "Enable Image signature verification support" 1297 default y 1298 depends on KEXEC_SIG 1299 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1300 help 1301 Enable Image signature verification support. 1302 1303comment "Support for PE file signature verification disabled" 1304 depends on KEXEC_SIG 1305 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1306 1307config CRASH_DUMP 1308 bool "Build kdump crash kernel" 1309 help 1310 Generate crash dump after being started by kexec. This should 1311 be normally only set in special crash dump kernels which are 1312 loaded in the main kernel with kexec-tools into a specially 1313 reserved region and then later executed after a crash by 1314 kdump/kexec. 1315 1316 For more details see Documentation/admin-guide/kdump/kdump.rst 1317 1318config TRANS_TABLE 1319 def_bool y 1320 depends on HIBERNATION || KEXEC_CORE 1321 1322config XEN_DOM0 1323 def_bool y 1324 depends on XEN 1325 1326config XEN 1327 bool "Xen guest support on ARM64" 1328 depends on ARM64 && OF 1329 select SWIOTLB_XEN 1330 select PARAVIRT 1331 help 1332 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1333 1334config FORCE_MAX_ZONEORDER 1335 int 1336 default "14" if ARM64_64K_PAGES 1337 default "12" if ARM64_16K_PAGES 1338 default "11" 1339 help 1340 The kernel memory allocator divides physically contiguous memory 1341 blocks into "zones", where each zone is a power of two number of 1342 pages. This option selects the largest power of two that the kernel 1343 keeps in the memory allocator. If you need to allocate very large 1344 blocks of physically contiguous memory, then you may need to 1345 increase this value. 1346 1347 This config option is actually maximum order plus one. For example, 1348 a value of 11 means that the largest free memory block is 2^10 pages. 1349 1350 We make sure that we can allocate upto a HugePage size for each configuration. 1351 Hence we have : 1352 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1353 1354 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1355 4M allocations matching the default size used by generic code. 1356 1357config UNMAP_KERNEL_AT_EL0 1358 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1359 default y 1360 help 1361 Speculation attacks against some high-performance processors can 1362 be used to bypass MMU permission checks and leak kernel data to 1363 userspace. This can be defended against by unmapping the kernel 1364 when running in userspace, mapping it back in on exception entry 1365 via a trampoline page in the vector table. 1366 1367 If unsure, say Y. 1368 1369config RODATA_FULL_DEFAULT_ENABLED 1370 bool "Apply r/o permissions of VM areas also to their linear aliases" 1371 default y 1372 help 1373 Apply read-only attributes of VM areas to the linear alias of 1374 the backing pages as well. This prevents code or read-only data 1375 from being modified (inadvertently or intentionally) via another 1376 mapping of the same memory page. This additional enhancement can 1377 be turned off at runtime by passing rodata=[off|on] (and turned on 1378 with rodata=full if this option is set to 'n') 1379 1380 This requires the linear region to be mapped down to pages, 1381 which may adversely affect performance in some cases. 1382 1383config ARM64_SW_TTBR0_PAN 1384 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1385 help 1386 Enabling this option prevents the kernel from accessing 1387 user-space memory directly by pointing TTBR0_EL1 to a reserved 1388 zeroed area and reserved ASID. The user access routines 1389 restore the valid TTBR0_EL1 temporarily. 1390 1391config ARM64_TAGGED_ADDR_ABI 1392 bool "Enable the tagged user addresses syscall ABI" 1393 default y 1394 help 1395 When this option is enabled, user applications can opt in to a 1396 relaxed ABI via prctl() allowing tagged addresses to be passed 1397 to system calls as pointer arguments. For details, see 1398 Documentation/arm64/tagged-address-abi.rst. 1399 1400menuconfig COMPAT 1401 bool "Kernel support for 32-bit EL0" 1402 depends on ARM64_4K_PAGES || EXPERT 1403 select HAVE_UID16 1404 select OLD_SIGSUSPEND3 1405 select COMPAT_OLD_SIGACTION 1406 help 1407 This option enables support for a 32-bit EL0 running under a 64-bit 1408 kernel at EL1. AArch32-specific components such as system calls, 1409 the user helper functions, VFP support and the ptrace interface are 1410 handled appropriately by the kernel. 1411 1412 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1413 that you will only be able to execute AArch32 binaries that were compiled 1414 with page size aligned segments. 1415 1416 If you want to execute 32-bit userspace applications, say Y. 1417 1418if COMPAT 1419 1420config KUSER_HELPERS 1421 bool "Enable kuser helpers page for 32-bit applications" 1422 default y 1423 help 1424 Warning: disabling this option may break 32-bit user programs. 1425 1426 Provide kuser helpers to compat tasks. The kernel provides 1427 helper code to userspace in read only form at a fixed location 1428 to allow userspace to be independent of the CPU type fitted to 1429 the system. This permits binaries to be run on ARMv4 through 1430 to ARMv8 without modification. 1431 1432 See Documentation/arm/kernel_user_helpers.rst for details. 1433 1434 However, the fixed address nature of these helpers can be used 1435 by ROP (return orientated programming) authors when creating 1436 exploits. 1437 1438 If all of the binaries and libraries which run on your platform 1439 are built specifically for your platform, and make no use of 1440 these helpers, then you can turn this option off to hinder 1441 such exploits. However, in that case, if a binary or library 1442 relying on those helpers is run, it will not function correctly. 1443 1444 Say N here only if you are absolutely certain that you do not 1445 need these helpers; otherwise, the safe option is to say Y. 1446 1447config COMPAT_VDSO 1448 bool "Enable vDSO for 32-bit applications" 1449 depends on !CPU_BIG_ENDIAN 1450 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1451 select GENERIC_COMPAT_VDSO 1452 default y 1453 help 1454 Place in the process address space of 32-bit applications an 1455 ELF shared object providing fast implementations of gettimeofday 1456 and clock_gettime. 1457 1458 You must have a 32-bit build of glibc 2.22 or later for programs 1459 to seamlessly take advantage of this. 1460 1461config THUMB2_COMPAT_VDSO 1462 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1463 depends on COMPAT_VDSO 1464 default y 1465 help 1466 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1467 otherwise with '-marm'. 1468 1469menuconfig ARMV8_DEPRECATED 1470 bool "Emulate deprecated/obsolete ARMv8 instructions" 1471 depends on SYSCTL 1472 help 1473 Legacy software support may require certain instructions 1474 that have been deprecated or obsoleted in the architecture. 1475 1476 Enable this config to enable selective emulation of these 1477 features. 1478 1479 If unsure, say Y 1480 1481if ARMV8_DEPRECATED 1482 1483config SWP_EMULATION 1484 bool "Emulate SWP/SWPB instructions" 1485 help 1486 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1487 they are always undefined. Say Y here to enable software 1488 emulation of these instructions for userspace using LDXR/STXR. 1489 This feature can be controlled at runtime with the abi.swp 1490 sysctl which is disabled by default. 1491 1492 In some older versions of glibc [<=2.8] SWP is used during futex 1493 trylock() operations with the assumption that the code will not 1494 be preempted. This invalid assumption may be more likely to fail 1495 with SWP emulation enabled, leading to deadlock of the user 1496 application. 1497 1498 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1499 on an external transaction monitoring block called a global 1500 monitor to maintain update atomicity. If your system does not 1501 implement a global monitor, this option can cause programs that 1502 perform SWP operations to uncached memory to deadlock. 1503 1504 If unsure, say Y 1505 1506config CP15_BARRIER_EMULATION 1507 bool "Emulate CP15 Barrier instructions" 1508 help 1509 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1510 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1511 strongly recommended to use the ISB, DSB, and DMB 1512 instructions instead. 1513 1514 Say Y here to enable software emulation of these 1515 instructions for AArch32 userspace code. When this option is 1516 enabled, CP15 barrier usage is traced which can help 1517 identify software that needs updating. This feature can be 1518 controlled at runtime with the abi.cp15_barrier sysctl. 1519 1520 If unsure, say Y 1521 1522config SETEND_EMULATION 1523 bool "Emulate SETEND instruction" 1524 help 1525 The SETEND instruction alters the data-endianness of the 1526 AArch32 EL0, and is deprecated in ARMv8. 1527 1528 Say Y here to enable software emulation of the instruction 1529 for AArch32 userspace code. This feature can be controlled 1530 at runtime with the abi.setend sysctl. 1531 1532 Note: All the cpus on the system must have mixed endian support at EL0 1533 for this feature to be enabled. If a new CPU - which doesn't support mixed 1534 endian - is hotplugged in after this feature has been enabled, there could 1535 be unexpected results in the applications. 1536 1537 If unsure, say Y 1538endif 1539 1540endif 1541 1542menu "ARMv8.1 architectural features" 1543 1544config ARM64_HW_AFDBM 1545 bool "Support for hardware updates of the Access and Dirty page flags" 1546 default y 1547 help 1548 The ARMv8.1 architecture extensions introduce support for 1549 hardware updates of the access and dirty information in page 1550 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1551 capable processors, accesses to pages with PTE_AF cleared will 1552 set this bit instead of raising an access flag fault. 1553 Similarly, writes to read-only pages with the DBM bit set will 1554 clear the read-only bit (AP[2]) instead of raising a 1555 permission fault. 1556 1557 Kernels built with this configuration option enabled continue 1558 to work on pre-ARMv8.1 hardware and the performance impact is 1559 minimal. If unsure, say Y. 1560 1561config ARM64_PAN 1562 bool "Enable support for Privileged Access Never (PAN)" 1563 default y 1564 help 1565 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1566 prevents the kernel or hypervisor from accessing user-space (EL0) 1567 memory directly. 1568 1569 Choosing this option will cause any unprotected (not using 1570 copy_to_user et al) memory access to fail with a permission fault. 1571 1572 The feature is detected at runtime, and will remain as a 'nop' 1573 instruction if the cpu does not implement the feature. 1574 1575config AS_HAS_LDAPR 1576 def_bool $(as-instr,.arch_extension rcpc) 1577 1578config AS_HAS_LSE_ATOMICS 1579 def_bool $(as-instr,.arch_extension lse) 1580 1581config ARM64_LSE_ATOMICS 1582 bool 1583 default ARM64_USE_LSE_ATOMICS 1584 depends on AS_HAS_LSE_ATOMICS 1585 1586config ARM64_USE_LSE_ATOMICS 1587 bool "Atomic instructions" 1588 depends on JUMP_LABEL 1589 default y 1590 help 1591 As part of the Large System Extensions, ARMv8.1 introduces new 1592 atomic instructions that are designed specifically to scale in 1593 very large systems. 1594 1595 Say Y here to make use of these instructions for the in-kernel 1596 atomic routines. This incurs a small overhead on CPUs that do 1597 not support these instructions and requires the kernel to be 1598 built with binutils >= 2.25 in order for the new instructions 1599 to be used. 1600 1601endmenu 1602 1603menu "ARMv8.2 architectural features" 1604 1605config AS_HAS_ARMV8_2 1606 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1607 1608config AS_HAS_SHA3 1609 def_bool $(as-instr,.arch armv8.2-a+sha3) 1610 1611config ARM64_PMEM 1612 bool "Enable support for persistent memory" 1613 select ARCH_HAS_PMEM_API 1614 select ARCH_HAS_UACCESS_FLUSHCACHE 1615 help 1616 Say Y to enable support for the persistent memory API based on the 1617 ARMv8.2 DCPoP feature. 1618 1619 The feature is detected at runtime, and the kernel will use DC CVAC 1620 operations if DC CVAP is not supported (following the behaviour of 1621 DC CVAP itself if the system does not define a point of persistence). 1622 1623config ARM64_RAS_EXTN 1624 bool "Enable support for RAS CPU Extensions" 1625 default y 1626 help 1627 CPUs that support the Reliability, Availability and Serviceability 1628 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1629 errors, classify them and report them to software. 1630 1631 On CPUs with these extensions system software can use additional 1632 barriers to determine if faults are pending and read the 1633 classification from a new set of registers. 1634 1635 Selecting this feature will allow the kernel to use these barriers 1636 and access the new registers if the system supports the extension. 1637 Platform RAS features may additionally depend on firmware support. 1638 1639config ARM64_CNP 1640 bool "Enable support for Common Not Private (CNP) translations" 1641 default y 1642 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1643 help 1644 Common Not Private (CNP) allows translation table entries to 1645 be shared between different PEs in the same inner shareable 1646 domain, so the hardware can use this fact to optimise the 1647 caching of such entries in the TLB. 1648 1649 Selecting this option allows the CNP feature to be detected 1650 at runtime, and does not affect PEs that do not implement 1651 this feature. 1652 1653endmenu 1654 1655menu "ARMv8.3 architectural features" 1656 1657config ARM64_PTR_AUTH 1658 bool "Enable support for pointer authentication" 1659 default y 1660 help 1661 Pointer authentication (part of the ARMv8.3 Extensions) provides 1662 instructions for signing and authenticating pointers against secret 1663 keys, which can be used to mitigate Return Oriented Programming (ROP) 1664 and other attacks. 1665 1666 This option enables these instructions at EL0 (i.e. for userspace). 1667 Choosing this option will cause the kernel to initialise secret keys 1668 for each process at exec() time, with these keys being 1669 context-switched along with the process. 1670 1671 The feature is detected at runtime. If the feature is not present in 1672 hardware it will not be advertised to userspace/KVM guest nor will it 1673 be enabled. 1674 1675 If the feature is present on the boot CPU but not on a late CPU, then 1676 the late CPU will be parked. Also, if the boot CPU does not have 1677 address auth and the late CPU has then the late CPU will still boot 1678 but with the feature disabled. On such a system, this option should 1679 not be selected. 1680 1681config ARM64_PTR_AUTH_KERNEL 1682 bool "Use pointer authentication for kernel" 1683 default y 1684 depends on ARM64_PTR_AUTH 1685 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1686 # Modern compilers insert a .note.gnu.property section note for PAC 1687 # which is only understood by binutils starting with version 2.33.1. 1688 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1689 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1690 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1691 help 1692 If the compiler supports the -mbranch-protection or 1693 -msign-return-address flag (e.g. GCC 7 or later), then this option 1694 will cause the kernel itself to be compiled with return address 1695 protection. In this case, and if the target hardware is known to 1696 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1697 disabled with minimal loss of protection. 1698 1699 This feature works with FUNCTION_GRAPH_TRACER option only if 1700 DYNAMIC_FTRACE_WITH_REGS is enabled. 1701 1702config CC_HAS_BRANCH_PROT_PAC_RET 1703 # GCC 9 or later, clang 8 or later 1704 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1705 1706config CC_HAS_SIGN_RETURN_ADDRESS 1707 # GCC 7, 8 1708 def_bool $(cc-option,-msign-return-address=all) 1709 1710config AS_HAS_PAC 1711 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1712 1713config AS_HAS_CFI_NEGATE_RA_STATE 1714 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1715 1716endmenu 1717 1718menu "ARMv8.4 architectural features" 1719 1720config ARM64_AMU_EXTN 1721 bool "Enable support for the Activity Monitors Unit CPU extension" 1722 default y 1723 help 1724 The activity monitors extension is an optional extension introduced 1725 by the ARMv8.4 CPU architecture. This enables support for version 1 1726 of the activity monitors architecture, AMUv1. 1727 1728 To enable the use of this extension on CPUs that implement it, say Y. 1729 1730 Note that for architectural reasons, firmware _must_ implement AMU 1731 support when running on CPUs that present the activity monitors 1732 extension. The required support is present in: 1733 * Version 1.5 and later of the ARM Trusted Firmware 1734 1735 For kernels that have this configuration enabled but boot with broken 1736 firmware, you may need to say N here until the firmware is fixed. 1737 Otherwise you may experience firmware panics or lockups when 1738 accessing the counter registers. Even if you are not observing these 1739 symptoms, the values returned by the register reads might not 1740 correctly reflect reality. Most commonly, the value read will be 0, 1741 indicating that the counter is not enabled. 1742 1743config AS_HAS_ARMV8_4 1744 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1745 1746config ARM64_TLB_RANGE 1747 bool "Enable support for tlbi range feature" 1748 default y 1749 depends on AS_HAS_ARMV8_4 1750 help 1751 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1752 range of input addresses. 1753 1754 The feature introduces new assembly instructions, and they were 1755 support when binutils >= 2.30. 1756 1757endmenu 1758 1759menu "ARMv8.5 architectural features" 1760 1761config AS_HAS_ARMV8_5 1762 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1763 1764config ARM64_BTI 1765 bool "Branch Target Identification support" 1766 default y 1767 help 1768 Branch Target Identification (part of the ARMv8.5 Extensions) 1769 provides a mechanism to limit the set of locations to which computed 1770 branch instructions such as BR or BLR can jump. 1771 1772 To make use of BTI on CPUs that support it, say Y. 1773 1774 BTI is intended to provide complementary protection to other control 1775 flow integrity protection mechanisms, such as the Pointer 1776 authentication mechanism provided as part of the ARMv8.3 Extensions. 1777 For this reason, it does not make sense to enable this option without 1778 also enabling support for pointer authentication. Thus, when 1779 enabling this option you should also select ARM64_PTR_AUTH=y. 1780 1781 Userspace binaries must also be specifically compiled to make use of 1782 this mechanism. If you say N here or the hardware does not support 1783 BTI, such binaries can still run, but you get no additional 1784 enforcement of branch destinations. 1785 1786config ARM64_BTI_KERNEL 1787 bool "Use Branch Target Identification for kernel" 1788 default y 1789 depends on ARM64_BTI 1790 depends on ARM64_PTR_AUTH_KERNEL 1791 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1792 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1793 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1794 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1795 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1796 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1797 help 1798 Build the kernel with Branch Target Identification annotations 1799 and enable enforcement of this for kernel code. When this option 1800 is enabled and the system supports BTI all kernel code including 1801 modular code must have BTI enabled. 1802 1803config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1804 # GCC 9 or later, clang 8 or later 1805 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1806 1807config ARM64_E0PD 1808 bool "Enable support for E0PD" 1809 default y 1810 help 1811 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1812 that EL0 accesses made via TTBR1 always fault in constant time, 1813 providing similar benefits to KASLR as those provided by KPTI, but 1814 with lower overhead and without disrupting legitimate access to 1815 kernel memory such as SPE. 1816 1817 This option enables E0PD for TTBR1 where available. 1818 1819config ARCH_RANDOM 1820 bool "Enable support for random number generation" 1821 default y 1822 help 1823 Random number generation (part of the ARMv8.5 Extensions) 1824 provides a high bandwidth, cryptographically secure 1825 hardware random number generator. 1826 1827config ARM64_AS_HAS_MTE 1828 # Initial support for MTE went in binutils 2.32.0, checked with 1829 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1830 # as a late addition to the final architecture spec (LDGM/STGM) 1831 # is only supported in the newer 2.32.x and 2.33 binutils 1832 # versions, hence the extra "stgm" instruction check below. 1833 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1834 1835config ARM64_MTE 1836 bool "Memory Tagging Extension support" 1837 default y 1838 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1839 depends on AS_HAS_ARMV8_5 1840 depends on AS_HAS_LSE_ATOMICS 1841 # Required for tag checking in the uaccess routines 1842 depends on ARM64_PAN 1843 select ARCH_USES_HIGH_VMA_FLAGS 1844 help 1845 Memory Tagging (part of the ARMv8.5 Extensions) provides 1846 architectural support for run-time, always-on detection of 1847 various classes of memory error to aid with software debugging 1848 to eliminate vulnerabilities arising from memory-unsafe 1849 languages. 1850 1851 This option enables the support for the Memory Tagging 1852 Extension at EL0 (i.e. for userspace). 1853 1854 Selecting this option allows the feature to be detected at 1855 runtime. Any secondary CPU not implementing this feature will 1856 not be allowed a late bring-up. 1857 1858 Userspace binaries that want to use this feature must 1859 explicitly opt in. The mechanism for the userspace is 1860 described in: 1861 1862 Documentation/arm64/memory-tagging-extension.rst. 1863 1864endmenu 1865 1866menu "ARMv8.7 architectural features" 1867 1868config ARM64_EPAN 1869 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1870 default y 1871 depends on ARM64_PAN 1872 help 1873 Enhanced Privileged Access Never (EPAN) allows Privileged 1874 Access Never to be used with Execute-only mappings. 1875 1876 The feature is detected at runtime, and will remain disabled 1877 if the cpu does not implement the feature. 1878endmenu 1879 1880config ARM64_SVE 1881 bool "ARM Scalable Vector Extension support" 1882 default y 1883 help 1884 The Scalable Vector Extension (SVE) is an extension to the AArch64 1885 execution state which complements and extends the SIMD functionality 1886 of the base architecture to support much larger vectors and to enable 1887 additional vectorisation opportunities. 1888 1889 To enable use of this extension on CPUs that implement it, say Y. 1890 1891 On CPUs that support the SVE2 extensions, this option will enable 1892 those too. 1893 1894 Note that for architectural reasons, firmware _must_ implement SVE 1895 support when running on SVE capable hardware. The required support 1896 is present in: 1897 1898 * version 1.5 and later of the ARM Trusted Firmware 1899 * the AArch64 boot wrapper since commit 5e1261e08abf 1900 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1901 1902 For other firmware implementations, consult the firmware documentation 1903 or vendor. 1904 1905 If you need the kernel to boot on SVE-capable hardware with broken 1906 firmware, you may need to say N here until you get your firmware 1907 fixed. Otherwise, you may experience firmware panics or lockups when 1908 booting the kernel. If unsure and you are not observing these 1909 symptoms, you should assume that it is safe to say Y. 1910 1911config ARM64_MODULE_PLTS 1912 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1913 depends on MODULES 1914 select HAVE_MOD_ARCH_SPECIFIC 1915 help 1916 Allocate PLTs when loading modules so that jumps and calls whose 1917 targets are too far away for their relative offsets to be encoded 1918 in the instructions themselves can be bounced via veneers in the 1919 module's PLT. This allows modules to be allocated in the generic 1920 vmalloc area after the dedicated module memory area has been 1921 exhausted. 1922 1923 When running with address space randomization (KASLR), the module 1924 region itself may be too far away for ordinary relative jumps and 1925 calls, and so in that case, module PLTs are required and cannot be 1926 disabled. 1927 1928 Specific errata workaround(s) might also force module PLTs to be 1929 enabled (ARM64_ERRATUM_843419). 1930 1931config ARM64_PSEUDO_NMI 1932 bool "Support for NMI-like interrupts" 1933 select ARM_GIC_V3 1934 help 1935 Adds support for mimicking Non-Maskable Interrupts through the use of 1936 GIC interrupt priority. This support requires version 3 or later of 1937 ARM GIC. 1938 1939 This high priority configuration for interrupts needs to be 1940 explicitly enabled by setting the kernel parameter 1941 "irqchip.gicv3_pseudo_nmi" to 1. 1942 1943 If unsure, say N 1944 1945if ARM64_PSEUDO_NMI 1946config ARM64_DEBUG_PRIORITY_MASKING 1947 bool "Debug interrupt priority masking" 1948 help 1949 This adds runtime checks to functions enabling/disabling 1950 interrupts when using priority masking. The additional checks verify 1951 the validity of ICC_PMR_EL1 when calling concerned functions. 1952 1953 If unsure, say N 1954endif 1955 1956config RELOCATABLE 1957 bool "Build a relocatable kernel image" if EXPERT 1958 select ARCH_HAS_RELR 1959 default y 1960 help 1961 This builds the kernel as a Position Independent Executable (PIE), 1962 which retains all relocation metadata required to relocate the 1963 kernel binary at runtime to a different virtual address than the 1964 address it was linked at. 1965 Since AArch64 uses the RELA relocation format, this requires a 1966 relocation pass at runtime even if the kernel is loaded at the 1967 same address it was linked at. 1968 1969config RANDOMIZE_BASE 1970 bool "Randomize the address of the kernel image" 1971 select ARM64_MODULE_PLTS if MODULES 1972 select RELOCATABLE 1973 help 1974 Randomizes the virtual address at which the kernel image is 1975 loaded, as a security feature that deters exploit attempts 1976 relying on knowledge of the location of kernel internals. 1977 1978 It is the bootloader's job to provide entropy, by passing a 1979 random u64 value in /chosen/kaslr-seed at kernel entry. 1980 1981 When booting via the UEFI stub, it will invoke the firmware's 1982 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1983 to the kernel proper. In addition, it will randomise the physical 1984 location of the kernel Image as well. 1985 1986 If unsure, say N. 1987 1988config RANDOMIZE_MODULE_REGION_FULL 1989 bool "Randomize the module region over a 2 GB range" 1990 depends on RANDOMIZE_BASE 1991 default y 1992 help 1993 Randomizes the location of the module region inside a 2 GB window 1994 covering the core kernel. This way, it is less likely for modules 1995 to leak information about the location of core kernel data structures 1996 but it does imply that function calls between modules and the core 1997 kernel will need to be resolved via veneers in the module PLT. 1998 1999 When this option is not set, the module region will be randomized over 2000 a limited range that contains the [_stext, _etext] interval of the 2001 core kernel, so branch relocations are almost always in range unless 2002 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2003 particular case of region exhaustion, modules might be able to fall 2004 back to a larger 2GB area. 2005 2006config CC_HAVE_STACKPROTECTOR_SYSREG 2007 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2008 2009config STACKPROTECTOR_PER_TASK 2010 def_bool y 2011 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2012 2013endmenu 2014 2015menu "Boot options" 2016 2017config ARM64_ACPI_PARKING_PROTOCOL 2018 bool "Enable support for the ARM64 ACPI parking protocol" 2019 depends on ACPI 2020 help 2021 Enable support for the ARM64 ACPI parking protocol. If disabled 2022 the kernel will not allow booting through the ARM64 ACPI parking 2023 protocol even if the corresponding data is present in the ACPI 2024 MADT table. 2025 2026config CMDLINE 2027 string "Default kernel command string" 2028 default "" 2029 help 2030 Provide a set of default command-line options at build time by 2031 entering them here. As a minimum, you should specify the the 2032 root device (e.g. root=/dev/nfs). 2033 2034choice 2035 prompt "Kernel command line type" if CMDLINE != "" 2036 default CMDLINE_FROM_BOOTLOADER 2037 help 2038 Choose how the kernel will handle the provided default kernel 2039 command line string. 2040 2041config CMDLINE_FROM_BOOTLOADER 2042 bool "Use bootloader kernel arguments if available" 2043 help 2044 Uses the command-line options passed by the boot loader. If 2045 the boot loader doesn't provide any, the default kernel command 2046 string provided in CMDLINE will be used. 2047 2048config CMDLINE_FORCE 2049 bool "Always use the default kernel command string" 2050 help 2051 Always use the default kernel command string, even if the boot 2052 loader passes other arguments to the kernel. 2053 This is useful if you cannot or don't want to change the 2054 command-line options your boot loader passes to the kernel. 2055 2056endchoice 2057 2058config EFI_STUB 2059 bool 2060 2061config EFI 2062 bool "UEFI runtime support" 2063 depends on OF && !CPU_BIG_ENDIAN 2064 depends on KERNEL_MODE_NEON 2065 select ARCH_SUPPORTS_ACPI 2066 select LIBFDT 2067 select UCS2_STRING 2068 select EFI_PARAMS_FROM_FDT 2069 select EFI_RUNTIME_WRAPPERS 2070 select EFI_STUB 2071 select EFI_GENERIC_STUB 2072 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2073 default y 2074 help 2075 This option provides support for runtime services provided 2076 by UEFI firmware (such as non-volatile variables, realtime 2077 clock, and platform reset). A UEFI stub is also provided to 2078 allow the kernel to be booted as an EFI application. This 2079 is only useful on systems that have UEFI firmware. 2080 2081config DMI 2082 bool "Enable support for SMBIOS (DMI) tables" 2083 depends on EFI 2084 default y 2085 help 2086 This enables SMBIOS/DMI feature for systems. 2087 2088 This option is only useful on systems that have UEFI firmware. 2089 However, even with this option, the resultant kernel should 2090 continue to boot on existing non-UEFI platforms. 2091 2092endmenu 2093 2094config SYSVIPC_COMPAT 2095 def_bool y 2096 depends on COMPAT && SYSVIPC 2097 2098menu "Power management options" 2099 2100source "kernel/power/Kconfig" 2101 2102config ARCH_HIBERNATION_POSSIBLE 2103 def_bool y 2104 depends on CPU_PM 2105 2106config ARCH_HIBERNATION_HEADER 2107 def_bool y 2108 depends on HIBERNATION 2109 2110config ARCH_SUSPEND_POSSIBLE 2111 def_bool y 2112 2113endmenu 2114 2115menu "CPU Power Management" 2116 2117source "drivers/cpuidle/Kconfig" 2118 2119source "drivers/cpufreq/Kconfig" 2120 2121endmenu 2122 2123source "drivers/acpi/Kconfig" 2124 2125source "arch/arm64/kvm/Kconfig" 2126 2127if CRYPTO 2128source "arch/arm64/crypto/Kconfig" 2129endif 2130