1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_VIRTUAL 13 select ARCH_HAS_DEVMEM_IS_ALLOWED 14 select ARCH_HAS_DMA_PREP_COHERENT 15 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 16 select ARCH_HAS_FAST_MULTIPLIER 17 select ARCH_HAS_FORTIFY_SOURCE 18 select ARCH_HAS_GCOV_PROFILE_ALL 19 select ARCH_HAS_GIGANTIC_PAGE 20 select ARCH_HAS_KCOV 21 select ARCH_HAS_KEEPINITRD 22 select ARCH_HAS_MEMBARRIER_SYNC_CORE 23 select ARCH_HAS_PTE_DEVMAP 24 select ARCH_HAS_PTE_SPECIAL 25 select ARCH_HAS_SETUP_DMA_OPS 26 select ARCH_HAS_SET_DIRECT_MAP 27 select ARCH_HAS_SET_MEMORY 28 select ARCH_HAS_STRICT_KERNEL_RWX 29 select ARCH_HAS_STRICT_MODULE_RWX 30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 31 select ARCH_HAS_SYNC_DMA_FOR_CPU 32 select ARCH_HAS_SYSCALL_WRAPPER 33 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 34 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 35 select ARCH_HAVE_NMI_SAFE_CMPXCHG 36 select ARCH_INLINE_READ_LOCK if !PREEMPTION 37 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 38 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 39 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 40 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 41 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 42 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 43 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 44 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 45 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 46 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 47 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 48 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 49 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 50 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 51 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 52 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 53 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 54 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 55 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 56 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 58 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 59 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 60 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 62 select ARCH_KEEP_MEMBLOCK 63 select ARCH_USE_CMPXCHG_LOCKREF 64 select ARCH_USE_QUEUED_RWLOCKS 65 select ARCH_USE_QUEUED_SPINLOCKS 66 select ARCH_SUPPORTS_MEMORY_FAILURE 67 select ARCH_SUPPORTS_ATOMIC_RMW 68 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG) 69 select ARCH_SUPPORTS_NUMA_BALANCING 70 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 71 select ARCH_WANT_DEFAULT_BPF_JIT 72 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 73 select ARCH_WANT_FRAME_POINTERS 74 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 75 select ARCH_HAS_UBSAN_SANITIZE_ALL 76 select ARM_AMBA 77 select ARM_ARCH_TIMER 78 select ARM_GIC 79 select AUDIT_ARCH_COMPAT_GENERIC 80 select ARM_GIC_V2M if PCI 81 select ARM_GIC_V3 82 select ARM_GIC_V3_ITS if PCI 83 select ARM_PSCI_FW 84 select BUILDTIME_TABLE_SORT 85 select CLONE_BACKWARDS 86 select COMMON_CLK 87 select CPU_PM if (SUSPEND || CPU_IDLE) 88 select CRC32 89 select DCACHE_WORD_ACCESS 90 select DMA_DIRECT_REMAP 91 select EDAC_SUPPORT 92 select FRAME_POINTER 93 select GENERIC_ALLOCATOR 94 select GENERIC_ARCH_TOPOLOGY 95 select GENERIC_CLOCKEVENTS 96 select GENERIC_CLOCKEVENTS_BROADCAST 97 select GENERIC_CPU_AUTOPROBE 98 select GENERIC_CPU_VULNERABILITIES 99 select GENERIC_EARLY_IOREMAP 100 select GENERIC_IDLE_POLL_SETUP 101 select GENERIC_IRQ_MULTI_HANDLER 102 select GENERIC_IRQ_PROBE 103 select GENERIC_IRQ_SHOW 104 select GENERIC_IRQ_SHOW_LEVEL 105 select GENERIC_PCI_IOMAP 106 select GENERIC_PTDUMP 107 select GENERIC_SCHED_CLOCK 108 select GENERIC_SMP_IDLE_THREAD 109 select GENERIC_STRNCPY_FROM_USER 110 select GENERIC_STRNLEN_USER 111 select GENERIC_TIME_VSYSCALL 112 select GENERIC_GETTIMEOFDAY 113 select HANDLE_DOMAIN_IRQ 114 select HARDIRQS_SW_RESEND 115 select HAVE_PCI 116 select HAVE_ACPI_APEI if (ACPI && EFI) 117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 118 select HAVE_ARCH_AUDITSYSCALL 119 select HAVE_ARCH_BITREVERSE 120 select HAVE_ARCH_HUGE_VMAP 121 select HAVE_ARCH_JUMP_LABEL 122 select HAVE_ARCH_JUMP_LABEL_RELATIVE 123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 125 select HAVE_ARCH_KGDB 126 select HAVE_ARCH_MMAP_RND_BITS 127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 128 select HAVE_ARCH_PREL32_RELOCATIONS 129 select HAVE_ARCH_SECCOMP_FILTER 130 select HAVE_ARCH_STACKLEAK 131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 132 select HAVE_ARCH_TRACEHOOK 133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 134 select HAVE_ARCH_VMAP_STACK 135 select HAVE_ARM_SMCCC 136 select HAVE_ASM_MODVERSIONS 137 select HAVE_EBPF_JIT 138 select HAVE_C_RECORDMCOUNT 139 select HAVE_CMPXCHG_DOUBLE 140 select HAVE_CMPXCHG_LOCAL 141 select HAVE_CONTEXT_TRACKING 142 select HAVE_COPY_THREAD_TLS 143 select HAVE_DEBUG_BUGVERBOSE 144 select HAVE_DEBUG_KMEMLEAK 145 select HAVE_DMA_CONTIGUOUS 146 select HAVE_DYNAMIC_FTRACE 147 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 148 if $(cc-option,-fpatchable-function-entry=2) 149 select HAVE_EFFICIENT_UNALIGNED_ACCESS 150 select HAVE_FAST_GUP 151 select HAVE_FTRACE_MCOUNT_RECORD 152 select HAVE_FUNCTION_TRACER 153 select HAVE_FUNCTION_ERROR_INJECTION 154 select HAVE_FUNCTION_GRAPH_TRACER 155 select HAVE_GCC_PLUGINS 156 select HAVE_HW_BREAKPOINT if PERF_EVENTS 157 select HAVE_IRQ_TIME_ACCOUNTING 158 select HAVE_MEMBLOCK_NODE_MAP if NUMA 159 select HAVE_NMI 160 select HAVE_PATA_PLATFORM 161 select HAVE_PERF_EVENTS 162 select HAVE_PERF_REGS 163 select HAVE_PERF_USER_STACK_DUMP 164 select HAVE_REGS_AND_STACK_ACCESS_API 165 select HAVE_FUNCTION_ARG_ACCESS_API 166 select HAVE_FUTEX_CMPXCHG if FUTEX 167 select MMU_GATHER_RCU_TABLE_FREE 168 select HAVE_RSEQ 169 select HAVE_STACKPROTECTOR 170 select HAVE_SYSCALL_TRACEPOINTS 171 select HAVE_KPROBES 172 select HAVE_KRETPROBES 173 select HAVE_GENERIC_VDSO 174 select IOMMU_DMA if IOMMU_SUPPORT 175 select IRQ_DOMAIN 176 select IRQ_FORCED_THREADING 177 select MODULES_USE_ELF_RELA 178 select NEED_DMA_MAP_STATE 179 select NEED_SG_DMA_LENGTH 180 select OF 181 select OF_EARLY_FLATTREE 182 select PCI_DOMAINS_GENERIC if PCI 183 select PCI_ECAM if (ACPI && PCI) 184 select PCI_SYSCALL if PCI 185 select POWER_RESET 186 select POWER_SUPPLY 187 select SPARSE_IRQ 188 select SWIOTLB 189 select SYSCTL_EXCEPTION_TRACE 190 select THREAD_INFO_IN_TASK 191 help 192 ARM 64-bit (AArch64) Linux support. 193 194config 64BIT 195 def_bool y 196 197config MMU 198 def_bool y 199 200config ARM64_PAGE_SHIFT 201 int 202 default 16 if ARM64_64K_PAGES 203 default 14 if ARM64_16K_PAGES 204 default 12 205 206config ARM64_CONT_SHIFT 207 int 208 default 5 if ARM64_64K_PAGES 209 default 7 if ARM64_16K_PAGES 210 default 4 211 212config ARCH_MMAP_RND_BITS_MIN 213 default 14 if ARM64_64K_PAGES 214 default 16 if ARM64_16K_PAGES 215 default 18 216 217# max bits determined by the following formula: 218# VA_BITS - PAGE_SHIFT - 3 219config ARCH_MMAP_RND_BITS_MAX 220 default 19 if ARM64_VA_BITS=36 221 default 24 if ARM64_VA_BITS=39 222 default 27 if ARM64_VA_BITS=42 223 default 30 if ARM64_VA_BITS=47 224 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 225 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 226 default 33 if ARM64_VA_BITS=48 227 default 14 if ARM64_64K_PAGES 228 default 16 if ARM64_16K_PAGES 229 default 18 230 231config ARCH_MMAP_RND_COMPAT_BITS_MIN 232 default 7 if ARM64_64K_PAGES 233 default 9 if ARM64_16K_PAGES 234 default 11 235 236config ARCH_MMAP_RND_COMPAT_BITS_MAX 237 default 16 238 239config NO_IOPORT_MAP 240 def_bool y if !PCI 241 242config STACKTRACE_SUPPORT 243 def_bool y 244 245config ILLEGAL_POINTER_VALUE 246 hex 247 default 0xdead000000000000 248 249config LOCKDEP_SUPPORT 250 def_bool y 251 252config TRACE_IRQFLAGS_SUPPORT 253 def_bool y 254 255config GENERIC_BUG 256 def_bool y 257 depends on BUG 258 259config GENERIC_BUG_RELATIVE_POINTERS 260 def_bool y 261 depends on GENERIC_BUG 262 263config GENERIC_HWEIGHT 264 def_bool y 265 266config GENERIC_CSUM 267 def_bool y 268 269config GENERIC_CALIBRATE_DELAY 270 def_bool y 271 272config ZONE_DMA 273 bool "Support DMA zone" if EXPERT 274 default y 275 276config ZONE_DMA32 277 bool "Support DMA32 zone" if EXPERT 278 default y 279 280config ARCH_ENABLE_MEMORY_HOTPLUG 281 def_bool y 282 283config SMP 284 def_bool y 285 286config KERNEL_MODE_NEON 287 def_bool y 288 289config FIX_EARLYCON_MEM 290 def_bool y 291 292config PGTABLE_LEVELS 293 int 294 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 295 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 296 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 297 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 298 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 299 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 300 301config ARCH_SUPPORTS_UPROBES 302 def_bool y 303 304config ARCH_PROC_KCORE_TEXT 305 def_bool y 306 307config BROKEN_GAS_INST 308 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 309 310config KASAN_SHADOW_OFFSET 311 hex 312 depends on KASAN 313 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 314 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 315 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 316 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 317 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 318 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 319 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 320 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 321 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 322 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 323 default 0xffffffffffffffff 324 325source "arch/arm64/Kconfig.platforms" 326 327menu "Kernel Features" 328 329menu "ARM errata workarounds via the alternatives framework" 330 331config ARM64_WORKAROUND_CLEAN_CACHE 332 bool 333 334config ARM64_ERRATUM_826319 335 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 336 default y 337 select ARM64_WORKAROUND_CLEAN_CACHE 338 help 339 This option adds an alternative code sequence to work around ARM 340 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 341 AXI master interface and an L2 cache. 342 343 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 344 and is unable to accept a certain write via this interface, it will 345 not progress on read data presented on the read data channel and the 346 system can deadlock. 347 348 The workaround promotes data cache clean instructions to 349 data cache clean-and-invalidate. 350 Please note that this does not necessarily enable the workaround, 351 as it depends on the alternative framework, which will only patch 352 the kernel if an affected CPU is detected. 353 354 If unsure, say Y. 355 356config ARM64_ERRATUM_827319 357 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 358 default y 359 select ARM64_WORKAROUND_CLEAN_CACHE 360 help 361 This option adds an alternative code sequence to work around ARM 362 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 363 master interface and an L2 cache. 364 365 Under certain conditions this erratum can cause a clean line eviction 366 to occur at the same time as another transaction to the same address 367 on the AMBA 5 CHI interface, which can cause data corruption if the 368 interconnect reorders the two transactions. 369 370 The workaround promotes data cache clean instructions to 371 data cache clean-and-invalidate. 372 Please note that this does not necessarily enable the workaround, 373 as it depends on the alternative framework, which will only patch 374 the kernel if an affected CPU is detected. 375 376 If unsure, say Y. 377 378config ARM64_ERRATUM_824069 379 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 380 default y 381 select ARM64_WORKAROUND_CLEAN_CACHE 382 help 383 This option adds an alternative code sequence to work around ARM 384 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 385 to a coherent interconnect. 386 387 If a Cortex-A53 processor is executing a store or prefetch for 388 write instruction at the same time as a processor in another 389 cluster is executing a cache maintenance operation to the same 390 address, then this erratum might cause a clean cache line to be 391 incorrectly marked as dirty. 392 393 The workaround promotes data cache clean instructions to 394 data cache clean-and-invalidate. 395 Please note that this option does not necessarily enable the 396 workaround, as it depends on the alternative framework, which will 397 only patch the kernel if an affected CPU is detected. 398 399 If unsure, say Y. 400 401config ARM64_ERRATUM_819472 402 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 403 default y 404 select ARM64_WORKAROUND_CLEAN_CACHE 405 help 406 This option adds an alternative code sequence to work around ARM 407 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 408 present when it is connected to a coherent interconnect. 409 410 If the processor is executing a load and store exclusive sequence at 411 the same time as a processor in another cluster is executing a cache 412 maintenance operation to the same address, then this erratum might 413 cause data corruption. 414 415 The workaround promotes data cache clean instructions to 416 data cache clean-and-invalidate. 417 Please note that this does not necessarily enable the workaround, 418 as it depends on the alternative framework, which will only patch 419 the kernel if an affected CPU is detected. 420 421 If unsure, say Y. 422 423config ARM64_ERRATUM_832075 424 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 425 default y 426 help 427 This option adds an alternative code sequence to work around ARM 428 erratum 832075 on Cortex-A57 parts up to r1p2. 429 430 Affected Cortex-A57 parts might deadlock when exclusive load/store 431 instructions to Write-Back memory are mixed with Device loads. 432 433 The workaround is to promote device loads to use Load-Acquire 434 semantics. 435 Please note that this does not necessarily enable the workaround, 436 as it depends on the alternative framework, which will only patch 437 the kernel if an affected CPU is detected. 438 439 If unsure, say Y. 440 441config ARM64_ERRATUM_834220 442 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 443 depends on KVM 444 default y 445 help 446 This option adds an alternative code sequence to work around ARM 447 erratum 834220 on Cortex-A57 parts up to r1p2. 448 449 Affected Cortex-A57 parts might report a Stage 2 translation 450 fault as the result of a Stage 1 fault for load crossing a 451 page boundary when there is a permission or device memory 452 alignment fault at Stage 1 and a translation fault at Stage 2. 453 454 The workaround is to verify that the Stage 1 translation 455 doesn't generate a fault before handling the Stage 2 fault. 456 Please note that this does not necessarily enable the workaround, 457 as it depends on the alternative framework, which will only patch 458 the kernel if an affected CPU is detected. 459 460 If unsure, say Y. 461 462config ARM64_ERRATUM_845719 463 bool "Cortex-A53: 845719: a load might read incorrect data" 464 depends on COMPAT 465 default y 466 help 467 This option adds an alternative code sequence to work around ARM 468 erratum 845719 on Cortex-A53 parts up to r0p4. 469 470 When running a compat (AArch32) userspace on an affected Cortex-A53 471 part, a load at EL0 from a virtual address that matches the bottom 32 472 bits of the virtual address used by a recent load at (AArch64) EL1 473 might return incorrect data. 474 475 The workaround is to write the contextidr_el1 register on exception 476 return to a 32-bit task. 477 Please note that this does not necessarily enable the workaround, 478 as it depends on the alternative framework, which will only patch 479 the kernel if an affected CPU is detected. 480 481 If unsure, say Y. 482 483config ARM64_ERRATUM_843419 484 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 485 default y 486 select ARM64_MODULE_PLTS if MODULES 487 help 488 This option links the kernel with '--fix-cortex-a53-843419' and 489 enables PLT support to replace certain ADRP instructions, which can 490 cause subsequent memory accesses to use an incorrect address on 491 Cortex-A53 parts up to r0p4. 492 493 If unsure, say Y. 494 495config ARM64_ERRATUM_1024718 496 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 497 default y 498 help 499 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 500 501 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect 502 update of the hardware dirty bit when the DBM/AP bits are updated 503 without a break-before-make. The workaround is to disable the usage 504 of hardware DBM locally on the affected cores. CPUs not affected by 505 this erratum will continue to use the feature. 506 507 If unsure, say Y. 508 509config ARM64_ERRATUM_1418040 510 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 511 default y 512 depends on COMPAT 513 help 514 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 515 errata 1188873 and 1418040. 516 517 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 518 cause register corruption when accessing the timer registers 519 from AArch32 userspace. 520 521 If unsure, say Y. 522 523config ARM64_WORKAROUND_SPECULATIVE_AT_VHE 524 bool 525 526config ARM64_ERRATUM_1165522 527 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 528 default y 529 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE 530 help 531 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 532 533 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 534 corrupted TLBs by speculating an AT instruction during a guest 535 context switch. 536 537 If unsure, say Y. 538 539config ARM64_ERRATUM_1530923 540 bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 541 default y 542 select ARM64_WORKAROUND_SPECULATIVE_AT_VHE 543 help 544 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 545 546 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 547 corrupted TLBs by speculating an AT instruction during a guest 548 context switch. 549 550 If unsure, say Y. 551 552config ARM64_ERRATUM_1286807 553 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 554 default y 555 select ARM64_WORKAROUND_REPEAT_TLBI 556 help 557 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 558 559 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 560 address for a cacheable mapping of a location is being 561 accessed by a core while another core is remapping the virtual 562 address to a new physical page using the recommended 563 break-before-make sequence, then under very rare circumstances 564 TLBI+DSB completes before a read using the translation being 565 invalidated has been observed by other observers. The 566 workaround repeats the TLBI+DSB operation. 567 568config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 569 bool 570 571config ARM64_ERRATUM_1319367 572 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 573 default y 574 select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 575 help 576 This option adds work arounds for ARM Cortex-A57 erratum 1319537 577 and A72 erratum 1319367 578 579 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 580 speculating an AT instruction during a guest context switch. 581 582 If unsure, say Y. 583 584config ARM64_ERRATUM_1463225 585 bool "Cortex-A76: Software Step might prevent interrupt recognition" 586 default y 587 help 588 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 589 590 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 591 of a system call instruction (SVC) can prevent recognition of 592 subsequent interrupts when software stepping is disabled in the 593 exception handler of the system call and either kernel debugging 594 is enabled or VHE is in use. 595 596 Work around the erratum by triggering a dummy step exception 597 when handling a system call from a task that is being stepped 598 in a VHE configuration of the kernel. 599 600 If unsure, say Y. 601 602config ARM64_ERRATUM_1542419 603 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 604 default y 605 help 606 This option adds a workaround for ARM Neoverse-N1 erratum 607 1542419. 608 609 Affected Neoverse-N1 cores could execute a stale instruction when 610 modified by another CPU. The workaround depends on a firmware 611 counterpart. 612 613 Workaround the issue by hiding the DIC feature from EL0. This 614 forces user-space to perform cache maintenance. 615 616 If unsure, say Y. 617 618config CAVIUM_ERRATUM_22375 619 bool "Cavium erratum 22375, 24313" 620 default y 621 help 622 Enable workaround for errata 22375 and 24313. 623 624 This implements two gicv3-its errata workarounds for ThunderX. Both 625 with a small impact affecting only ITS table allocation. 626 627 erratum 22375: only alloc 8MB table size 628 erratum 24313: ignore memory access type 629 630 The fixes are in ITS initialization and basically ignore memory access 631 type and table size provided by the TYPER and BASER registers. 632 633 If unsure, say Y. 634 635config CAVIUM_ERRATUM_23144 636 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 637 depends on NUMA 638 default y 639 help 640 ITS SYNC command hang for cross node io and collections/cpu mapping. 641 642 If unsure, say Y. 643 644config CAVIUM_ERRATUM_23154 645 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 646 default y 647 help 648 The gicv3 of ThunderX requires a modified version for 649 reading the IAR status to ensure data synchronization 650 (access to icc_iar1_el1 is not sync'ed before and after). 651 652 If unsure, say Y. 653 654config CAVIUM_ERRATUM_27456 655 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 656 default y 657 help 658 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 659 instructions may cause the icache to become corrupted if it 660 contains data for a non-current ASID. The fix is to 661 invalidate the icache when changing the mm context. 662 663 If unsure, say Y. 664 665config CAVIUM_ERRATUM_30115 666 bool "Cavium erratum 30115: Guest may disable interrupts in host" 667 default y 668 help 669 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 670 1.2, and T83 Pass 1.0, KVM guest execution may disable 671 interrupts in host. Trapping both GICv3 group-0 and group-1 672 accesses sidesteps the issue. 673 674 If unsure, say Y. 675 676config CAVIUM_TX2_ERRATUM_219 677 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 678 default y 679 help 680 On Cavium ThunderX2, a load, store or prefetch instruction between a 681 TTBR update and the corresponding context synchronizing operation can 682 cause a spurious Data Abort to be delivered to any hardware thread in 683 the CPU core. 684 685 Work around the issue by avoiding the problematic code sequence and 686 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 687 trap handler performs the corresponding register access, skips the 688 instruction and ensures context synchronization by virtue of the 689 exception return. 690 691 If unsure, say Y. 692 693config QCOM_FALKOR_ERRATUM_1003 694 bool "Falkor E1003: Incorrect translation due to ASID change" 695 default y 696 help 697 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 698 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 699 in TTBR1_EL1, this situation only occurs in the entry trampoline and 700 then only for entries in the walk cache, since the leaf translation 701 is unchanged. Work around the erratum by invalidating the walk cache 702 entries for the trampoline before entering the kernel proper. 703 704config ARM64_WORKAROUND_REPEAT_TLBI 705 bool 706 707config QCOM_FALKOR_ERRATUM_1009 708 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 709 default y 710 select ARM64_WORKAROUND_REPEAT_TLBI 711 help 712 On Falkor v1, the CPU may prematurely complete a DSB following a 713 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 714 one more time to fix the issue. 715 716 If unsure, say Y. 717 718config QCOM_QDF2400_ERRATUM_0065 719 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 720 default y 721 help 722 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 723 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 724 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 725 726 If unsure, say Y. 727 728config SOCIONEXT_SYNQUACER_PREITS 729 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 730 default y 731 help 732 Socionext Synquacer SoCs implement a separate h/w block to generate 733 MSI doorbell writes with non-zero values for the device ID. 734 735 If unsure, say Y. 736 737config HISILICON_ERRATUM_161600802 738 bool "Hip07 161600802: Erroneous redistributor VLPI base" 739 default y 740 help 741 The HiSilicon Hip07 SoC uses the wrong redistributor base 742 when issued ITS commands such as VMOVP and VMAPP, and requires 743 a 128kB offset to be applied to the target address in this commands. 744 745 If unsure, say Y. 746 747config QCOM_FALKOR_ERRATUM_E1041 748 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 749 default y 750 help 751 Falkor CPU may speculatively fetch instructions from an improper 752 memory location when MMU translation is changed from SCTLR_ELn[M]=1 753 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 754 755 If unsure, say Y. 756 757config FUJITSU_ERRATUM_010001 758 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 759 default y 760 help 761 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 762 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 763 accesses may cause undefined fault (Data abort, DFSC=0b111111). 764 This fault occurs under a specific hardware condition when a 765 load/store instruction performs an address translation using: 766 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 767 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 768 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 769 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 770 771 The workaround is to ensure these bits are clear in TCR_ELx. 772 The workaround only affects the Fujitsu-A64FX. 773 774 If unsure, say Y. 775 776endmenu 777 778 779choice 780 prompt "Page size" 781 default ARM64_4K_PAGES 782 help 783 Page size (translation granule) configuration. 784 785config ARM64_4K_PAGES 786 bool "4KB" 787 help 788 This feature enables 4KB pages support. 789 790config ARM64_16K_PAGES 791 bool "16KB" 792 help 793 The system will use 16KB pages support. AArch32 emulation 794 requires applications compiled with 16K (or a multiple of 16K) 795 aligned segments. 796 797config ARM64_64K_PAGES 798 bool "64KB" 799 help 800 This feature enables 64KB pages support (4KB by default) 801 allowing only two levels of page tables and faster TLB 802 look-up. AArch32 emulation requires applications compiled 803 with 64K aligned segments. 804 805endchoice 806 807choice 808 prompt "Virtual address space size" 809 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 810 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 811 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 812 help 813 Allows choosing one of multiple possible virtual address 814 space sizes. The level of translation table is determined by 815 a combination of page size and virtual address space size. 816 817config ARM64_VA_BITS_36 818 bool "36-bit" if EXPERT 819 depends on ARM64_16K_PAGES 820 821config ARM64_VA_BITS_39 822 bool "39-bit" 823 depends on ARM64_4K_PAGES 824 825config ARM64_VA_BITS_42 826 bool "42-bit" 827 depends on ARM64_64K_PAGES 828 829config ARM64_VA_BITS_47 830 bool "47-bit" 831 depends on ARM64_16K_PAGES 832 833config ARM64_VA_BITS_48 834 bool "48-bit" 835 836config ARM64_VA_BITS_52 837 bool "52-bit" 838 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 839 help 840 Enable 52-bit virtual addressing for userspace when explicitly 841 requested via a hint to mmap(). The kernel will also use 52-bit 842 virtual addresses for its own mappings (provided HW support for 843 this feature is available, otherwise it reverts to 48-bit). 844 845 NOTE: Enabling 52-bit virtual addressing in conjunction with 846 ARMv8.3 Pointer Authentication will result in the PAC being 847 reduced from 7 bits to 3 bits, which may have a significant 848 impact on its susceptibility to brute-force attacks. 849 850 If unsure, select 48-bit virtual addressing instead. 851 852endchoice 853 854config ARM64_FORCE_52BIT 855 bool "Force 52-bit virtual addresses for userspace" 856 depends on ARM64_VA_BITS_52 && EXPERT 857 help 858 For systems with 52-bit userspace VAs enabled, the kernel will attempt 859 to maintain compatibility with older software by providing 48-bit VAs 860 unless a hint is supplied to mmap. 861 862 This configuration option disables the 48-bit compatibility logic, and 863 forces all userspace addresses to be 52-bit on HW that supports it. One 864 should only enable this configuration option for stress testing userspace 865 memory management code. If unsure say N here. 866 867config ARM64_VA_BITS 868 int 869 default 36 if ARM64_VA_BITS_36 870 default 39 if ARM64_VA_BITS_39 871 default 42 if ARM64_VA_BITS_42 872 default 47 if ARM64_VA_BITS_47 873 default 48 if ARM64_VA_BITS_48 874 default 52 if ARM64_VA_BITS_52 875 876choice 877 prompt "Physical address space size" 878 default ARM64_PA_BITS_48 879 help 880 Choose the maximum physical address range that the kernel will 881 support. 882 883config ARM64_PA_BITS_48 884 bool "48-bit" 885 886config ARM64_PA_BITS_52 887 bool "52-bit (ARMv8.2)" 888 depends on ARM64_64K_PAGES 889 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 890 help 891 Enable support for a 52-bit physical address space, introduced as 892 part of the ARMv8.2-LPA extension. 893 894 With this enabled, the kernel will also continue to work on CPUs that 895 do not support ARMv8.2-LPA, but with some added memory overhead (and 896 minor performance overhead). 897 898endchoice 899 900config ARM64_PA_BITS 901 int 902 default 48 if ARM64_PA_BITS_48 903 default 52 if ARM64_PA_BITS_52 904 905choice 906 prompt "Endianness" 907 default CPU_LITTLE_ENDIAN 908 help 909 Select the endianness of data accesses performed by the CPU. Userspace 910 applications will need to be compiled and linked for the endianness 911 that is selected here. 912 913config CPU_BIG_ENDIAN 914 bool "Build big-endian kernel" 915 help 916 Say Y if you plan on running a kernel with a big-endian userspace. 917 918config CPU_LITTLE_ENDIAN 919 bool "Build little-endian kernel" 920 help 921 Say Y if you plan on running a kernel with a little-endian userspace. 922 This is usually the case for distributions targeting arm64. 923 924endchoice 925 926config SCHED_MC 927 bool "Multi-core scheduler support" 928 help 929 Multi-core scheduler support improves the CPU scheduler's decision 930 making when dealing with multi-core CPU chips at a cost of slightly 931 increased overhead in some places. If unsure say N here. 932 933config SCHED_SMT 934 bool "SMT scheduler support" 935 help 936 Improves the CPU scheduler's decision making when dealing with 937 MultiThreading at a cost of slightly increased overhead in some 938 places. If unsure say N here. 939 940config NR_CPUS 941 int "Maximum number of CPUs (2-4096)" 942 range 2 4096 943 default "256" 944 945config HOTPLUG_CPU 946 bool "Support for hot-pluggable CPUs" 947 select GENERIC_IRQ_MIGRATION 948 help 949 Say Y here to experiment with turning CPUs off and on. CPUs 950 can be controlled through /sys/devices/system/cpu. 951 952# Common NUMA Features 953config NUMA 954 bool "Numa Memory Allocation and Scheduler Support" 955 select ACPI_NUMA if ACPI 956 select OF_NUMA 957 help 958 Enable NUMA (Non Uniform Memory Access) support. 959 960 The kernel will try to allocate memory used by a CPU on the 961 local memory of the CPU and add some more 962 NUMA awareness to the kernel. 963 964config NODES_SHIFT 965 int "Maximum NUMA Nodes (as a power of 2)" 966 range 1 10 967 default "2" 968 depends on NEED_MULTIPLE_NODES 969 help 970 Specify the maximum number of NUMA Nodes available on the target 971 system. Increases memory reserved to accommodate various tables. 972 973config USE_PERCPU_NUMA_NODE_ID 974 def_bool y 975 depends on NUMA 976 977config HAVE_SETUP_PER_CPU_AREA 978 def_bool y 979 depends on NUMA 980 981config NEED_PER_CPU_EMBED_FIRST_CHUNK 982 def_bool y 983 depends on NUMA 984 985config HOLES_IN_ZONE 986 def_bool y 987 988source "kernel/Kconfig.hz" 989 990config ARCH_SUPPORTS_DEBUG_PAGEALLOC 991 def_bool y 992 993config ARCH_SPARSEMEM_ENABLE 994 def_bool y 995 select SPARSEMEM_VMEMMAP_ENABLE 996 997config ARCH_SPARSEMEM_DEFAULT 998 def_bool ARCH_SPARSEMEM_ENABLE 999 1000config ARCH_SELECT_MEMORY_MODEL 1001 def_bool ARCH_SPARSEMEM_ENABLE 1002 1003config ARCH_FLATMEM_ENABLE 1004 def_bool !NUMA 1005 1006config HAVE_ARCH_PFN_VALID 1007 def_bool y 1008 1009config HW_PERF_EVENTS 1010 def_bool y 1011 depends on ARM_PMU 1012 1013config SYS_SUPPORTS_HUGETLBFS 1014 def_bool y 1015 1016config ARCH_WANT_HUGE_PMD_SHARE 1017 1018config ARCH_HAS_CACHE_LINE_SIZE 1019 def_bool y 1020 1021config ARCH_ENABLE_SPLIT_PMD_PTLOCK 1022 def_bool y if PGTABLE_LEVELS > 2 1023 1024config SECCOMP 1025 bool "Enable seccomp to safely compute untrusted bytecode" 1026 ---help--- 1027 This kernel feature is useful for number crunching applications 1028 that may need to compute untrusted bytecode during their 1029 execution. By using pipes or other transports made available to 1030 the process as file descriptors supporting the read/write 1031 syscalls, it's possible to isolate those applications in 1032 their own address space using seccomp. Once seccomp is 1033 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1034 and the task is only allowed to execute a few safe syscalls 1035 defined by each seccomp mode. 1036 1037config PARAVIRT 1038 bool "Enable paravirtualization code" 1039 help 1040 This changes the kernel so it can modify itself when it is run 1041 under a hypervisor, potentially improving performance significantly 1042 over full virtualization. 1043 1044config PARAVIRT_TIME_ACCOUNTING 1045 bool "Paravirtual steal time accounting" 1046 select PARAVIRT 1047 help 1048 Select this option to enable fine granularity task steal time 1049 accounting. Time spent executing other tasks in parallel with 1050 the current vCPU is discounted from the vCPU power. To account for 1051 that, there can be a small performance impact. 1052 1053 If in doubt, say N here. 1054 1055config KEXEC 1056 depends on PM_SLEEP_SMP 1057 select KEXEC_CORE 1058 bool "kexec system call" 1059 ---help--- 1060 kexec is a system call that implements the ability to shutdown your 1061 current kernel, and to start another kernel. It is like a reboot 1062 but it is independent of the system firmware. And like a reboot 1063 you can start any kernel with it, not just Linux. 1064 1065config KEXEC_FILE 1066 bool "kexec file based system call" 1067 select KEXEC_CORE 1068 help 1069 This is new version of kexec system call. This system call is 1070 file based and takes file descriptors as system call argument 1071 for kernel and initramfs as opposed to list of segments as 1072 accepted by previous system call. 1073 1074config KEXEC_SIG 1075 bool "Verify kernel signature during kexec_file_load() syscall" 1076 depends on KEXEC_FILE 1077 help 1078 Select this option to verify a signature with loaded kernel 1079 image. If configured, any attempt of loading a image without 1080 valid signature will fail. 1081 1082 In addition to that option, you need to enable signature 1083 verification for the corresponding kernel image type being 1084 loaded in order for this to work. 1085 1086config KEXEC_IMAGE_VERIFY_SIG 1087 bool "Enable Image signature verification support" 1088 default y 1089 depends on KEXEC_SIG 1090 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1091 help 1092 Enable Image signature verification support. 1093 1094comment "Support for PE file signature verification disabled" 1095 depends on KEXEC_SIG 1096 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1097 1098config CRASH_DUMP 1099 bool "Build kdump crash kernel" 1100 help 1101 Generate crash dump after being started by kexec. This should 1102 be normally only set in special crash dump kernels which are 1103 loaded in the main kernel with kexec-tools into a specially 1104 reserved region and then later executed after a crash by 1105 kdump/kexec. 1106 1107 For more details see Documentation/admin-guide/kdump/kdump.rst 1108 1109config XEN_DOM0 1110 def_bool y 1111 depends on XEN 1112 1113config XEN 1114 bool "Xen guest support on ARM64" 1115 depends on ARM64 && OF 1116 select SWIOTLB_XEN 1117 select PARAVIRT 1118 help 1119 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1120 1121config FORCE_MAX_ZONEORDER 1122 int 1123 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 1124 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 1125 default "11" 1126 help 1127 The kernel memory allocator divides physically contiguous memory 1128 blocks into "zones", where each zone is a power of two number of 1129 pages. This option selects the largest power of two that the kernel 1130 keeps in the memory allocator. If you need to allocate very large 1131 blocks of physically contiguous memory, then you may need to 1132 increase this value. 1133 1134 This config option is actually maximum order plus one. For example, 1135 a value of 11 means that the largest free memory block is 2^10 pages. 1136 1137 We make sure that we can allocate upto a HugePage size for each configuration. 1138 Hence we have : 1139 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1140 1141 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1142 4M allocations matching the default size used by generic code. 1143 1144config UNMAP_KERNEL_AT_EL0 1145 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1146 default y 1147 help 1148 Speculation attacks against some high-performance processors can 1149 be used to bypass MMU permission checks and leak kernel data to 1150 userspace. This can be defended against by unmapping the kernel 1151 when running in userspace, mapping it back in on exception entry 1152 via a trampoline page in the vector table. 1153 1154 If unsure, say Y. 1155 1156config HARDEN_BRANCH_PREDICTOR 1157 bool "Harden the branch predictor against aliasing attacks" if EXPERT 1158 default y 1159 help 1160 Speculation attacks against some high-performance processors rely on 1161 being able to manipulate the branch predictor for a victim context by 1162 executing aliasing branches in the attacker context. Such attacks 1163 can be partially mitigated against by clearing internal branch 1164 predictor state and limiting the prediction logic in some situations. 1165 1166 This config option will take CPU-specific actions to harden the 1167 branch predictor against aliasing attacks and may rely on specific 1168 instruction sequences or control bits being set by the system 1169 firmware. 1170 1171 If unsure, say Y. 1172 1173config HARDEN_EL2_VECTORS 1174 bool "Harden EL2 vector mapping against system register leak" if EXPERT 1175 default y 1176 help 1177 Speculation attacks against some high-performance processors can 1178 be used to leak privileged information such as the vector base 1179 register, resulting in a potential defeat of the EL2 layout 1180 randomization. 1181 1182 This config option will map the vectors to a fixed location, 1183 independent of the EL2 code mapping, so that revealing VBAR_EL2 1184 to an attacker does not give away any extra information. This 1185 only gets enabled on affected CPUs. 1186 1187 If unsure, say Y. 1188 1189config ARM64_SSBD 1190 bool "Speculative Store Bypass Disable" if EXPERT 1191 default y 1192 help 1193 This enables mitigation of the bypassing of previous stores 1194 by speculative loads. 1195 1196 If unsure, say Y. 1197 1198config RODATA_FULL_DEFAULT_ENABLED 1199 bool "Apply r/o permissions of VM areas also to their linear aliases" 1200 default y 1201 help 1202 Apply read-only attributes of VM areas to the linear alias of 1203 the backing pages as well. This prevents code or read-only data 1204 from being modified (inadvertently or intentionally) via another 1205 mapping of the same memory page. This additional enhancement can 1206 be turned off at runtime by passing rodata=[off|on] (and turned on 1207 with rodata=full if this option is set to 'n') 1208 1209 This requires the linear region to be mapped down to pages, 1210 which may adversely affect performance in some cases. 1211 1212config ARM64_SW_TTBR0_PAN 1213 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1214 help 1215 Enabling this option prevents the kernel from accessing 1216 user-space memory directly by pointing TTBR0_EL1 to a reserved 1217 zeroed area and reserved ASID. The user access routines 1218 restore the valid TTBR0_EL1 temporarily. 1219 1220config ARM64_TAGGED_ADDR_ABI 1221 bool "Enable the tagged user addresses syscall ABI" 1222 default y 1223 help 1224 When this option is enabled, user applications can opt in to a 1225 relaxed ABI via prctl() allowing tagged addresses to be passed 1226 to system calls as pointer arguments. For details, see 1227 Documentation/arm64/tagged-address-abi.rst. 1228 1229menuconfig COMPAT 1230 bool "Kernel support for 32-bit EL0" 1231 depends on ARM64_4K_PAGES || EXPERT 1232 select COMPAT_BINFMT_ELF if BINFMT_ELF 1233 select HAVE_UID16 1234 select OLD_SIGSUSPEND3 1235 select COMPAT_OLD_SIGACTION 1236 help 1237 This option enables support for a 32-bit EL0 running under a 64-bit 1238 kernel at EL1. AArch32-specific components such as system calls, 1239 the user helper functions, VFP support and the ptrace interface are 1240 handled appropriately by the kernel. 1241 1242 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1243 that you will only be able to execute AArch32 binaries that were compiled 1244 with page size aligned segments. 1245 1246 If you want to execute 32-bit userspace applications, say Y. 1247 1248if COMPAT 1249 1250config KUSER_HELPERS 1251 bool "Enable kuser helpers page for 32-bit applications" 1252 default y 1253 help 1254 Warning: disabling this option may break 32-bit user programs. 1255 1256 Provide kuser helpers to compat tasks. The kernel provides 1257 helper code to userspace in read only form at a fixed location 1258 to allow userspace to be independent of the CPU type fitted to 1259 the system. This permits binaries to be run on ARMv4 through 1260 to ARMv8 without modification. 1261 1262 See Documentation/arm/kernel_user_helpers.rst for details. 1263 1264 However, the fixed address nature of these helpers can be used 1265 by ROP (return orientated programming) authors when creating 1266 exploits. 1267 1268 If all of the binaries and libraries which run on your platform 1269 are built specifically for your platform, and make no use of 1270 these helpers, then you can turn this option off to hinder 1271 such exploits. However, in that case, if a binary or library 1272 relying on those helpers is run, it will not function correctly. 1273 1274 Say N here only if you are absolutely certain that you do not 1275 need these helpers; otherwise, the safe option is to say Y. 1276 1277config COMPAT_VDSO 1278 bool "Enable vDSO for 32-bit applications" 1279 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != "" 1280 select GENERIC_COMPAT_VDSO 1281 default y 1282 help 1283 Place in the process address space of 32-bit applications an 1284 ELF shared object providing fast implementations of gettimeofday 1285 and clock_gettime. 1286 1287 You must have a 32-bit build of glibc 2.22 or later for programs 1288 to seamlessly take advantage of this. 1289 1290menuconfig ARMV8_DEPRECATED 1291 bool "Emulate deprecated/obsolete ARMv8 instructions" 1292 depends on SYSCTL 1293 help 1294 Legacy software support may require certain instructions 1295 that have been deprecated or obsoleted in the architecture. 1296 1297 Enable this config to enable selective emulation of these 1298 features. 1299 1300 If unsure, say Y 1301 1302if ARMV8_DEPRECATED 1303 1304config SWP_EMULATION 1305 bool "Emulate SWP/SWPB instructions" 1306 help 1307 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1308 they are always undefined. Say Y here to enable software 1309 emulation of these instructions for userspace using LDXR/STXR. 1310 1311 In some older versions of glibc [<=2.8] SWP is used during futex 1312 trylock() operations with the assumption that the code will not 1313 be preempted. This invalid assumption may be more likely to fail 1314 with SWP emulation enabled, leading to deadlock of the user 1315 application. 1316 1317 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1318 on an external transaction monitoring block called a global 1319 monitor to maintain update atomicity. If your system does not 1320 implement a global monitor, this option can cause programs that 1321 perform SWP operations to uncached memory to deadlock. 1322 1323 If unsure, say Y 1324 1325config CP15_BARRIER_EMULATION 1326 bool "Emulate CP15 Barrier instructions" 1327 help 1328 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1329 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1330 strongly recommended to use the ISB, DSB, and DMB 1331 instructions instead. 1332 1333 Say Y here to enable software emulation of these 1334 instructions for AArch32 userspace code. When this option is 1335 enabled, CP15 barrier usage is traced which can help 1336 identify software that needs updating. 1337 1338 If unsure, say Y 1339 1340config SETEND_EMULATION 1341 bool "Emulate SETEND instruction" 1342 help 1343 The SETEND instruction alters the data-endianness of the 1344 AArch32 EL0, and is deprecated in ARMv8. 1345 1346 Say Y here to enable software emulation of the instruction 1347 for AArch32 userspace code. 1348 1349 Note: All the cpus on the system must have mixed endian support at EL0 1350 for this feature to be enabled. If a new CPU - which doesn't support mixed 1351 endian - is hotplugged in after this feature has been enabled, there could 1352 be unexpected results in the applications. 1353 1354 If unsure, say Y 1355endif 1356 1357endif 1358 1359menu "ARMv8.1 architectural features" 1360 1361config ARM64_HW_AFDBM 1362 bool "Support for hardware updates of the Access and Dirty page flags" 1363 default y 1364 help 1365 The ARMv8.1 architecture extensions introduce support for 1366 hardware updates of the access and dirty information in page 1367 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1368 capable processors, accesses to pages with PTE_AF cleared will 1369 set this bit instead of raising an access flag fault. 1370 Similarly, writes to read-only pages with the DBM bit set will 1371 clear the read-only bit (AP[2]) instead of raising a 1372 permission fault. 1373 1374 Kernels built with this configuration option enabled continue 1375 to work on pre-ARMv8.1 hardware and the performance impact is 1376 minimal. If unsure, say Y. 1377 1378config ARM64_PAN 1379 bool "Enable support for Privileged Access Never (PAN)" 1380 default y 1381 help 1382 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1383 prevents the kernel or hypervisor from accessing user-space (EL0) 1384 memory directly. 1385 1386 Choosing this option will cause any unprotected (not using 1387 copy_to_user et al) memory access to fail with a permission fault. 1388 1389 The feature is detected at runtime, and will remain as a 'nop' 1390 instruction if the cpu does not implement the feature. 1391 1392config ARM64_LSE_ATOMICS 1393 bool 1394 default ARM64_USE_LSE_ATOMICS 1395 depends on $(as-instr,.arch_extension lse) 1396 1397config ARM64_USE_LSE_ATOMICS 1398 bool "Atomic instructions" 1399 depends on JUMP_LABEL 1400 default y 1401 help 1402 As part of the Large System Extensions, ARMv8.1 introduces new 1403 atomic instructions that are designed specifically to scale in 1404 very large systems. 1405 1406 Say Y here to make use of these instructions for the in-kernel 1407 atomic routines. This incurs a small overhead on CPUs that do 1408 not support these instructions and requires the kernel to be 1409 built with binutils >= 2.25 in order for the new instructions 1410 to be used. 1411 1412config ARM64_VHE 1413 bool "Enable support for Virtualization Host Extensions (VHE)" 1414 default y 1415 help 1416 Virtualization Host Extensions (VHE) allow the kernel to run 1417 directly at EL2 (instead of EL1) on processors that support 1418 it. This leads to better performance for KVM, as they reduce 1419 the cost of the world switch. 1420 1421 Selecting this option allows the VHE feature to be detected 1422 at runtime, and does not affect processors that do not 1423 implement this feature. 1424 1425endmenu 1426 1427menu "ARMv8.2 architectural features" 1428 1429config ARM64_UAO 1430 bool "Enable support for User Access Override (UAO)" 1431 default y 1432 help 1433 User Access Override (UAO; part of the ARMv8.2 Extensions) 1434 causes the 'unprivileged' variant of the load/store instructions to 1435 be overridden to be privileged. 1436 1437 This option changes get_user() and friends to use the 'unprivileged' 1438 variant of the load/store instructions. This ensures that user-space 1439 really did have access to the supplied memory. When addr_limit is 1440 set to kernel memory the UAO bit will be set, allowing privileged 1441 access to kernel memory. 1442 1443 Choosing this option will cause copy_to_user() et al to use user-space 1444 memory permissions. 1445 1446 The feature is detected at runtime, the kernel will use the 1447 regular load/store instructions if the cpu does not implement the 1448 feature. 1449 1450config ARM64_PMEM 1451 bool "Enable support for persistent memory" 1452 select ARCH_HAS_PMEM_API 1453 select ARCH_HAS_UACCESS_FLUSHCACHE 1454 help 1455 Say Y to enable support for the persistent memory API based on the 1456 ARMv8.2 DCPoP feature. 1457 1458 The feature is detected at runtime, and the kernel will use DC CVAC 1459 operations if DC CVAP is not supported (following the behaviour of 1460 DC CVAP itself if the system does not define a point of persistence). 1461 1462config ARM64_RAS_EXTN 1463 bool "Enable support for RAS CPU Extensions" 1464 default y 1465 help 1466 CPUs that support the Reliability, Availability and Serviceability 1467 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1468 errors, classify them and report them to software. 1469 1470 On CPUs with these extensions system software can use additional 1471 barriers to determine if faults are pending and read the 1472 classification from a new set of registers. 1473 1474 Selecting this feature will allow the kernel to use these barriers 1475 and access the new registers if the system supports the extension. 1476 Platform RAS features may additionally depend on firmware support. 1477 1478config ARM64_CNP 1479 bool "Enable support for Common Not Private (CNP) translations" 1480 default y 1481 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1482 help 1483 Common Not Private (CNP) allows translation table entries to 1484 be shared between different PEs in the same inner shareable 1485 domain, so the hardware can use this fact to optimise the 1486 caching of such entries in the TLB. 1487 1488 Selecting this option allows the CNP feature to be detected 1489 at runtime, and does not affect PEs that do not implement 1490 this feature. 1491 1492endmenu 1493 1494menu "ARMv8.3 architectural features" 1495 1496config ARM64_PTR_AUTH 1497 bool "Enable support for pointer authentication" 1498 default y 1499 depends on !KVM || ARM64_VHE 1500 help 1501 Pointer authentication (part of the ARMv8.3 Extensions) provides 1502 instructions for signing and authenticating pointers against secret 1503 keys, which can be used to mitigate Return Oriented Programming (ROP) 1504 and other attacks. 1505 1506 This option enables these instructions at EL0 (i.e. for userspace). 1507 1508 Choosing this option will cause the kernel to initialise secret keys 1509 for each process at exec() time, with these keys being 1510 context-switched along with the process. 1511 1512 The feature is detected at runtime. If the feature is not present in 1513 hardware it will not be advertised to userspace/KVM guest nor will it 1514 be enabled. However, KVM guest also require VHE mode and hence 1515 CONFIG_ARM64_VHE=y option to use this feature. 1516 1517endmenu 1518 1519menu "ARMv8.5 architectural features" 1520 1521config ARM64_E0PD 1522 bool "Enable support for E0PD" 1523 default y 1524 help 1525 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1526 that EL0 accesses made via TTBR1 always fault in constant time, 1527 providing similar benefits to KASLR as those provided by KPTI, but 1528 with lower overhead and without disrupting legitimate access to 1529 kernel memory such as SPE. 1530 1531 This option enables E0PD for TTBR1 where available. 1532 1533config ARCH_RANDOM 1534 bool "Enable support for random number generation" 1535 default y 1536 help 1537 Random number generation (part of the ARMv8.5 Extensions) 1538 provides a high bandwidth, cryptographically secure 1539 hardware random number generator. 1540 1541endmenu 1542 1543config ARM64_SVE 1544 bool "ARM Scalable Vector Extension support" 1545 default y 1546 depends on !KVM || ARM64_VHE 1547 help 1548 The Scalable Vector Extension (SVE) is an extension to the AArch64 1549 execution state which complements and extends the SIMD functionality 1550 of the base architecture to support much larger vectors and to enable 1551 additional vectorisation opportunities. 1552 1553 To enable use of this extension on CPUs that implement it, say Y. 1554 1555 On CPUs that support the SVE2 extensions, this option will enable 1556 those too. 1557 1558 Note that for architectural reasons, firmware _must_ implement SVE 1559 support when running on SVE capable hardware. The required support 1560 is present in: 1561 1562 * version 1.5 and later of the ARM Trusted Firmware 1563 * the AArch64 boot wrapper since commit 5e1261e08abf 1564 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1565 1566 For other firmware implementations, consult the firmware documentation 1567 or vendor. 1568 1569 If you need the kernel to boot on SVE-capable hardware with broken 1570 firmware, you may need to say N here until you get your firmware 1571 fixed. Otherwise, you may experience firmware panics or lockups when 1572 booting the kernel. If unsure and you are not observing these 1573 symptoms, you should assume that it is safe to say Y. 1574 1575 CPUs that support SVE are architecturally required to support the 1576 Virtualization Host Extensions (VHE), so the kernel makes no 1577 provision for supporting SVE alongside KVM without VHE enabled. 1578 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support 1579 KVM in the same kernel image. 1580 1581config ARM64_MODULE_PLTS 1582 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1583 depends on MODULES 1584 select HAVE_MOD_ARCH_SPECIFIC 1585 help 1586 Allocate PLTs when loading modules so that jumps and calls whose 1587 targets are too far away for their relative offsets to be encoded 1588 in the instructions themselves can be bounced via veneers in the 1589 module's PLT. This allows modules to be allocated in the generic 1590 vmalloc area after the dedicated module memory area has been 1591 exhausted. 1592 1593 When running with address space randomization (KASLR), the module 1594 region itself may be too far away for ordinary relative jumps and 1595 calls, and so in that case, module PLTs are required and cannot be 1596 disabled. 1597 1598 Specific errata workaround(s) might also force module PLTs to be 1599 enabled (ARM64_ERRATUM_843419). 1600 1601config ARM64_PSEUDO_NMI 1602 bool "Support for NMI-like interrupts" 1603 select ARM_GIC_V3 1604 help 1605 Adds support for mimicking Non-Maskable Interrupts through the use of 1606 GIC interrupt priority. This support requires version 3 or later of 1607 ARM GIC. 1608 1609 This high priority configuration for interrupts needs to be 1610 explicitly enabled by setting the kernel parameter 1611 "irqchip.gicv3_pseudo_nmi" to 1. 1612 1613 If unsure, say N 1614 1615if ARM64_PSEUDO_NMI 1616config ARM64_DEBUG_PRIORITY_MASKING 1617 bool "Debug interrupt priority masking" 1618 help 1619 This adds runtime checks to functions enabling/disabling 1620 interrupts when using priority masking. The additional checks verify 1621 the validity of ICC_PMR_EL1 when calling concerned functions. 1622 1623 If unsure, say N 1624endif 1625 1626config RELOCATABLE 1627 bool 1628 select ARCH_HAS_RELR 1629 help 1630 This builds the kernel as a Position Independent Executable (PIE), 1631 which retains all relocation metadata required to relocate the 1632 kernel binary at runtime to a different virtual address than the 1633 address it was linked at. 1634 Since AArch64 uses the RELA relocation format, this requires a 1635 relocation pass at runtime even if the kernel is loaded at the 1636 same address it was linked at. 1637 1638config RANDOMIZE_BASE 1639 bool "Randomize the address of the kernel image" 1640 select ARM64_MODULE_PLTS if MODULES 1641 select RELOCATABLE 1642 help 1643 Randomizes the virtual address at which the kernel image is 1644 loaded, as a security feature that deters exploit attempts 1645 relying on knowledge of the location of kernel internals. 1646 1647 It is the bootloader's job to provide entropy, by passing a 1648 random u64 value in /chosen/kaslr-seed at kernel entry. 1649 1650 When booting via the UEFI stub, it will invoke the firmware's 1651 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1652 to the kernel proper. In addition, it will randomise the physical 1653 location of the kernel Image as well. 1654 1655 If unsure, say N. 1656 1657config RANDOMIZE_MODULE_REGION_FULL 1658 bool "Randomize the module region over a 4 GB range" 1659 depends on RANDOMIZE_BASE 1660 default y 1661 help 1662 Randomizes the location of the module region inside a 4 GB window 1663 covering the core kernel. This way, it is less likely for modules 1664 to leak information about the location of core kernel data structures 1665 but it does imply that function calls between modules and the core 1666 kernel will need to be resolved via veneers in the module PLT. 1667 1668 When this option is not set, the module region will be randomized over 1669 a limited range that contains the [_stext, _etext] interval of the 1670 core kernel, so branch relocations are always in range. 1671 1672config CC_HAVE_STACKPROTECTOR_SYSREG 1673 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 1674 1675config STACKPROTECTOR_PER_TASK 1676 def_bool y 1677 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 1678 1679endmenu 1680 1681menu "Boot options" 1682 1683config ARM64_ACPI_PARKING_PROTOCOL 1684 bool "Enable support for the ARM64 ACPI parking protocol" 1685 depends on ACPI 1686 help 1687 Enable support for the ARM64 ACPI parking protocol. If disabled 1688 the kernel will not allow booting through the ARM64 ACPI parking 1689 protocol even if the corresponding data is present in the ACPI 1690 MADT table. 1691 1692config CMDLINE 1693 string "Default kernel command string" 1694 default "" 1695 help 1696 Provide a set of default command-line options at build time by 1697 entering them here. As a minimum, you should specify the the 1698 root device (e.g. root=/dev/nfs). 1699 1700config CMDLINE_FORCE 1701 bool "Always use the default kernel command string" 1702 depends on CMDLINE != "" 1703 help 1704 Always use the default kernel command string, even if the boot 1705 loader passes other arguments to the kernel. 1706 This is useful if you cannot or don't want to change the 1707 command-line options your boot loader passes to the kernel. 1708 1709config EFI_STUB 1710 bool 1711 1712config EFI 1713 bool "UEFI runtime support" 1714 depends on OF && !CPU_BIG_ENDIAN 1715 depends on KERNEL_MODE_NEON 1716 select ARCH_SUPPORTS_ACPI 1717 select LIBFDT 1718 select UCS2_STRING 1719 select EFI_PARAMS_FROM_FDT 1720 select EFI_RUNTIME_WRAPPERS 1721 select EFI_STUB 1722 select EFI_ARMSTUB 1723 default y 1724 help 1725 This option provides support for runtime services provided 1726 by UEFI firmware (such as non-volatile variables, realtime 1727 clock, and platform reset). A UEFI stub is also provided to 1728 allow the kernel to be booted as an EFI application. This 1729 is only useful on systems that have UEFI firmware. 1730 1731config DMI 1732 bool "Enable support for SMBIOS (DMI) tables" 1733 depends on EFI 1734 default y 1735 help 1736 This enables SMBIOS/DMI feature for systems. 1737 1738 This option is only useful on systems that have UEFI firmware. 1739 However, even with this option, the resultant kernel should 1740 continue to boot on existing non-UEFI platforms. 1741 1742endmenu 1743 1744config SYSVIPC_COMPAT 1745 def_bool y 1746 depends on COMPAT && SYSVIPC 1747 1748config ARCH_ENABLE_HUGEPAGE_MIGRATION 1749 def_bool y 1750 depends on HUGETLB_PAGE && MIGRATION 1751 1752menu "Power management options" 1753 1754source "kernel/power/Kconfig" 1755 1756config ARCH_HIBERNATION_POSSIBLE 1757 def_bool y 1758 depends on CPU_PM 1759 1760config ARCH_HIBERNATION_HEADER 1761 def_bool y 1762 depends on HIBERNATION 1763 1764config ARCH_SUSPEND_POSSIBLE 1765 def_bool y 1766 1767endmenu 1768 1769menu "CPU Power Management" 1770 1771source "drivers/cpuidle/Kconfig" 1772 1773source "drivers/cpufreq/Kconfig" 1774 1775endmenu 1776 1777source "drivers/firmware/Kconfig" 1778 1779source "drivers/acpi/Kconfig" 1780 1781source "arch/arm64/kvm/Kconfig" 1782 1783if CRYPTO 1784source "arch/arm64/crypto/Kconfig" 1785endif 1786