1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ACPI_MCFG if ACPI 7 select ARCH_HAS_DEVMEM_IS_ALLOWED 8 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 9 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_GCOV_PROFILE_ALL 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_SG_CHAIN 14 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 15 select ARCH_USE_CMPXCHG_LOCKREF 16 select ARCH_SUPPORTS_ATOMIC_RMW 17 select ARCH_SUPPORTS_NUMA_BALANCING 18 select ARCH_WANT_OPTIONAL_GPIOLIB 19 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 20 select ARCH_WANT_FRAME_POINTERS 21 select ARCH_HAS_UBSAN_SANITIZE_ALL 22 select ARM_AMBA 23 select ARM_ARCH_TIMER 24 select ARM_GIC 25 select AUDIT_ARCH_COMPAT_GENERIC 26 select ARM_GIC_V2M if PCI 27 select ARM_GIC_V3 28 select ARM_GIC_V3_ITS if PCI 29 select ARM_PSCI_FW 30 select BUILDTIME_EXTABLE_SORT 31 select CLONE_BACKWARDS 32 select COMMON_CLK 33 select CPU_PM if (SUSPEND || CPU_IDLE) 34 select DCACHE_WORD_ACCESS 35 select EDAC_SUPPORT 36 select FRAME_POINTER 37 select GENERIC_ALLOCATOR 38 select GENERIC_CLOCKEVENTS 39 select GENERIC_CLOCKEVENTS_BROADCAST 40 select GENERIC_CPU_AUTOPROBE 41 select GENERIC_EARLY_IOREMAP 42 select GENERIC_IDLE_POLL_SETUP 43 select GENERIC_IRQ_PROBE 44 select GENERIC_IRQ_SHOW 45 select GENERIC_IRQ_SHOW_LEVEL 46 select GENERIC_PCI_IOMAP 47 select GENERIC_SCHED_CLOCK 48 select GENERIC_SMP_IDLE_THREAD 49 select GENERIC_STRNCPY_FROM_USER 50 select GENERIC_STRNLEN_USER 51 select GENERIC_TIME_VSYSCALL 52 select HANDLE_DOMAIN_IRQ 53 select HARDIRQS_SW_RESEND 54 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 55 select HAVE_ARCH_AUDITSYSCALL 56 select HAVE_ARCH_BITREVERSE 57 select HAVE_ARCH_HARDENED_USERCOPY 58 select HAVE_ARCH_HUGE_VMAP 59 select HAVE_ARCH_JUMP_LABEL 60 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 61 select HAVE_ARCH_KGDB 62 select HAVE_ARCH_MMAP_RND_BITS 63 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 64 select HAVE_ARCH_SECCOMP_FILTER 65 select HAVE_ARCH_TRACEHOOK 66 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 67 select HAVE_ARM_SMCCC 68 select HAVE_EBPF_JIT 69 select HAVE_C_RECORDMCOUNT 70 select HAVE_CC_STACKPROTECTOR 71 select HAVE_CMPXCHG_DOUBLE 72 select HAVE_CMPXCHG_LOCAL 73 select HAVE_CONTEXT_TRACKING 74 select HAVE_DEBUG_BUGVERBOSE 75 select HAVE_DEBUG_KMEMLEAK 76 select HAVE_DMA_API_DEBUG 77 select HAVE_DMA_CONTIGUOUS 78 select HAVE_DYNAMIC_FTRACE 79 select HAVE_EFFICIENT_UNALIGNED_ACCESS 80 select HAVE_FTRACE_MCOUNT_RECORD 81 select HAVE_FUNCTION_TRACER 82 select HAVE_FUNCTION_GRAPH_TRACER 83 select HAVE_GCC_PLUGINS 84 select HAVE_GENERIC_DMA_COHERENT 85 select HAVE_HW_BREAKPOINT if PERF_EVENTS 86 select HAVE_IRQ_TIME_ACCOUNTING 87 select HAVE_MEMBLOCK 88 select HAVE_MEMBLOCK_NODE_MAP if NUMA 89 select HAVE_PATA_PLATFORM 90 select HAVE_PERF_EVENTS 91 select HAVE_PERF_REGS 92 select HAVE_PERF_USER_STACK_DUMP 93 select HAVE_REGS_AND_STACK_ACCESS_API 94 select HAVE_RCU_TABLE_FREE 95 select HAVE_SYSCALL_TRACEPOINTS 96 select HAVE_KPROBES 97 select HAVE_KRETPROBES if HAVE_KPROBES 98 select IOMMU_DMA if IOMMU_SUPPORT 99 select IRQ_DOMAIN 100 select IRQ_FORCED_THREADING 101 select MODULES_USE_ELF_RELA 102 select NO_BOOTMEM 103 select OF 104 select OF_EARLY_FLATTREE 105 select OF_NUMA if NUMA && OF 106 select OF_RESERVED_MEM 107 select PCI_ECAM if ACPI 108 select PERF_USE_VMALLOC 109 select POWER_RESET 110 select POWER_SUPPLY 111 select SPARSE_IRQ 112 select SYSCTL_EXCEPTION_TRACE 113 help 114 ARM 64-bit (AArch64) Linux support. 115 116config 64BIT 117 def_bool y 118 119config ARCH_PHYS_ADDR_T_64BIT 120 def_bool y 121 122config MMU 123 def_bool y 124 125config ARM64_PAGE_SHIFT 126 int 127 default 16 if ARM64_64K_PAGES 128 default 14 if ARM64_16K_PAGES 129 default 12 130 131config ARM64_CONT_SHIFT 132 int 133 default 5 if ARM64_64K_PAGES 134 default 7 if ARM64_16K_PAGES 135 default 4 136 137config ARCH_MMAP_RND_BITS_MIN 138 default 14 if ARM64_64K_PAGES 139 default 16 if ARM64_16K_PAGES 140 default 18 141 142# max bits determined by the following formula: 143# VA_BITS - PAGE_SHIFT - 3 144config ARCH_MMAP_RND_BITS_MAX 145 default 19 if ARM64_VA_BITS=36 146 default 24 if ARM64_VA_BITS=39 147 default 27 if ARM64_VA_BITS=42 148 default 30 if ARM64_VA_BITS=47 149 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 150 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 151 default 33 if ARM64_VA_BITS=48 152 default 14 if ARM64_64K_PAGES 153 default 16 if ARM64_16K_PAGES 154 default 18 155 156config ARCH_MMAP_RND_COMPAT_BITS_MIN 157 default 7 if ARM64_64K_PAGES 158 default 9 if ARM64_16K_PAGES 159 default 11 160 161config ARCH_MMAP_RND_COMPAT_BITS_MAX 162 default 16 163 164config NO_IOPORT_MAP 165 def_bool y if !PCI 166 167config STACKTRACE_SUPPORT 168 def_bool y 169 170config ILLEGAL_POINTER_VALUE 171 hex 172 default 0xdead000000000000 173 174config LOCKDEP_SUPPORT 175 def_bool y 176 177config TRACE_IRQFLAGS_SUPPORT 178 def_bool y 179 180config RWSEM_XCHGADD_ALGORITHM 181 def_bool y 182 183config GENERIC_BUG 184 def_bool y 185 depends on BUG 186 187config GENERIC_BUG_RELATIVE_POINTERS 188 def_bool y 189 depends on GENERIC_BUG 190 191config GENERIC_HWEIGHT 192 def_bool y 193 194config GENERIC_CSUM 195 def_bool y 196 197config GENERIC_CALIBRATE_DELAY 198 def_bool y 199 200config ZONE_DMA 201 def_bool y 202 203config HAVE_GENERIC_RCU_GUP 204 def_bool y 205 206config ARCH_DMA_ADDR_T_64BIT 207 def_bool y 208 209config NEED_DMA_MAP_STATE 210 def_bool y 211 212config NEED_SG_DMA_LENGTH 213 def_bool y 214 215config SMP 216 def_bool y 217 218config SWIOTLB 219 def_bool y 220 221config IOMMU_HELPER 222 def_bool SWIOTLB 223 224config KERNEL_MODE_NEON 225 def_bool y 226 227config FIX_EARLYCON_MEM 228 def_bool y 229 230config PGTABLE_LEVELS 231 int 232 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 233 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 234 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 235 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 236 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 237 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 238 239source "init/Kconfig" 240 241source "kernel/Kconfig.freezer" 242 243source "arch/arm64/Kconfig.platforms" 244 245menu "Bus support" 246 247config PCI 248 bool "PCI support" 249 help 250 This feature enables support for PCI bus system. If you say Y 251 here, the kernel will include drivers and infrastructure code 252 to support PCI bus devices. 253 254config PCI_DOMAINS 255 def_bool PCI 256 257config PCI_DOMAINS_GENERIC 258 def_bool PCI 259 260config PCI_SYSCALL 261 def_bool PCI 262 263source "drivers/pci/Kconfig" 264 265endmenu 266 267menu "Kernel Features" 268 269menu "ARM errata workarounds via the alternatives framework" 270 271config ARM64_ERRATUM_826319 272 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 273 default y 274 help 275 This option adds an alternative code sequence to work around ARM 276 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 277 AXI master interface and an L2 cache. 278 279 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 280 and is unable to accept a certain write via this interface, it will 281 not progress on read data presented on the read data channel and the 282 system can deadlock. 283 284 The workaround promotes data cache clean instructions to 285 data cache clean-and-invalidate. 286 Please note that this does not necessarily enable the workaround, 287 as it depends on the alternative framework, which will only patch 288 the kernel if an affected CPU is detected. 289 290 If unsure, say Y. 291 292config ARM64_ERRATUM_827319 293 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 294 default y 295 help 296 This option adds an alternative code sequence to work around ARM 297 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 298 master interface and an L2 cache. 299 300 Under certain conditions this erratum can cause a clean line eviction 301 to occur at the same time as another transaction to the same address 302 on the AMBA 5 CHI interface, which can cause data corruption if the 303 interconnect reorders the two transactions. 304 305 The workaround promotes data cache clean instructions to 306 data cache clean-and-invalidate. 307 Please note that this does not necessarily enable the workaround, 308 as it depends on the alternative framework, which will only patch 309 the kernel if an affected CPU is detected. 310 311 If unsure, say Y. 312 313config ARM64_ERRATUM_824069 314 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 315 default y 316 help 317 This option adds an alternative code sequence to work around ARM 318 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 319 to a coherent interconnect. 320 321 If a Cortex-A53 processor is executing a store or prefetch for 322 write instruction at the same time as a processor in another 323 cluster is executing a cache maintenance operation to the same 324 address, then this erratum might cause a clean cache line to be 325 incorrectly marked as dirty. 326 327 The workaround promotes data cache clean instructions to 328 data cache clean-and-invalidate. 329 Please note that this option does not necessarily enable the 330 workaround, as it depends on the alternative framework, which will 331 only patch the kernel if an affected CPU is detected. 332 333 If unsure, say Y. 334 335config ARM64_ERRATUM_819472 336 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 337 default y 338 help 339 This option adds an alternative code sequence to work around ARM 340 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 341 present when it is connected to a coherent interconnect. 342 343 If the processor is executing a load and store exclusive sequence at 344 the same time as a processor in another cluster is executing a cache 345 maintenance operation to the same address, then this erratum might 346 cause data corruption. 347 348 The workaround promotes data cache clean instructions to 349 data cache clean-and-invalidate. 350 Please note that this does not necessarily enable the workaround, 351 as it depends on the alternative framework, which will only patch 352 the kernel if an affected CPU is detected. 353 354 If unsure, say Y. 355 356config ARM64_ERRATUM_832075 357 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 358 default y 359 help 360 This option adds an alternative code sequence to work around ARM 361 erratum 832075 on Cortex-A57 parts up to r1p2. 362 363 Affected Cortex-A57 parts might deadlock when exclusive load/store 364 instructions to Write-Back memory are mixed with Device loads. 365 366 The workaround is to promote device loads to use Load-Acquire 367 semantics. 368 Please note that this does not necessarily enable the workaround, 369 as it depends on the alternative framework, which will only patch 370 the kernel if an affected CPU is detected. 371 372 If unsure, say Y. 373 374config ARM64_ERRATUM_834220 375 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 376 depends on KVM 377 default y 378 help 379 This option adds an alternative code sequence to work around ARM 380 erratum 834220 on Cortex-A57 parts up to r1p2. 381 382 Affected Cortex-A57 parts might report a Stage 2 translation 383 fault as the result of a Stage 1 fault for load crossing a 384 page boundary when there is a permission or device memory 385 alignment fault at Stage 1 and a translation fault at Stage 2. 386 387 The workaround is to verify that the Stage 1 translation 388 doesn't generate a fault before handling the Stage 2 fault. 389 Please note that this does not necessarily enable the workaround, 390 as it depends on the alternative framework, which will only patch 391 the kernel if an affected CPU is detected. 392 393 If unsure, say Y. 394 395config ARM64_ERRATUM_845719 396 bool "Cortex-A53: 845719: a load might read incorrect data" 397 depends on COMPAT 398 default y 399 help 400 This option adds an alternative code sequence to work around ARM 401 erratum 845719 on Cortex-A53 parts up to r0p4. 402 403 When running a compat (AArch32) userspace on an affected Cortex-A53 404 part, a load at EL0 from a virtual address that matches the bottom 32 405 bits of the virtual address used by a recent load at (AArch64) EL1 406 might return incorrect data. 407 408 The workaround is to write the contextidr_el1 register on exception 409 return to a 32-bit task. 410 Please note that this does not necessarily enable the workaround, 411 as it depends on the alternative framework, which will only patch 412 the kernel if an affected CPU is detected. 413 414 If unsure, say Y. 415 416config ARM64_ERRATUM_843419 417 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 418 depends on MODULES 419 default y 420 select ARM64_MODULE_CMODEL_LARGE 421 help 422 This option builds kernel modules using the large memory model in 423 order to avoid the use of the ADRP instruction, which can cause 424 a subsequent memory access to use an incorrect address on Cortex-A53 425 parts up to r0p4. 426 427 Note that the kernel itself must be linked with a version of ld 428 which fixes potentially affected ADRP instructions through the 429 use of veneers. 430 431 If unsure, say Y. 432 433config CAVIUM_ERRATUM_22375 434 bool "Cavium erratum 22375, 24313" 435 default y 436 help 437 Enable workaround for erratum 22375, 24313. 438 439 This implements two gicv3-its errata workarounds for ThunderX. Both 440 with small impact affecting only ITS table allocation. 441 442 erratum 22375: only alloc 8MB table size 443 erratum 24313: ignore memory access type 444 445 The fixes are in ITS initialization and basically ignore memory access 446 type and table size provided by the TYPER and BASER registers. 447 448 If unsure, say Y. 449 450config CAVIUM_ERRATUM_23144 451 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 452 depends on NUMA 453 default y 454 help 455 ITS SYNC command hang for cross node io and collections/cpu mapping. 456 457 If unsure, say Y. 458 459config CAVIUM_ERRATUM_23154 460 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 461 default y 462 help 463 The gicv3 of ThunderX requires a modified version for 464 reading the IAR status to ensure data synchronization 465 (access to icc_iar1_el1 is not sync'ed before and after). 466 467 If unsure, say Y. 468 469config CAVIUM_ERRATUM_27456 470 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 471 default y 472 help 473 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 474 instructions may cause the icache to become corrupted if it 475 contains data for a non-current ASID. The fix is to 476 invalidate the icache when changing the mm context. 477 478 If unsure, say Y. 479 480endmenu 481 482 483choice 484 prompt "Page size" 485 default ARM64_4K_PAGES 486 help 487 Page size (translation granule) configuration. 488 489config ARM64_4K_PAGES 490 bool "4KB" 491 help 492 This feature enables 4KB pages support. 493 494config ARM64_16K_PAGES 495 bool "16KB" 496 help 497 The system will use 16KB pages support. AArch32 emulation 498 requires applications compiled with 16K (or a multiple of 16K) 499 aligned segments. 500 501config ARM64_64K_PAGES 502 bool "64KB" 503 help 504 This feature enables 64KB pages support (4KB by default) 505 allowing only two levels of page tables and faster TLB 506 look-up. AArch32 emulation requires applications compiled 507 with 64K aligned segments. 508 509endchoice 510 511choice 512 prompt "Virtual address space size" 513 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 514 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 515 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 516 help 517 Allows choosing one of multiple possible virtual address 518 space sizes. The level of translation table is determined by 519 a combination of page size and virtual address space size. 520 521config ARM64_VA_BITS_36 522 bool "36-bit" if EXPERT 523 depends on ARM64_16K_PAGES 524 525config ARM64_VA_BITS_39 526 bool "39-bit" 527 depends on ARM64_4K_PAGES 528 529config ARM64_VA_BITS_42 530 bool "42-bit" 531 depends on ARM64_64K_PAGES 532 533config ARM64_VA_BITS_47 534 bool "47-bit" 535 depends on ARM64_16K_PAGES 536 537config ARM64_VA_BITS_48 538 bool "48-bit" 539 540endchoice 541 542config ARM64_VA_BITS 543 int 544 default 36 if ARM64_VA_BITS_36 545 default 39 if ARM64_VA_BITS_39 546 default 42 if ARM64_VA_BITS_42 547 default 47 if ARM64_VA_BITS_47 548 default 48 if ARM64_VA_BITS_48 549 550config CPU_BIG_ENDIAN 551 bool "Build big-endian kernel" 552 help 553 Say Y if you plan on running a kernel in big-endian mode. 554 555config SCHED_MC 556 bool "Multi-core scheduler support" 557 help 558 Multi-core scheduler support improves the CPU scheduler's decision 559 making when dealing with multi-core CPU chips at a cost of slightly 560 increased overhead in some places. If unsure say N here. 561 562config SCHED_SMT 563 bool "SMT scheduler support" 564 help 565 Improves the CPU scheduler's decision making when dealing with 566 MultiThreading at a cost of slightly increased overhead in some 567 places. If unsure say N here. 568 569config NR_CPUS 570 int "Maximum number of CPUs (2-4096)" 571 range 2 4096 572 # These have to remain sorted largest to smallest 573 default "64" 574 575config HOTPLUG_CPU 576 bool "Support for hot-pluggable CPUs" 577 select GENERIC_IRQ_MIGRATION 578 help 579 Say Y here to experiment with turning CPUs off and on. CPUs 580 can be controlled through /sys/devices/system/cpu. 581 582# Common NUMA Features 583config NUMA 584 bool "Numa Memory Allocation and Scheduler Support" 585 depends on SMP 586 help 587 Enable NUMA (Non Uniform Memory Access) support. 588 589 The kernel will try to allocate memory used by a CPU on the 590 local memory of the CPU and add some more 591 NUMA awareness to the kernel. 592 593config NODES_SHIFT 594 int "Maximum NUMA Nodes (as a power of 2)" 595 range 1 10 596 default "2" 597 depends on NEED_MULTIPLE_NODES 598 help 599 Specify the maximum number of NUMA Nodes available on the target 600 system. Increases memory reserved to accommodate various tables. 601 602config USE_PERCPU_NUMA_NODE_ID 603 def_bool y 604 depends on NUMA 605 606source kernel/Kconfig.preempt 607source kernel/Kconfig.hz 608 609config ARCH_SUPPORTS_DEBUG_PAGEALLOC 610 depends on !HIBERNATION 611 def_bool y 612 613config ARCH_HAS_HOLES_MEMORYMODEL 614 def_bool y if SPARSEMEM 615 616config ARCH_SPARSEMEM_ENABLE 617 def_bool y 618 select SPARSEMEM_VMEMMAP_ENABLE 619 620config ARCH_SPARSEMEM_DEFAULT 621 def_bool ARCH_SPARSEMEM_ENABLE 622 623config ARCH_SELECT_MEMORY_MODEL 624 def_bool ARCH_SPARSEMEM_ENABLE 625 626config HAVE_ARCH_PFN_VALID 627 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 628 629config HW_PERF_EVENTS 630 def_bool y 631 depends on ARM_PMU 632 633config SYS_SUPPORTS_HUGETLBFS 634 def_bool y 635 636config ARCH_WANT_HUGE_PMD_SHARE 637 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 638 639config ARCH_HAS_CACHE_LINE_SIZE 640 def_bool y 641 642source "mm/Kconfig" 643 644config SECCOMP 645 bool "Enable seccomp to safely compute untrusted bytecode" 646 ---help--- 647 This kernel feature is useful for number crunching applications 648 that may need to compute untrusted bytecode during their 649 execution. By using pipes or other transports made available to 650 the process as file descriptors supporting the read/write 651 syscalls, it's possible to isolate those applications in 652 their own address space using seccomp. Once seccomp is 653 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 654 and the task is only allowed to execute a few safe syscalls 655 defined by each seccomp mode. 656 657config PARAVIRT 658 bool "Enable paravirtualization code" 659 help 660 This changes the kernel so it can modify itself when it is run 661 under a hypervisor, potentially improving performance significantly 662 over full virtualization. 663 664config PARAVIRT_TIME_ACCOUNTING 665 bool "Paravirtual steal time accounting" 666 select PARAVIRT 667 default n 668 help 669 Select this option to enable fine granularity task steal time 670 accounting. Time spent executing other tasks in parallel with 671 the current vCPU is discounted from the vCPU power. To account for 672 that, there can be a small performance impact. 673 674 If in doubt, say N here. 675 676config KEXEC 677 depends on PM_SLEEP_SMP 678 select KEXEC_CORE 679 bool "kexec system call" 680 ---help--- 681 kexec is a system call that implements the ability to shutdown your 682 current kernel, and to start another kernel. It is like a reboot 683 but it is independent of the system firmware. And like a reboot 684 you can start any kernel with it, not just Linux. 685 686config XEN_DOM0 687 def_bool y 688 depends on XEN 689 690config XEN 691 bool "Xen guest support on ARM64" 692 depends on ARM64 && OF 693 select SWIOTLB_XEN 694 select PARAVIRT 695 help 696 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 697 698config FORCE_MAX_ZONEORDER 699 int 700 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 701 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 702 default "11" 703 help 704 The kernel memory allocator divides physically contiguous memory 705 blocks into "zones", where each zone is a power of two number of 706 pages. This option selects the largest power of two that the kernel 707 keeps in the memory allocator. If you need to allocate very large 708 blocks of physically contiguous memory, then you may need to 709 increase this value. 710 711 This config option is actually maximum order plus one. For example, 712 a value of 11 means that the largest free memory block is 2^10 pages. 713 714 We make sure that we can allocate upto a HugePage size for each configuration. 715 Hence we have : 716 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 717 718 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 719 4M allocations matching the default size used by generic code. 720 721menuconfig ARMV8_DEPRECATED 722 bool "Emulate deprecated/obsolete ARMv8 instructions" 723 depends on COMPAT 724 help 725 Legacy software support may require certain instructions 726 that have been deprecated or obsoleted in the architecture. 727 728 Enable this config to enable selective emulation of these 729 features. 730 731 If unsure, say Y 732 733if ARMV8_DEPRECATED 734 735config SWP_EMULATION 736 bool "Emulate SWP/SWPB instructions" 737 help 738 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 739 they are always undefined. Say Y here to enable software 740 emulation of these instructions for userspace using LDXR/STXR. 741 742 In some older versions of glibc [<=2.8] SWP is used during futex 743 trylock() operations with the assumption that the code will not 744 be preempted. This invalid assumption may be more likely to fail 745 with SWP emulation enabled, leading to deadlock of the user 746 application. 747 748 NOTE: when accessing uncached shared regions, LDXR/STXR rely 749 on an external transaction monitoring block called a global 750 monitor to maintain update atomicity. If your system does not 751 implement a global monitor, this option can cause programs that 752 perform SWP operations to uncached memory to deadlock. 753 754 If unsure, say Y 755 756config CP15_BARRIER_EMULATION 757 bool "Emulate CP15 Barrier instructions" 758 help 759 The CP15 barrier instructions - CP15ISB, CP15DSB, and 760 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 761 strongly recommended to use the ISB, DSB, and DMB 762 instructions instead. 763 764 Say Y here to enable software emulation of these 765 instructions for AArch32 userspace code. When this option is 766 enabled, CP15 barrier usage is traced which can help 767 identify software that needs updating. 768 769 If unsure, say Y 770 771config SETEND_EMULATION 772 bool "Emulate SETEND instruction" 773 help 774 The SETEND instruction alters the data-endianness of the 775 AArch32 EL0, and is deprecated in ARMv8. 776 777 Say Y here to enable software emulation of the instruction 778 for AArch32 userspace code. 779 780 Note: All the cpus on the system must have mixed endian support at EL0 781 for this feature to be enabled. If a new CPU - which doesn't support mixed 782 endian - is hotplugged in after this feature has been enabled, there could 783 be unexpected results in the applications. 784 785 If unsure, say Y 786endif 787 788menu "ARMv8.1 architectural features" 789 790config ARM64_HW_AFDBM 791 bool "Support for hardware updates of the Access and Dirty page flags" 792 default y 793 help 794 The ARMv8.1 architecture extensions introduce support for 795 hardware updates of the access and dirty information in page 796 table entries. When enabled in TCR_EL1 (HA and HD bits) on 797 capable processors, accesses to pages with PTE_AF cleared will 798 set this bit instead of raising an access flag fault. 799 Similarly, writes to read-only pages with the DBM bit set will 800 clear the read-only bit (AP[2]) instead of raising a 801 permission fault. 802 803 Kernels built with this configuration option enabled continue 804 to work on pre-ARMv8.1 hardware and the performance impact is 805 minimal. If unsure, say Y. 806 807config ARM64_PAN 808 bool "Enable support for Privileged Access Never (PAN)" 809 default y 810 help 811 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 812 prevents the kernel or hypervisor from accessing user-space (EL0) 813 memory directly. 814 815 Choosing this option will cause any unprotected (not using 816 copy_to_user et al) memory access to fail with a permission fault. 817 818 The feature is detected at runtime, and will remain as a 'nop' 819 instruction if the cpu does not implement the feature. 820 821config ARM64_LSE_ATOMICS 822 bool "Atomic instructions" 823 help 824 As part of the Large System Extensions, ARMv8.1 introduces new 825 atomic instructions that are designed specifically to scale in 826 very large systems. 827 828 Say Y here to make use of these instructions for the in-kernel 829 atomic routines. This incurs a small overhead on CPUs that do 830 not support these instructions and requires the kernel to be 831 built with binutils >= 2.25. 832 833config ARM64_VHE 834 bool "Enable support for Virtualization Host Extensions (VHE)" 835 default y 836 help 837 Virtualization Host Extensions (VHE) allow the kernel to run 838 directly at EL2 (instead of EL1) on processors that support 839 it. This leads to better performance for KVM, as they reduce 840 the cost of the world switch. 841 842 Selecting this option allows the VHE feature to be detected 843 at runtime, and does not affect processors that do not 844 implement this feature. 845 846endmenu 847 848menu "ARMv8.2 architectural features" 849 850config ARM64_UAO 851 bool "Enable support for User Access Override (UAO)" 852 default y 853 help 854 User Access Override (UAO; part of the ARMv8.2 Extensions) 855 causes the 'unprivileged' variant of the load/store instructions to 856 be overriden to be privileged. 857 858 This option changes get_user() and friends to use the 'unprivileged' 859 variant of the load/store instructions. This ensures that user-space 860 really did have access to the supplied memory. When addr_limit is 861 set to kernel memory the UAO bit will be set, allowing privileged 862 access to kernel memory. 863 864 Choosing this option will cause copy_to_user() et al to use user-space 865 memory permissions. 866 867 The feature is detected at runtime, the kernel will use the 868 regular load/store instructions if the cpu does not implement the 869 feature. 870 871endmenu 872 873config ARM64_MODULE_CMODEL_LARGE 874 bool 875 876config ARM64_MODULE_PLTS 877 bool 878 select ARM64_MODULE_CMODEL_LARGE 879 select HAVE_MOD_ARCH_SPECIFIC 880 881config RELOCATABLE 882 bool 883 help 884 This builds the kernel as a Position Independent Executable (PIE), 885 which retains all relocation metadata required to relocate the 886 kernel binary at runtime to a different virtual address than the 887 address it was linked at. 888 Since AArch64 uses the RELA relocation format, this requires a 889 relocation pass at runtime even if the kernel is loaded at the 890 same address it was linked at. 891 892config RANDOMIZE_BASE 893 bool "Randomize the address of the kernel image" 894 select ARM64_MODULE_PLTS if MODULES 895 select RELOCATABLE 896 help 897 Randomizes the virtual address at which the kernel image is 898 loaded, as a security feature that deters exploit attempts 899 relying on knowledge of the location of kernel internals. 900 901 It is the bootloader's job to provide entropy, by passing a 902 random u64 value in /chosen/kaslr-seed at kernel entry. 903 904 When booting via the UEFI stub, it will invoke the firmware's 905 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 906 to the kernel proper. In addition, it will randomise the physical 907 location of the kernel Image as well. 908 909 If unsure, say N. 910 911config RANDOMIZE_MODULE_REGION_FULL 912 bool "Randomize the module region independently from the core kernel" 913 depends on RANDOMIZE_BASE 914 default y 915 help 916 Randomizes the location of the module region without considering the 917 location of the core kernel. This way, it is impossible for modules 918 to leak information about the location of core kernel data structures 919 but it does imply that function calls between modules and the core 920 kernel will need to be resolved via veneers in the module PLT. 921 922 When this option is not set, the module region will be randomized over 923 a limited range that contains the [_stext, _etext] interval of the 924 core kernel, so branch relocations are always in range. 925 926endmenu 927 928menu "Boot options" 929 930config ARM64_ACPI_PARKING_PROTOCOL 931 bool "Enable support for the ARM64 ACPI parking protocol" 932 depends on ACPI 933 help 934 Enable support for the ARM64 ACPI parking protocol. If disabled 935 the kernel will not allow booting through the ARM64 ACPI parking 936 protocol even if the corresponding data is present in the ACPI 937 MADT table. 938 939config CMDLINE 940 string "Default kernel command string" 941 default "" 942 help 943 Provide a set of default command-line options at build time by 944 entering them here. As a minimum, you should specify the the 945 root device (e.g. root=/dev/nfs). 946 947config CMDLINE_FORCE 948 bool "Always use the default kernel command string" 949 help 950 Always use the default kernel command string, even if the boot 951 loader passes other arguments to the kernel. 952 This is useful if you cannot or don't want to change the 953 command-line options your boot loader passes to the kernel. 954 955config EFI_STUB 956 bool 957 958config EFI 959 bool "UEFI runtime support" 960 depends on OF && !CPU_BIG_ENDIAN 961 select LIBFDT 962 select UCS2_STRING 963 select EFI_PARAMS_FROM_FDT 964 select EFI_RUNTIME_WRAPPERS 965 select EFI_STUB 966 select EFI_ARMSTUB 967 default y 968 help 969 This option provides support for runtime services provided 970 by UEFI firmware (such as non-volatile variables, realtime 971 clock, and platform reset). A UEFI stub is also provided to 972 allow the kernel to be booted as an EFI application. This 973 is only useful on systems that have UEFI firmware. 974 975config DMI 976 bool "Enable support for SMBIOS (DMI) tables" 977 depends on EFI 978 default y 979 help 980 This enables SMBIOS/DMI feature for systems. 981 982 This option is only useful on systems that have UEFI firmware. 983 However, even with this option, the resultant kernel should 984 continue to boot on existing non-UEFI platforms. 985 986endmenu 987 988menu "Userspace binary formats" 989 990source "fs/Kconfig.binfmt" 991 992config COMPAT 993 bool "Kernel support for 32-bit EL0" 994 depends on ARM64_4K_PAGES || EXPERT 995 select COMPAT_BINFMT_ELF 996 select HAVE_UID16 997 select OLD_SIGSUSPEND3 998 select COMPAT_OLD_SIGACTION 999 help 1000 This option enables support for a 32-bit EL0 running under a 64-bit 1001 kernel at EL1. AArch32-specific components such as system calls, 1002 the user helper functions, VFP support and the ptrace interface are 1003 handled appropriately by the kernel. 1004 1005 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1006 that you will only be able to execute AArch32 binaries that were compiled 1007 with page size aligned segments. 1008 1009 If you want to execute 32-bit userspace applications, say Y. 1010 1011config SYSVIPC_COMPAT 1012 def_bool y 1013 depends on COMPAT && SYSVIPC 1014 1015endmenu 1016 1017menu "Power management options" 1018 1019source "kernel/power/Kconfig" 1020 1021config ARCH_HIBERNATION_POSSIBLE 1022 def_bool y 1023 depends on CPU_PM 1024 1025config ARCH_HIBERNATION_HEADER 1026 def_bool y 1027 depends on HIBERNATION 1028 1029config ARCH_SUSPEND_POSSIBLE 1030 def_bool y 1031 1032endmenu 1033 1034menu "CPU Power Management" 1035 1036source "drivers/cpuidle/Kconfig" 1037 1038source "drivers/cpufreq/Kconfig" 1039 1040endmenu 1041 1042source "net/Kconfig" 1043 1044source "drivers/Kconfig" 1045 1046source "drivers/firmware/Kconfig" 1047 1048source "drivers/acpi/Kconfig" 1049 1050source "fs/Kconfig" 1051 1052source "arch/arm64/kvm/Kconfig" 1053 1054source "arch/arm64/Kconfig.debug" 1055 1056source "security/Kconfig" 1057 1058source "crypto/Kconfig" 1059if CRYPTO 1060source "arch/arm64/crypto/Kconfig" 1061endif 1062 1063source "lib/Kconfig" 1064