1/* 2 * linux/arch/arm/vfp/vfphw.S 3 * 4 * Copyright (C) 2004 ARM Limited. 5 * Written by Deep Blue Solutions Limited. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This code is called from the kernel's undefined instruction trap. 12 * r9 holds the return address for successful handling. 13 * lr holds the return address for unrecognised instructions. 14 * r10 points at the start of the private FP workspace in the thread structure 15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) 16 */ 17#include <asm/thread_info.h> 18#include <asm/vfpmacros.h> 19#include <linux/kern_levels.h> 20#include "../kernel/entry-header.S" 21 22 .macro DBGSTR, str 23#ifdef DEBUG 24 stmfd sp!, {r0-r3, ip, lr} 25 ldr r0, =1f 26 bl printk 27 ldmfd sp!, {r0-r3, ip, lr} 28 29 .pushsection .rodata, "a" 301: .ascii KERN_DEBUG "VFP: \str\n" 31 .byte 0 32 .previous 33#endif 34 .endm 35 36 .macro DBGSTR1, str, arg 37#ifdef DEBUG 38 stmfd sp!, {r0-r3, ip, lr} 39 mov r1, \arg 40 ldr r0, =1f 41 bl printk 42 ldmfd sp!, {r0-r3, ip, lr} 43 44 .pushsection .rodata, "a" 451: .ascii KERN_DEBUG "VFP: \str\n" 46 .byte 0 47 .previous 48#endif 49 .endm 50 51 .macro DBGSTR3, str, arg1, arg2, arg3 52#ifdef DEBUG 53 stmfd sp!, {r0-r3, ip, lr} 54 mov r3, \arg3 55 mov r2, \arg2 56 mov r1, \arg1 57 ldr r0, =1f 58 bl printk 59 ldmfd sp!, {r0-r3, ip, lr} 60 61 .pushsection .rodata, "a" 621: .ascii KERN_DEBUG "VFP: \str\n" 63 .byte 0 64 .previous 65#endif 66 .endm 67 68 69@ VFP hardware support entry point. 70@ 71@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 72@ r2 = PC value to resume execution after successful emulation 73@ r9 = normal "successful" return address 74@ r10 = vfp_state union 75@ r11 = CPU number 76@ lr = unrecognised instruction return address 77@ IRQs enabled. 78ENTRY(vfp_support_entry) 79 DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 80 81 ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions 82 and r3, r3, #MODE_MASK @ are supported in kernel mode 83 teq r3, #USR_MODE 84 bne vfp_kmode_exception @ Returns through lr 85 86 VFPFMRX r1, FPEXC @ Is the VFP enabled? 87 DBGSTR1 "fpexc %08x", r1 88 tst r1, #FPEXC_EN 89 bne look_for_VFP_exceptions @ VFP is already enabled 90 91 DBGSTR1 "enable %x", r10 92 ldr r3, vfp_current_hw_state_address 93 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set 94 ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer 95 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled 96 cmp r4, r10 @ this thread owns the hw context? 97#ifndef CONFIG_SMP 98 @ For UP, checking that this thread owns the hw context is 99 @ sufficient to determine that the hardware state is valid. 100 beq vfp_hw_state_valid 101 102 @ On UP, we lazily save the VFP context. As a different 103 @ thread wants ownership of the VFP hardware, save the old 104 @ state if there was a previous (valid) owner. 105 106 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending 107 @ exceptions, so we can get at the 108 @ rest of it 109 110 DBGSTR1 "save old state %p", r4 111 cmp r4, #0 @ if the vfp_current_hw_state is NULL 112 beq vfp_reload_hw @ then the hw state needs reloading 113 VFPFSTMIA r4, r5 @ save the working registers 114 VFPFMRX r5, FPSCR @ current status 115#ifndef CONFIG_CPU_FEROCEON 116 tst r1, #FPEXC_EX @ is there additional state to save? 117 beq 1f 118 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) 119 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? 120 beq 1f 121 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1221: 123#endif 124 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 125vfp_reload_hw: 126 127#else 128 @ For SMP, if this thread does not own the hw context, then we 129 @ need to reload it. No need to save the old state as on SMP, 130 @ we always save the state when we switch away from a thread. 131 bne vfp_reload_hw 132 133 @ This thread has ownership of the current hardware context. 134 @ However, it may have been migrated to another CPU, in which 135 @ case the saved state is newer than the hardware context. 136 @ Check this by looking at the CPU number which the state was 137 @ last loaded onto. 138 ldr ip, [r10, #VFP_CPU] 139 teq ip, r11 140 beq vfp_hw_state_valid 141 142vfp_reload_hw: 143 @ We're loading this threads state into the VFP hardware. Update 144 @ the CPU number which contains the most up to date VFP context. 145 str r11, [r10, #VFP_CPU] 146 147 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending 148 @ exceptions, so we can get at the 149 @ rest of it 150#endif 151 152 DBGSTR1 "load state %p", r10 153 str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer 154 @ Load the saved state back into the VFP 155 VFPFLDMIA r10, r5 @ reload the working registers while 156 @ FPEXC is in a safe state 157 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 158#ifndef CONFIG_CPU_FEROCEON 159 tst r1, #FPEXC_EX @ is there additional state to restore? 160 beq 1f 161 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) 162 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? 163 beq 1f 164 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1651: 166#endif 167 VFPFMXR FPSCR, r5 @ restore status 168 169@ The context stored in the VFP hardware is up to date with this thread 170vfp_hw_state_valid: 171 tst r1, #FPEXC_EX 172 bne process_exception @ might as well handle the pending 173 @ exception before retrying branch 174 @ out before setting an FPEXC that 175 @ stops us reading stuff 176 VFPFMXR FPEXC, r1 @ Restore FPEXC last 177 sub r2, r2, #4 @ Retry current instruction - if Thumb 178 str r2, [sp, #S_PC] @ mode it's two 16-bit instructions, 179 @ else it's one 32-bit instruction, so 180 @ always subtract 4 from the following 181 @ instruction address. 182#ifdef CONFIG_PREEMPT_COUNT 183 get_thread_info r10 184 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 185 sub r11, r4, #1 @ decrement it 186 str r11, [r10, #TI_PREEMPT] 187#endif 188 mov pc, r9 @ we think we have handled things 189 190 191look_for_VFP_exceptions: 192 @ Check for synchronous or asynchronous exception 193 tst r1, #FPEXC_EX | FPEXC_DEX 194 bne process_exception 195 @ On some implementations of the VFP subarch 1, setting FPSCR.IXE 196 @ causes all the CDP instructions to be bounced synchronously without 197 @ setting the FPEXC.EX bit 198 VFPFMRX r5, FPSCR 199 tst r5, #FPSCR_IXE 200 bne process_exception 201 202 @ Fall into hand on to next handler - appropriate coproc instr 203 @ not recognised by VFP 204 205 DBGSTR "not VFP" 206#ifdef CONFIG_PREEMPT_COUNT 207 get_thread_info r10 208 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 209 sub r11, r4, #1 @ decrement it 210 str r11, [r10, #TI_PREEMPT] 211#endif 212 mov pc, lr 213 214process_exception: 215 DBGSTR "bounce" 216 mov r2, sp @ nothing stacked - regdump is at TOS 217 mov lr, r9 @ setup for a return to the user code. 218 219 @ Now call the C code to package up the bounce to the support code 220 @ r0 holds the trigger instruction 221 @ r1 holds the FPEXC value 222 @ r2 pointer to register dump 223 b VFP_bounce @ we have handled this - the support 224 @ code will raise an exception if 225 @ required. If not, the user code will 226 @ retry the faulted instruction 227ENDPROC(vfp_support_entry) 228 229ENTRY(vfp_save_state) 230 @ Save the current VFP state 231 @ r0 - save location 232 @ r1 - FPEXC 233 DBGSTR1 "save VFP state %p", r0 234 VFPFSTMIA r0, r2 @ save the working registers 235 VFPFMRX r2, FPSCR @ current status 236 tst r1, #FPEXC_EX @ is there additional state to save? 237 beq 1f 238 VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) 239 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? 240 beq 1f 241 VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) 2421: 243 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 244 mov pc, lr 245ENDPROC(vfp_save_state) 246 247 .align 248vfp_current_hw_state_address: 249 .word vfp_current_hw_state 250 251 .macro tbl_branch, base, tmp, shift 252#ifdef CONFIG_THUMB2_KERNEL 253 adr \tmp, 1f 254 add \tmp, \tmp, \base, lsl \shift 255 mov pc, \tmp 256#else 257 add pc, pc, \base, lsl \shift 258 mov r0, r0 259#endif 2601: 261 .endm 262 263ENTRY(vfp_get_float) 264 tbl_branch r0, r3, #3 265 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2661: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 267 mov pc, lr 268 .org 1b + 8 2691: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 270 mov pc, lr 271 .org 1b + 8 272 .endr 273ENDPROC(vfp_get_float) 274 275ENTRY(vfp_put_float) 276 tbl_branch r1, r3, #3 277 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2781: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 279 mov pc, lr 280 .org 1b + 8 2811: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 282 mov pc, lr 283 .org 1b + 8 284 .endr 285ENDPROC(vfp_put_float) 286 287ENTRY(vfp_get_double) 288 tbl_branch r0, r3, #3 289 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2901: fmrrd r0, r1, d\dr 291 mov pc, lr 292 .org 1b + 8 293 .endr 294#ifdef CONFIG_VFPv3 295 @ d16 - d31 registers 296 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2971: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr 298 mov pc, lr 299 .org 1b + 8 300 .endr 301#endif 302 303 @ virtual register 16 (or 32 if VFPv3) for compare with zero 304 mov r0, #0 305 mov r1, #0 306 mov pc, lr 307ENDPROC(vfp_get_double) 308 309ENTRY(vfp_put_double) 310 tbl_branch r2, r3, #3 311 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 3121: fmdrr d\dr, r0, r1 313 mov pc, lr 314 .org 1b + 8 315 .endr 316#ifdef CONFIG_VFPv3 317 @ d16 - d31 registers 318 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 3191: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr 320 mov pc, lr 321 .org 1b + 8 322 .endr 323#endif 324ENDPROC(vfp_put_double) 325