1/* 2 * linux/arch/arm/vfp/vfphw.S 3 * 4 * Copyright (C) 2004 ARM Limited. 5 * Written by Deep Blue Solutions Limited. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This code is called from the kernel's undefined instruction trap. 12 * r9 holds the return address for successful handling. 13 * lr holds the return address for unrecognised instructions. 14 * r10 points at the start of the private FP workspace in the thread structure 15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) 16 */ 17#include <asm/thread_info.h> 18#include <asm/vfpmacros.h> 19#include <linux/kern_levels.h> 20#include "../kernel/entry-header.S" 21 22 .macro DBGSTR, str 23#ifdef DEBUG 24 stmfd sp!, {r0-r3, ip, lr} 25 ldr r0, =1f 26 bl printk 27 ldmfd sp!, {r0-r3, ip, lr} 28 29 .pushsection .rodata, "a" 301: .ascii KERN_DEBUG "VFP: \str\n" 31 .byte 0 32 .previous 33#endif 34 .endm 35 36 .macro DBGSTR1, str, arg 37#ifdef DEBUG 38 stmfd sp!, {r0-r3, ip, lr} 39 mov r1, \arg 40 ldr r0, =1f 41 bl printk 42 ldmfd sp!, {r0-r3, ip, lr} 43 44 .pushsection .rodata, "a" 451: .ascii KERN_DEBUG "VFP: \str\n" 46 .byte 0 47 .previous 48#endif 49 .endm 50 51 .macro DBGSTR3, str, arg1, arg2, arg3 52#ifdef DEBUG 53 stmfd sp!, {r0-r3, ip, lr} 54 mov r3, \arg3 55 mov r2, \arg2 56 mov r1, \arg1 57 ldr r0, =1f 58 bl printk 59 ldmfd sp!, {r0-r3, ip, lr} 60 61 .pushsection .rodata, "a" 621: .ascii KERN_DEBUG "VFP: \str\n" 63 .byte 0 64 .previous 65#endif 66 .endm 67 68 69@ VFP hardware support entry point. 70@ 71@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) 72@ r2 = PC value to resume execution after successful emulation 73@ r9 = normal "successful" return address 74@ r10 = vfp_state union 75@ r11 = CPU number 76@ lr = unrecognised instruction return address 77@ IRQs enabled. 78ENTRY(vfp_support_entry) 79 DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 80 81 VFPFMRX r1, FPEXC @ Is the VFP enabled? 82 DBGSTR1 "fpexc %08x", r1 83 tst r1, #FPEXC_EN 84 bne look_for_VFP_exceptions @ VFP is already enabled 85 86 DBGSTR1 "enable %x", r10 87 ldr r3, vfp_current_hw_state_address 88 orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set 89 ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer 90 bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled 91 cmp r4, r10 @ this thread owns the hw context? 92#ifndef CONFIG_SMP 93 @ For UP, checking that this thread owns the hw context is 94 @ sufficient to determine that the hardware state is valid. 95 beq vfp_hw_state_valid 96 97 @ On UP, we lazily save the VFP context. As a different 98 @ thread wants ownership of the VFP hardware, save the old 99 @ state if there was a previous (valid) owner. 100 101 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending 102 @ exceptions, so we can get at the 103 @ rest of it 104 105 DBGSTR1 "save old state %p", r4 106 cmp r4, #0 @ if the vfp_current_hw_state is NULL 107 beq vfp_reload_hw @ then the hw state needs reloading 108 VFPFSTMIA r4, r5 @ save the working registers 109 VFPFMRX r5, FPSCR @ current status 110#ifndef CONFIG_CPU_FEROCEON 111 tst r1, #FPEXC_EX @ is there additional state to save? 112 beq 1f 113 VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) 114 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? 115 beq 1f 116 VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1171: 118#endif 119 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 120vfp_reload_hw: 121 122#else 123 @ For SMP, if this thread does not own the hw context, then we 124 @ need to reload it. No need to save the old state as on SMP, 125 @ we always save the state when we switch away from a thread. 126 bne vfp_reload_hw 127 128 @ This thread has ownership of the current hardware context. 129 @ However, it may have been migrated to another CPU, in which 130 @ case the saved state is newer than the hardware context. 131 @ Check this by looking at the CPU number which the state was 132 @ last loaded onto. 133 ldr ip, [r10, #VFP_CPU] 134 teq ip, r11 135 beq vfp_hw_state_valid 136 137vfp_reload_hw: 138 @ We're loading this threads state into the VFP hardware. Update 139 @ the CPU number which contains the most up to date VFP context. 140 str r11, [r10, #VFP_CPU] 141 142 VFPFMXR FPEXC, r5 @ enable VFP, disable any pending 143 @ exceptions, so we can get at the 144 @ rest of it 145#endif 146 147 DBGSTR1 "load state %p", r10 148 str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer 149 @ Load the saved state back into the VFP 150 VFPFLDMIA r10, r5 @ reload the working registers while 151 @ FPEXC is in a safe state 152 ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 153#ifndef CONFIG_CPU_FEROCEON 154 tst r1, #FPEXC_EX @ is there additional state to restore? 155 beq 1f 156 VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) 157 tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? 158 beq 1f 159 VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) 1601: 161#endif 162 VFPFMXR FPSCR, r5 @ restore status 163 164@ The context stored in the VFP hardware is up to date with this thread 165vfp_hw_state_valid: 166 tst r1, #FPEXC_EX 167 bne process_exception @ might as well handle the pending 168 @ exception before retrying branch 169 @ out before setting an FPEXC that 170 @ stops us reading stuff 171 VFPFMXR FPEXC, r1 @ Restore FPEXC last 172 sub r2, r2, #4 @ Retry current instruction - if Thumb 173 str r2, [sp, #S_PC] @ mode it's two 16-bit instructions, 174 @ else it's one 32-bit instruction, so 175 @ always subtract 4 from the following 176 @ instruction address. 177#ifdef CONFIG_PREEMPT_COUNT 178 get_thread_info r10 179 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 180 sub r11, r4, #1 @ decrement it 181 str r11, [r10, #TI_PREEMPT] 182#endif 183 mov pc, r9 @ we think we have handled things 184 185 186look_for_VFP_exceptions: 187 @ Check for synchronous or asynchronous exception 188 tst r1, #FPEXC_EX | FPEXC_DEX 189 bne process_exception 190 @ On some implementations of the VFP subarch 1, setting FPSCR.IXE 191 @ causes all the CDP instructions to be bounced synchronously without 192 @ setting the FPEXC.EX bit 193 VFPFMRX r5, FPSCR 194 tst r5, #FPSCR_IXE 195 bne process_exception 196 197 @ Fall into hand on to next handler - appropriate coproc instr 198 @ not recognised by VFP 199 200 DBGSTR "not VFP" 201#ifdef CONFIG_PREEMPT_COUNT 202 get_thread_info r10 203 ldr r4, [r10, #TI_PREEMPT] @ get preempt count 204 sub r11, r4, #1 @ decrement it 205 str r11, [r10, #TI_PREEMPT] 206#endif 207 mov pc, lr 208 209process_exception: 210 DBGSTR "bounce" 211 mov r2, sp @ nothing stacked - regdump is at TOS 212 mov lr, r9 @ setup for a return to the user code. 213 214 @ Now call the C code to package up the bounce to the support code 215 @ r0 holds the trigger instruction 216 @ r1 holds the FPEXC value 217 @ r2 pointer to register dump 218 b VFP_bounce @ we have handled this - the support 219 @ code will raise an exception if 220 @ required. If not, the user code will 221 @ retry the faulted instruction 222ENDPROC(vfp_support_entry) 223 224ENTRY(vfp_save_state) 225 @ Save the current VFP state 226 @ r0 - save location 227 @ r1 - FPEXC 228 DBGSTR1 "save VFP state %p", r0 229 VFPFSTMIA r0, r2 @ save the working registers 230 VFPFMRX r2, FPSCR @ current status 231 tst r1, #FPEXC_EX @ is there additional state to save? 232 beq 1f 233 VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) 234 tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? 235 beq 1f 236 VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) 2371: 238 stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 239 mov pc, lr 240ENDPROC(vfp_save_state) 241 242 .align 243vfp_current_hw_state_address: 244 .word vfp_current_hw_state 245 246 .macro tbl_branch, base, tmp, shift 247#ifdef CONFIG_THUMB2_KERNEL 248 adr \tmp, 1f 249 add \tmp, \tmp, \base, lsl \shift 250 mov pc, \tmp 251#else 252 add pc, pc, \base, lsl \shift 253 mov r0, r0 254#endif 2551: 256 .endm 257 258ENTRY(vfp_get_float) 259 tbl_branch r0, r3, #3 260 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2611: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 262 mov pc, lr 263 .org 1b + 8 2641: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 265 mov pc, lr 266 .org 1b + 8 267 .endr 268ENDPROC(vfp_get_float) 269 270ENTRY(vfp_put_float) 271 tbl_branch r1, r3, #3 272 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2731: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 274 mov pc, lr 275 .org 1b + 8 2761: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 277 mov pc, lr 278 .org 1b + 8 279 .endr 280ENDPROC(vfp_put_float) 281 282ENTRY(vfp_get_double) 283 tbl_branch r0, r3, #3 284 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2851: fmrrd r0, r1, d\dr 286 mov pc, lr 287 .org 1b + 8 288 .endr 289#ifdef CONFIG_VFPv3 290 @ d16 - d31 registers 291 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 2921: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr 293 mov pc, lr 294 .org 1b + 8 295 .endr 296#endif 297 298 @ virtual register 16 (or 32 if VFPv3) for compare with zero 299 mov r0, #0 300 mov r1, #0 301 mov pc, lr 302ENDPROC(vfp_get_double) 303 304ENTRY(vfp_put_double) 305 tbl_branch r2, r3, #3 306 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 3071: fmdrr d\dr, r0, r1 308 mov pc, lr 309 .org 1b + 8 310 .endr 311#ifdef CONFIG_VFPv3 312 @ d16 - d31 registers 313 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 3141: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr 315 mov pc, lr 316 .org 1b + 8 317 .endr 318#endif 319ENDPROC(vfp_put_double) 320