xref: /openbmc/linux/arch/arm/vfp/vfphw.S (revision 367b8112) 
1/*
2 *  linux/arch/arm/vfp/vfphw.S
3 *
4 *  Copyright (C) 2004 ARM Limited.
5 *  Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This code is called from the kernel's undefined instruction trap.
12 * r9 holds the return address for successful handling.
13 * lr holds the return address for unrecognised instructions.
14 * r10 points at the start of the private FP workspace in the thread structure
15 * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
16 */
17#include <asm/thread_info.h>
18#include <asm/vfpmacros.h>
19#include "../kernel/entry-header.S"
20
21	.macro	DBGSTR, str
22#ifdef DEBUG
23	stmfd	sp!, {r0-r3, ip, lr}
24	add	r0, pc, #4
25	bl	printk
26	b	1f
27	.asciz  "<7>VFP: \str\n"
28	.balign 4
291:	ldmfd	sp!, {r0-r3, ip, lr}
30#endif
31	.endm
32
33	.macro  DBGSTR1, str, arg
34#ifdef DEBUG
35	stmfd	sp!, {r0-r3, ip, lr}
36	mov	r1, \arg
37	add	r0, pc, #4
38	bl	printk
39	b	1f
40	.asciz  "<7>VFP: \str\n"
41	.balign 4
421:	ldmfd	sp!, {r0-r3, ip, lr}
43#endif
44	.endm
45
46	.macro  DBGSTR3, str, arg1, arg2, arg3
47#ifdef DEBUG
48	stmfd	sp!, {r0-r3, ip, lr}
49	mov	r3, \arg3
50	mov	r2, \arg2
51	mov	r1, \arg1
52	add	r0, pc, #4
53	bl	printk
54	b	1f
55	.asciz  "<7>VFP: \str\n"
56	.balign 4
571:	ldmfd	sp!, {r0-r3, ip, lr}
58#endif
59	.endm
60
61
62@ VFP hardware support entry point.
63@
64@  r0  = faulted instruction
65@  r2  = faulted PC+4
66@  r9  = successful return
67@  r10 = vfp_state union
68@  r11 = CPU number
69@  lr  = failure return
70
71ENTRY(vfp_support_entry)
72	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10
73
74	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
75	DBGSTR1	"fpexc %08x", r1
76	tst	r1, #FPEXC_EN
77	bne	look_for_VFP_exceptions	@ VFP is already enabled
78
79	DBGSTR1 "enable %x", r10
80	ldr	r3, last_VFP_context_address
81	orr	r1, r1, #FPEXC_EN	@ user FPEXC has the enable bit set
82	ldr	r4, [r3, r11, lsl #2]	@ last_VFP_context pointer
83	bic	r5, r1, #FPEXC_EX	@ make sure exceptions are disabled
84	cmp	r4, r10
85	beq	check_for_exception	@ we are returning to the same
86					@ process, so the registers are
87					@ still there.  In this case, we do
88					@ not want to drop a pending exception.
89
90	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
91					@ exceptions, so we can get at the
92					@ rest of it
93
94#ifndef CONFIG_SMP
95	@ Save out the current registers to the old thread state
96	@ No need for SMP since this is not done lazily
97
98	DBGSTR1	"save old state %p", r4
99	cmp	r4, #0
100	beq	no_old_VFP_process
101	VFPFSTMIA r4, r5		@ save the working registers
102	VFPFMRX	r5, FPSCR		@ current status
103	tst	r1, #FPEXC_EX		@ is there additional state to save?
104	VFPFMRX	r6, FPINST, NE		@ FPINST (only if FPEXC.EX is set)
105	tstne	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
106	VFPFMRX	r8, FPINST2, NE		@ FPINST2 if needed (and present)
107	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
108					@ and point r4 at the word at the
109					@ start of the register dump
110#endif
111
112no_old_VFP_process:
113	DBGSTR1	"load state %p", r10
114	str	r10, [r3, r11, lsl #2]	@ update the last_VFP_context pointer
115					@ Load the saved state back into the VFP
116	VFPFLDMIA r10, r5		@ reload the working registers while
117					@ FPEXC is in a safe state
118	ldmia	r10, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
119	tst	r1, #FPEXC_EX		@ is there additional state to restore?
120	VFPFMXR	FPINST, r6, NE		@ restore FPINST (only if FPEXC.EX is set)
121	tstne	r1, #FPEXC_FP2V		@ is there an FPINST2 to write?
122	VFPFMXR	FPINST2, r8, NE		@ FPINST2 if needed (and present)
123	VFPFMXR	FPSCR, r5		@ restore status
124
125check_for_exception:
126	tst	r1, #FPEXC_EX
127	bne	process_exception	@ might as well handle the pending
128					@ exception before retrying branch
129					@ out before setting an FPEXC that
130					@ stops us reading stuff
131	VFPFMXR	FPEXC, r1		@ restore FPEXC last
132	sub	r2, r2, #4
133	str	r2, [sp, #S_PC]		@ retry the instruction
134	mov	pc, r9			@ we think we have handled things
135
136
137look_for_VFP_exceptions:
138	@ Check for synchronous or asynchronous exception
139	tst	r1, #FPEXC_EX | FPEXC_DEX
140	bne	process_exception
141	@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
142	@ causes all the CDP instructions to be bounced synchronously without
143	@ setting the FPEXC.EX bit
144	VFPFMRX	r5, FPSCR
145	tst	r5, #FPSCR_IXE
146	bne	process_exception
147
148	@ Fall into hand on to next handler - appropriate coproc instr
149	@ not recognised by VFP
150
151	DBGSTR	"not VFP"
152	mov	pc, lr
153
154process_exception:
155	DBGSTR	"bounce"
156	mov	r2, sp			@ nothing stacked - regdump is at TOS
157	mov	lr, r9			@ setup for a return to the user code.
158
159	@ Now call the C code to package up the bounce to the support code
160	@   r0 holds the trigger instruction
161	@   r1 holds the FPEXC value
162	@   r2 pointer to register dump
163	b	VFP_bounce		@ we have handled this - the support
164					@ code will raise an exception if
165					@ required. If not, the user code will
166					@ retry the faulted instruction
167ENDPROC(vfp_support_entry)
168
169#ifdef CONFIG_SMP
170ENTRY(vfp_save_state)
171	@ Save the current VFP state
172	@ r0 - save location
173	@ r1 - FPEXC
174	DBGSTR1	"save VFP state %p", r0
175	VFPFSTMIA r0, r2		@ save the working registers
176	VFPFMRX	r2, FPSCR		@ current status
177	tst	r1, #FPEXC_EX		@ is there additional state to save?
178	VFPFMRX	r3, FPINST, NE		@ FPINST (only if FPEXC.EX is set)
179	tstne	r1, #FPEXC_FP2V		@ is there an FPINST2 to read?
180	VFPFMRX	r12, FPINST2, NE	@ FPINST2 if needed (and present)
181	stmia	r0, {r1, r2, r3, r12}	@ save FPEXC, FPSCR, FPINST, FPINST2
182	mov	pc, lr
183ENDPROC(vfp_save_state)
184#endif
185
186last_VFP_context_address:
187	.word	last_VFP_context
188
189ENTRY(vfp_get_float)
190	add	pc, pc, r0, lsl #3
191	mov	r0, r0
192	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
193	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
194	mov	pc, lr
195	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
196	mov	pc, lr
197	.endr
198ENDPROC(vfp_get_float)
199
200ENTRY(vfp_put_float)
201	add	pc, pc, r1, lsl #3
202	mov	r0, r0
203	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
204	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
205	mov	pc, lr
206	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
207	mov	pc, lr
208	.endr
209ENDPROC(vfp_put_float)
210
211ENTRY(vfp_get_double)
212	add	pc, pc, r0, lsl #3
213	mov	r0, r0
214	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
215	fmrrd	r0, r1, d\dr
216	mov	pc, lr
217	.endr
218#ifdef CONFIG_VFPv3
219	@ d16 - d31 registers
220	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
221	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
222	mov	pc, lr
223	.endr
224#endif
225
226	@ virtual register 16 (or 32 if VFPv3) for compare with zero
227	mov	r0, #0
228	mov	r1, #0
229	mov	pc, lr
230ENDPROC(vfp_get_double)
231
232ENTRY(vfp_put_double)
233	add	pc, pc, r2, lsl #3
234	mov	r0, r0
235	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
236	fmdrr	d\dr, r0, r1
237	mov	pc, lr
238	.endr
239#ifdef CONFIG_VFPv3
240	@ d16 - d31 registers
241	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
242	mcrr	p11, 3, r1, r2, c\dr	@ fmdrr	r1, r2, d\dr
243	mov	pc, lr
244	.endr
245#endif
246ENDPROC(vfp_put_double)
247