16624cf65SWang Nan /*
26624cf65SWang Nan  * arch/arm/probes/kprobes/checkers-arm.c
36624cf65SWang Nan  *
46624cf65SWang Nan  * Copyright (C) 2014 Huawei Inc.
56624cf65SWang Nan  *
66624cf65SWang Nan  * This program is free software; you can redistribute it and/or modify
76624cf65SWang Nan  * it under the terms of the GNU General Public License version 2 as
86624cf65SWang Nan  * published by the Free Software Foundation.
96624cf65SWang Nan  *
106624cf65SWang Nan  * This program is distributed in the hope that it will be useful,
116624cf65SWang Nan  * but WITHOUT ANY WARRANTY; without even the implied warranty of
126624cf65SWang Nan  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
136624cf65SWang Nan  * General Public License for more details.
146624cf65SWang Nan  */
156624cf65SWang Nan 
166624cf65SWang Nan #include <linux/kernel.h>
176624cf65SWang Nan #include "../decode.h"
186624cf65SWang Nan #include "../decode-arm.h"
196624cf65SWang Nan #include "checkers.h"
206624cf65SWang Nan 
216624cf65SWang Nan static enum probes_insn __kprobes arm_check_stack(probes_opcode_t insn,
226624cf65SWang Nan 		struct arch_probes_insn *asi,
236624cf65SWang Nan 		const struct decode_header *h)
246624cf65SWang Nan {
256624cf65SWang Nan 	/*
266624cf65SWang Nan 	 * PROBES_LDRSTRD, PROBES_LDMSTM, PROBES_STORE,
276624cf65SWang Nan 	 * PROBES_STORE_EXTRA may get here. Simply mark all normal
286624cf65SWang Nan 	 * insns as STACK_USE_NONE.
296624cf65SWang Nan 	 */
306624cf65SWang Nan 	static const union decode_item table[] = {
316624cf65SWang Nan 		/*
326624cf65SWang Nan 		 * 'STR{,D,B,H}, Rt, [Rn, Rm]' should be marked as UNKNOWN
336624cf65SWang Nan 		 * if Rn or Rm is SP.
346624cf65SWang Nan 		 *                                 x
356624cf65SWang Nan 		 * STR (register)	cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx
366624cf65SWang Nan 		 * STRB (register)	cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx
376624cf65SWang Nan 		 */
386624cf65SWang Nan 		DECODE_OR	(0x0e10000f, 0x0600000d),
396624cf65SWang Nan 		DECODE_OR	(0x0e1f0000, 0x060d0000),
406624cf65SWang Nan 
416624cf65SWang Nan 		/*
426624cf65SWang Nan 		 *                                                     x
436624cf65SWang Nan 		 * STRD (register)	cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
446624cf65SWang Nan 		 * STRH (register)	cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx
456624cf65SWang Nan 		 */
466624cf65SWang Nan 		DECODE_OR	(0x0e5000bf, 0x000000bd),
476624cf65SWang Nan 		DECODE_CUSTOM	(0x0e5f00b0, 0x000d00b0, STACK_USE_UNKNOWN),
486624cf65SWang Nan 
496624cf65SWang Nan 		/*
506624cf65SWang Nan 		 * For PROBES_LDMSTM, only stmdx sp, [...] need to examine
516624cf65SWang Nan 		 *
526624cf65SWang Nan 		 * Bit B/A (bit 24) encodes arithmetic operation order. 1 means
536624cf65SWang Nan 		 * before, 0 means after.
546624cf65SWang Nan 		 * Bit I/D (bit 23) encodes arithmetic operation. 1 means
556624cf65SWang Nan 		 * increment, 0 means decrement.
566624cf65SWang Nan 		 *
576624cf65SWang Nan 		 * So:
586624cf65SWang Nan 		 *                              B I
596624cf65SWang Nan 		 *                              / /
606624cf65SWang Nan 		 *                              A D   | Rn |
616624cf65SWang Nan 		 * STMDX SP, [...]	cccc 100x 00x0 xxxx xxxx xxxx xxxx xxxx
626624cf65SWang Nan 		 */
636624cf65SWang Nan 		DECODE_CUSTOM	(0x0edf0000, 0x080d0000, STACK_USE_STMDX),
646624cf65SWang Nan 
656624cf65SWang Nan 		/*                              P U W | Rn | Rt |     imm12    |*/
666624cf65SWang Nan 		/* STR (immediate)	cccc 010x x0x0 1101 xxxx xxxx xxxx xxxx */
676624cf65SWang Nan 		/* STRB (immediate)	cccc 010x x1x0 1101 xxxx xxxx xxxx xxxx */
686624cf65SWang Nan 		/*                              P U W | Rn | Rt |imm4|    |imm4|*/
696624cf65SWang Nan 		/* STRD (immediate)	cccc 000x x1x0 1101 xxxx xxxx 1111 xxxx */
706624cf65SWang Nan 		/* STRH (immediate)	cccc 000x x1x0 1101 xxxx xxxx 1011 xxxx */
716624cf65SWang Nan 		/*
726624cf65SWang Nan 		 * index = (P == '1'); add = (U == '1').
736624cf65SWang Nan 		 * Above insns with:
746624cf65SWang Nan 		 *    index == 0 (str{,d,h} rx, [sp], #+/-imm) or
756624cf65SWang Nan 		 *    add == 1 (str{,d,h} rx, [sp, #+<imm>])
766624cf65SWang Nan 		 * should be STACK_USE_NONE.
776624cf65SWang Nan 		 * Only str{,b,d,h} rx,[sp,#-n] (P == 1 and U == 0) are
786624cf65SWang Nan 		 * required to be examined.
796624cf65SWang Nan 		 */
806624cf65SWang Nan 		/* STR{,B} Rt,[SP,#-n]	cccc 0101 0xx0 1101 xxxx xxxx xxxx xxxx */
816624cf65SWang Nan 		DECODE_CUSTOM	(0x0f9f0000, 0x050d0000, STACK_USE_FIXED_XXX),
826624cf65SWang Nan 
836624cf65SWang Nan 		/* STR{D,H} Rt,[SP,#-n]	cccc 0001 01x0 1101 xxxx xxxx 1x11 xxxx */
846624cf65SWang Nan 		DECODE_CUSTOM	(0x0fdf00b0, 0x014d00b0, STACK_USE_FIXED_X0X),
856624cf65SWang Nan 
866624cf65SWang Nan 		/* fall through */
876624cf65SWang Nan 		DECODE_CUSTOM	(0, 0, STACK_USE_NONE),
886624cf65SWang Nan 		DECODE_END
896624cf65SWang Nan 	};
906624cf65SWang Nan 
916624cf65SWang Nan 	return probes_decode_insn(insn, asi, table, false, false, stack_check_actions, NULL);
926624cf65SWang Nan }
936624cf65SWang Nan 
946624cf65SWang Nan const struct decode_checker arm_stack_checker[NUM_PROBES_ARM_ACTIONS] = {
956624cf65SWang Nan 	[PROBES_LDRSTRD] = {.checker = arm_check_stack},
966624cf65SWang Nan 	[PROBES_STORE_EXTRA] = {.checker = arm_check_stack},
976624cf65SWang Nan 	[PROBES_STORE] = {.checker = arm_check_stack},
986624cf65SWang Nan 	[PROBES_LDMSTM] = {.checker = arm_check_stack},
996624cf65SWang Nan };
10028a1899dSWang Nan 
10128a1899dSWang Nan static enum probes_insn __kprobes arm_check_regs_nouse(probes_opcode_t insn,
10228a1899dSWang Nan 		struct arch_probes_insn *asi,
10328a1899dSWang Nan 		const struct decode_header *h)
10428a1899dSWang Nan {
10528a1899dSWang Nan 	asi->register_usage_flags = 0;
10628a1899dSWang Nan 	return INSN_GOOD;
10728a1899dSWang Nan }
10828a1899dSWang Nan 
10928a1899dSWang Nan static enum probes_insn arm_check_regs_normal(probes_opcode_t insn,
11028a1899dSWang Nan 		struct arch_probes_insn *asi,
11128a1899dSWang Nan 		const struct decode_header *h)
11228a1899dSWang Nan {
11328a1899dSWang Nan 	u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
11428a1899dSWang Nan 	int i;
11528a1899dSWang Nan 
11628a1899dSWang Nan 	asi->register_usage_flags = 0;
11728a1899dSWang Nan 	for (i = 0; i < 5; regs >>= 4, insn >>= 4, i++)
11828a1899dSWang Nan 		if (regs & 0xf)
11928a1899dSWang Nan 			asi->register_usage_flags |= 1 << (insn & 0xf);
12028a1899dSWang Nan 
12128a1899dSWang Nan 	return INSN_GOOD;
12228a1899dSWang Nan }
12328a1899dSWang Nan 
12428a1899dSWang Nan 
12528a1899dSWang Nan static enum probes_insn arm_check_regs_ldmstm(probes_opcode_t insn,
12628a1899dSWang Nan 		struct arch_probes_insn *asi,
12728a1899dSWang Nan 		const struct decode_header *h)
12828a1899dSWang Nan {
12928a1899dSWang Nan 	unsigned int reglist = insn & 0xffff;
13028a1899dSWang Nan 	unsigned int rn = (insn >> 16) & 0xf;
13128a1899dSWang Nan 	asi->register_usage_flags = reglist | (1 << rn);
13228a1899dSWang Nan 	return INSN_GOOD;
13328a1899dSWang Nan }
13428a1899dSWang Nan 
13528a1899dSWang Nan static enum probes_insn arm_check_regs_mov_ip_sp(probes_opcode_t insn,
13628a1899dSWang Nan 		struct arch_probes_insn *asi,
13728a1899dSWang Nan 		const struct decode_header *h)
13828a1899dSWang Nan {
13928a1899dSWang Nan 	/* Instruction is 'mov ip, sp' i.e. 'mov r12, r13' */
14028a1899dSWang Nan 	asi->register_usage_flags = (1 << 12) | (1<< 13);
14128a1899dSWang Nan 	return INSN_GOOD;
14228a1899dSWang Nan }
14328a1899dSWang Nan 
14428a1899dSWang Nan /*
14528a1899dSWang Nan  *                                    | Rn |Rt/d|         | Rm |
14628a1899dSWang Nan  * LDRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx
14728a1899dSWang Nan  * STRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
14828a1899dSWang Nan  *                                    | Rn |Rt/d|         |imm4L|
14928a1899dSWang Nan  * LDRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx
15028a1899dSWang Nan  * STRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx
15128a1899dSWang Nan  *
15228a1899dSWang Nan  * Such instructions access Rt/d and its next register, so different
15328a1899dSWang Nan  * from others, a specific checker is required to handle this extra
15428a1899dSWang Nan  * implicit register usage.
15528a1899dSWang Nan  */
15628a1899dSWang Nan static enum probes_insn arm_check_regs_ldrdstrd(probes_opcode_t insn,
15728a1899dSWang Nan 		struct arch_probes_insn *asi,
15828a1899dSWang Nan 		const struct decode_header *h)
15928a1899dSWang Nan {
16028a1899dSWang Nan 	int rdt = (insn >> 12) & 0xf;
16128a1899dSWang Nan 	arm_check_regs_normal(insn, asi, h);
16228a1899dSWang Nan 	asi->register_usage_flags |= 1 << (rdt + 1);
16328a1899dSWang Nan 	return INSN_GOOD;
16428a1899dSWang Nan }
16528a1899dSWang Nan 
16628a1899dSWang Nan 
16728a1899dSWang Nan const struct decode_checker arm_regs_checker[NUM_PROBES_ARM_ACTIONS] = {
16828a1899dSWang Nan 	[PROBES_MRS] = {.checker = arm_check_regs_normal},
16928a1899dSWang Nan 	[PROBES_SATURATING_ARITHMETIC] = {.checker = arm_check_regs_normal},
17028a1899dSWang Nan 	[PROBES_MUL1] = {.checker = arm_check_regs_normal},
17128a1899dSWang Nan 	[PROBES_MUL2] = {.checker = arm_check_regs_normal},
17228a1899dSWang Nan 	[PROBES_MUL_ADD_LONG] = {.checker = arm_check_regs_normal},
17328a1899dSWang Nan 	[PROBES_MUL_ADD] = {.checker = arm_check_regs_normal},
17428a1899dSWang Nan 	[PROBES_LOAD] = {.checker = arm_check_regs_normal},
17528a1899dSWang Nan 	[PROBES_LOAD_EXTRA] = {.checker = arm_check_regs_normal},
17628a1899dSWang Nan 	[PROBES_STORE] = {.checker = arm_check_regs_normal},
17728a1899dSWang Nan 	[PROBES_STORE_EXTRA] = {.checker = arm_check_regs_normal},
17828a1899dSWang Nan 	[PROBES_DATA_PROCESSING_REG] = {.checker = arm_check_regs_normal},
17928a1899dSWang Nan 	[PROBES_DATA_PROCESSING_IMM] = {.checker = arm_check_regs_normal},
18028a1899dSWang Nan 	[PROBES_SEV] = {.checker = arm_check_regs_nouse},
18128a1899dSWang Nan 	[PROBES_WFE] = {.checker = arm_check_regs_nouse},
18228a1899dSWang Nan 	[PROBES_SATURATE] = {.checker = arm_check_regs_normal},
18328a1899dSWang Nan 	[PROBES_REV] = {.checker = arm_check_regs_normal},
18428a1899dSWang Nan 	[PROBES_MMI] = {.checker = arm_check_regs_normal},
18528a1899dSWang Nan 	[PROBES_PACK] = {.checker = arm_check_regs_normal},
18628a1899dSWang Nan 	[PROBES_EXTEND] = {.checker = arm_check_regs_normal},
18728a1899dSWang Nan 	[PROBES_EXTEND_ADD] = {.checker = arm_check_regs_normal},
18828a1899dSWang Nan 	[PROBES_BITFIELD] = {.checker = arm_check_regs_normal},
18928a1899dSWang Nan 	[PROBES_LDMSTM] = {.checker = arm_check_regs_ldmstm},
19028a1899dSWang Nan 	[PROBES_MOV_IP_SP] = {.checker = arm_check_regs_mov_ip_sp},
19128a1899dSWang Nan 	[PROBES_LDRSTRD] = {.checker = arm_check_regs_ldrdstrd},
19228a1899dSWang Nan };
193