1fcaf2036SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2fca08f32SWang Nan /* 3fca08f32SWang Nan * arch/arm/probes/decode-thumb.h 4fca08f32SWang Nan * 5fca08f32SWang Nan * Copyright 2013 Linaro Ltd. 6fca08f32SWang Nan * Written by: David A. Long 7fca08f32SWang Nan */ 8fca08f32SWang Nan 9fca08f32SWang Nan #ifndef _ARM_KERNEL_PROBES_THUMB_H 10fca08f32SWang Nan #define _ARM_KERNEL_PROBES_THUMB_H 11fca08f32SWang Nan 12fca08f32SWang Nan #include "decode.h" 13fca08f32SWang Nan 14fca08f32SWang Nan /* 15fca08f32SWang Nan * True if current instruction is in an IT block. 16fca08f32SWang Nan */ 17fca08f32SWang Nan #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000) 18fca08f32SWang Nan 19fca08f32SWang Nan /* 20fca08f32SWang Nan * Return the condition code to check for the currently executing instruction. 21fca08f32SWang Nan * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if 22fca08f32SWang Nan * in_it_block returns true. 23fca08f32SWang Nan */ 24fca08f32SWang Nan #define current_cond(cpsr) ((cpsr >> 12) & 0xf) 25fca08f32SWang Nan 26fca08f32SWang Nan enum probes_t32_action { 27fca08f32SWang Nan PROBES_T32_EMULATE_NONE, 28fca08f32SWang Nan PROBES_T32_SIMULATE_NOP, 29fca08f32SWang Nan PROBES_T32_LDMSTM, 30fca08f32SWang Nan PROBES_T32_LDRDSTRD, 31fca08f32SWang Nan PROBES_T32_TABLE_BRANCH, 32fca08f32SWang Nan PROBES_T32_TST, 33fca08f32SWang Nan PROBES_T32_CMP, 34fca08f32SWang Nan PROBES_T32_MOV, 35fca08f32SWang Nan PROBES_T32_ADDSUB, 36fca08f32SWang Nan PROBES_T32_LOGICAL, 37fca08f32SWang Nan PROBES_T32_ADDWSUBW_PC, 38fca08f32SWang Nan PROBES_T32_ADDWSUBW, 39fca08f32SWang Nan PROBES_T32_MOVW, 40fca08f32SWang Nan PROBES_T32_SAT, 41fca08f32SWang Nan PROBES_T32_BITFIELD, 42fca08f32SWang Nan PROBES_T32_SEV, 43fca08f32SWang Nan PROBES_T32_WFE, 44fca08f32SWang Nan PROBES_T32_MRS, 45fca08f32SWang Nan PROBES_T32_BRANCH_COND, 46fca08f32SWang Nan PROBES_T32_BRANCH, 47fca08f32SWang Nan PROBES_T32_PLDI, 48fca08f32SWang Nan PROBES_T32_LDR_LIT, 49fca08f32SWang Nan PROBES_T32_LDRSTR, 50fca08f32SWang Nan PROBES_T32_SIGN_EXTEND, 51fca08f32SWang Nan PROBES_T32_MEDIA, 52fca08f32SWang Nan PROBES_T32_REVERSE, 53fca08f32SWang Nan PROBES_T32_MUL_ADD, 54fca08f32SWang Nan PROBES_T32_MUL_ADD2, 55fca08f32SWang Nan PROBES_T32_MUL_ADD_LONG, 56fca08f32SWang Nan NUM_PROBES_T32_ACTIONS 57fca08f32SWang Nan }; 58fca08f32SWang Nan 59fca08f32SWang Nan enum probes_t16_action { 60fca08f32SWang Nan PROBES_T16_ADD_SP, 61fca08f32SWang Nan PROBES_T16_CBZ, 62fca08f32SWang Nan PROBES_T16_SIGN_EXTEND, 63fca08f32SWang Nan PROBES_T16_PUSH, 64fca08f32SWang Nan PROBES_T16_POP, 65fca08f32SWang Nan PROBES_T16_SEV, 66fca08f32SWang Nan PROBES_T16_WFE, 67fca08f32SWang Nan PROBES_T16_IT, 68fca08f32SWang Nan PROBES_T16_CMP, 69fca08f32SWang Nan PROBES_T16_ADDSUB, 70fca08f32SWang Nan PROBES_T16_LOGICAL, 71fca08f32SWang Nan PROBES_T16_BLX, 72fca08f32SWang Nan PROBES_T16_HIREGOPS, 73fca08f32SWang Nan PROBES_T16_LDR_LIT, 74fca08f32SWang Nan PROBES_T16_LDRHSTRH, 75fca08f32SWang Nan PROBES_T16_LDRSTR, 76fca08f32SWang Nan PROBES_T16_ADR, 77fca08f32SWang Nan PROBES_T16_LDMSTM, 78fca08f32SWang Nan PROBES_T16_BRANCH_COND, 79fca08f32SWang Nan PROBES_T16_BRANCH, 80fca08f32SWang Nan NUM_PROBES_T16_ACTIONS 81fca08f32SWang Nan }; 82fca08f32SWang Nan 83fca08f32SWang Nan extern const union decode_item probes_decode_thumb32_table[]; 84fca08f32SWang Nan extern const union decode_item probes_decode_thumb16_table[]; 85fca08f32SWang Nan 86fca08f32SWang Nan enum probes_insn __kprobes 87fca08f32SWang Nan thumb16_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, 8883803d97SWang Nan bool emulate, const union decode_action *actions, 8983803d97SWang Nan const struct decode_checker *checkers[]); 90fca08f32SWang Nan enum probes_insn __kprobes 91fca08f32SWang Nan thumb32_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, 9283803d97SWang Nan bool emulate, const union decode_action *actions, 9383803d97SWang Nan const struct decode_checker *checkers[]); 94fca08f32SWang Nan 95fca08f32SWang Nan #endif 96