1 /* 2 * arch/arm/plat-orion/time.c 3 * 4 * Marvell Orion SoC timer handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 * 10 * Timer 0 is used as free-running clocksource, while timer 1 is 11 * used as clock_event_device. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/sched.h> 16 #include <linux/cnt32_to_63.h> 17 #include <linux/timer.h> 18 #include <linux/clockchips.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <asm/mach/time.h> 22 #include <mach/bridge-regs.h> 23 #include <mach/hardware.h> 24 25 /* 26 * Number of timer ticks per jiffy. 27 */ 28 static u32 ticks_per_jiffy; 29 30 31 /* 32 * Timer block registers. 33 */ 34 #define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000) 35 #define TIMER0_EN 0x0001 36 #define TIMER0_RELOAD_EN 0x0002 37 #define TIMER1_EN 0x0004 38 #define TIMER1_RELOAD_EN 0x0008 39 #define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010) 40 #define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014) 41 #define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018) 42 #define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c) 43 44 45 /* 46 * Orion's sched_clock implementation. It has a resolution of 47 * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days. 48 * 49 * Because the hardware timer period is quite short (21 secs if 50 * 200MHz TCLK) and because cnt32_to_63() needs to be called at 51 * least once per half period to work properly, a kernel timer is 52 * set up to ensure this requirement is always met. 53 */ 54 #define TCLK2NS_SCALE_FACTOR 8 55 56 static unsigned long tclk2ns_scale; 57 58 unsigned long long sched_clock(void) 59 { 60 unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); 61 return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; 62 } 63 64 static struct timer_list cnt32_to_63_keepwarm_timer; 65 66 static void cnt32_to_63_keepwarm(unsigned long data) 67 { 68 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); 69 (void) sched_clock(); 70 } 71 72 static void __init setup_sched_clock(unsigned long tclk) 73 { 74 unsigned long long v; 75 unsigned long data; 76 77 v = NSEC_PER_SEC; 78 v <<= TCLK2NS_SCALE_FACTOR; 79 v += tclk/2; 80 do_div(v, tclk); 81 /* 82 * We want an even value to automatically clear the top bit 83 * returned by cnt32_to_63() without an additional run time 84 * instruction. So if the LSB is 1 then round it up. 85 */ 86 if (v & 1) 87 v++; 88 tclk2ns_scale = v; 89 90 data = (0xffffffffUL / tclk / 2 - 2) * HZ; 91 setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); 92 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); 93 } 94 95 /* 96 * Clocksource handling. 97 */ 98 static cycle_t orion_clksrc_read(struct clocksource *cs) 99 { 100 return 0xffffffff - readl(TIMER0_VAL); 101 } 102 103 static struct clocksource orion_clksrc = { 104 .name = "orion_clocksource", 105 .rating = 300, 106 .read = orion_clksrc_read, 107 .mask = CLOCKSOURCE_MASK(32), 108 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 109 }; 110 111 112 113 /* 114 * Clockevent handling. 115 */ 116 static int 117 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) 118 { 119 unsigned long flags; 120 u32 u; 121 122 if (delta == 0) 123 return -ETIME; 124 125 local_irq_save(flags); 126 127 /* 128 * Clear and enable clockevent timer interrupt. 129 */ 130 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 131 132 u = readl(BRIDGE_MASK); 133 u |= BRIDGE_INT_TIMER1; 134 writel(u, BRIDGE_MASK); 135 136 /* 137 * Setup new clockevent timer value. 138 */ 139 writel(delta, TIMER1_VAL); 140 141 /* 142 * Enable the timer. 143 */ 144 u = readl(TIMER_CTRL); 145 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; 146 writel(u, TIMER_CTRL); 147 148 local_irq_restore(flags); 149 150 return 0; 151 } 152 153 static void 154 orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) 155 { 156 unsigned long flags; 157 u32 u; 158 159 local_irq_save(flags); 160 if (mode == CLOCK_EVT_MODE_PERIODIC) { 161 /* 162 * Setup timer to fire at 1/HZ intervals. 163 */ 164 writel(ticks_per_jiffy - 1, TIMER1_RELOAD); 165 writel(ticks_per_jiffy - 1, TIMER1_VAL); 166 167 /* 168 * Enable timer interrupt. 169 */ 170 u = readl(BRIDGE_MASK); 171 writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK); 172 173 /* 174 * Enable timer. 175 */ 176 u = readl(TIMER_CTRL); 177 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL); 178 } else { 179 /* 180 * Disable timer. 181 */ 182 u = readl(TIMER_CTRL); 183 writel(u & ~TIMER1_EN, TIMER_CTRL); 184 185 /* 186 * Disable timer interrupt. 187 */ 188 u = readl(BRIDGE_MASK); 189 writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK); 190 191 /* 192 * ACK pending timer interrupt. 193 */ 194 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 195 196 } 197 local_irq_restore(flags); 198 } 199 200 static struct clock_event_device orion_clkevt = { 201 .name = "orion_tick", 202 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 203 .shift = 32, 204 .rating = 300, 205 .set_next_event = orion_clkevt_next_event, 206 .set_mode = orion_clkevt_mode, 207 }; 208 209 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) 210 { 211 /* 212 * ACK timer interrupt and call event handler. 213 */ 214 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); 215 orion_clkevt.event_handler(&orion_clkevt); 216 217 return IRQ_HANDLED; 218 } 219 220 static struct irqaction orion_timer_irq = { 221 .name = "orion_tick", 222 .flags = IRQF_DISABLED | IRQF_TIMER, 223 .handler = orion_timer_interrupt 224 }; 225 226 void __init orion_time_init(unsigned int irq, unsigned int tclk) 227 { 228 u32 u; 229 230 ticks_per_jiffy = (tclk + HZ/2) / HZ; 231 232 /* 233 * Set scale and timer for sched_clock 234 */ 235 setup_sched_clock(tclk); 236 237 /* 238 * Setup free-running clocksource timer (interrupts 239 * disabled.) 240 */ 241 writel(0xffffffff, TIMER0_VAL); 242 writel(0xffffffff, TIMER0_RELOAD); 243 u = readl(BRIDGE_MASK); 244 writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); 245 u = readl(TIMER_CTRL); 246 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); 247 clocksource_register_hz(&orion_clksrc, tclk); 248 249 /* 250 * Setup clockevent timer (interrupt-driven.) 251 */ 252 setup_irq(irq, &orion_timer_irq); 253 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); 254 orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); 255 orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); 256 orion_clkevt.cpumask = cpumask_of(0); 257 clockevents_register_device(&orion_clkevt); 258 } 259