1 /* 2 * arch/arm/plat-orion/irq.c 3 * 4 * Marvell Orion SoC IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <asm/exception.h> 19 #include <plat/irq.h> 20 #include <plat/orion-gpio.h> 21 #include <mach/bridge-regs.h> 22 23 #ifdef CONFIG_MULTI_IRQ_HANDLER 24 /* 25 * Compiling with both non-DT and DT support enabled, will 26 * break asm irq handler used by non-DT boards. Therefore, 27 * we provide a C-style irq handler even for non-DT boards, 28 * if MULTI_IRQ_HANDLER is set. 29 * 30 * Notes: 31 * - this is prepared for Kirkwood and Dove only, update 32 * accordingly if you add Orion5x or MV78x00. 33 * - Orion5x uses different macro names and has only one 34 * set of CAUSE/MASK registers. 35 * - MV78x00 uses the same macro names but has a third 36 * set of CAUSE/MASK registers. 37 * 38 */ 39 40 static void __iomem *orion_irq_base = IRQ_VIRT_BASE; 41 42 asmlinkage void 43 __exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs) 44 { 45 u32 stat; 46 47 stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF); 48 stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF); 49 if (stat) { 50 unsigned int hwirq = __fls(stat); 51 handle_IRQ(hwirq, regs); 52 return; 53 } 54 stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF); 55 stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF); 56 if (stat) { 57 unsigned int hwirq = 32 + __fls(stat); 58 handle_IRQ(hwirq, regs); 59 return; 60 } 61 } 62 #endif 63 64 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) 65 { 66 struct irq_chip_generic *gc; 67 struct irq_chip_type *ct; 68 69 /* 70 * Mask all interrupts initially. 71 */ 72 writel(0, maskaddr); 73 74 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, 75 handle_level_irq); 76 ct = gc->chip_types; 77 ct->chip.irq_mask = irq_gc_mask_clr_bit; 78 ct->chip.irq_unmask = irq_gc_mask_set_bit; 79 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, 80 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 81 82 #ifdef CONFIG_MULTI_IRQ_HANDLER 83 set_handle_irq(orion_legacy_handle_irq); 84 #endif 85 } 86 87 #ifdef CONFIG_OF 88 static int __init orion_add_irq_domain(struct device_node *np, 89 struct device_node *interrupt_parent) 90 { 91 int i = 0; 92 void __iomem *base; 93 94 do { 95 base = of_iomap(np, i); 96 if (base) { 97 orion_irq_init(i * 32, base + 0x04); 98 i++; 99 } 100 } while (base); 101 102 irq_domain_add_legacy(np, i * 32, 0, 0, 103 &irq_domain_simple_ops, NULL); 104 return 0; 105 } 106 107 static const struct of_device_id orion_irq_match[] = { 108 { .compatible = "marvell,orion-intc", 109 .data = orion_add_irq_domain, }, 110 {}, 111 }; 112 113 void __init orion_dt_init_irq(void) 114 { 115 of_irq_init(orion_irq_match); 116 } 117 #endif 118