1 /* 2 * arch/arm/plat-orion/irq.c 3 * 4 * Marvell Orion SoC IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <asm/exception.h> 19 #include <plat/irq.h> 20 #include <plat/orion-gpio.h> 21 #include <mach/bridge-regs.h> 22 23 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) 24 { 25 struct irq_chip_generic *gc; 26 struct irq_chip_type *ct; 27 28 /* 29 * Mask all interrupts initially. 30 */ 31 writel(0, maskaddr); 32 33 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, 34 handle_level_irq); 35 ct = gc->chip_types; 36 ct->chip.irq_mask = irq_gc_mask_clr_bit; 37 ct->chip.irq_unmask = irq_gc_mask_set_bit; 38 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, 39 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 40 } 41 42 #ifdef CONFIG_OF 43 static int __init orion_add_irq_domain(struct device_node *np, 44 struct device_node *interrupt_parent) 45 { 46 int i = 0; 47 void __iomem *base; 48 49 do { 50 base = of_iomap(np, i); 51 if (base) { 52 orion_irq_init(i * 32, base + 0x04); 53 i++; 54 } 55 } while (base); 56 57 irq_domain_add_legacy(np, i * 32, 0, 0, 58 &irq_domain_simple_ops, NULL); 59 return 0; 60 } 61 62 static const struct of_device_id orion_irq_match[] = { 63 { .compatible = "marvell,orion-intc", 64 .data = orion_add_irq_domain, }, 65 {}, 66 }; 67 68 void __init orion_dt_init_irq(void) 69 { 70 of_irq_init(orion_irq_match); 71 } 72 #endif 73