101eb5698SLennert Buytenhek /* 201eb5698SLennert Buytenhek * arch/arm/plat-orion/irq.c 301eb5698SLennert Buytenhek * 401eb5698SLennert Buytenhek * Marvell Orion SoC IRQ handling. 501eb5698SLennert Buytenhek * 601eb5698SLennert Buytenhek * This file is licensed under the terms of the GNU General Public 701eb5698SLennert Buytenhek * License version 2. This program is licensed "as is" without any 801eb5698SLennert Buytenhek * warranty of any kind, whether express or implied. 901eb5698SLennert Buytenhek */ 1001eb5698SLennert Buytenhek 1101eb5698SLennert Buytenhek #include <linux/kernel.h> 1201eb5698SLennert Buytenhek #include <linux/init.h> 1301eb5698SLennert Buytenhek #include <linux/irq.h> 1401eb5698SLennert Buytenhek #include <linux/io.h> 156f088f1dSLennert Buytenhek #include <plat/irq.h> 1601eb5698SLennert Buytenhek 1701eb5698SLennert Buytenhek void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) 1801eb5698SLennert Buytenhek { 19e59347a1SThomas Gleixner struct irq_chip_generic *gc; 20e59347a1SThomas Gleixner struct irq_chip_type *ct; 2101eb5698SLennert Buytenhek 2201eb5698SLennert Buytenhek /* 2301eb5698SLennert Buytenhek * Mask all interrupts initially. 2401eb5698SLennert Buytenhek */ 2501eb5698SLennert Buytenhek writel(0, maskaddr); 2601eb5698SLennert Buytenhek 27e59347a1SThomas Gleixner gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, 28f38c02f3SThomas Gleixner handle_level_irq); 29e59347a1SThomas Gleixner ct = gc->chip_types; 30e59347a1SThomas Gleixner ct->chip.irq_mask = irq_gc_mask_clr_bit; 31e59347a1SThomas Gleixner ct->chip.irq_unmask = irq_gc_mask_set_bit; 32e59347a1SThomas Gleixner irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, 33e59347a1SThomas Gleixner IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 3401eb5698SLennert Buytenhek } 35