1 /* 2 * arch/arm/plat-orion/gpio.c 3 * 4 * Marvell Orion SoC GPIO handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #define DEBUG 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/spinlock.h> 19 #include <linux/bitops.h> 20 #include <linux/io.h> 21 #include <linux/gpio.h> 22 #include <linux/leds.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_address.h> 26 #include <plat/orion-gpio.h> 27 28 /* 29 * GPIO unit register offsets. 30 */ 31 #define GPIO_OUT_OFF 0x0000 32 #define GPIO_IO_CONF_OFF 0x0004 33 #define GPIO_BLINK_EN_OFF 0x0008 34 #define GPIO_IN_POL_OFF 0x000c 35 #define GPIO_DATA_IN_OFF 0x0010 36 #define GPIO_EDGE_CAUSE_OFF 0x0014 37 #define GPIO_EDGE_MASK_OFF 0x0018 38 #define GPIO_LEVEL_MASK_OFF 0x001c 39 40 struct orion_gpio_chip { 41 struct gpio_chip chip; 42 spinlock_t lock; 43 void __iomem *base; 44 unsigned long valid_input; 45 unsigned long valid_output; 46 int mask_offset; 47 int secondary_irq_base; 48 struct irq_domain *domain; 49 }; 50 51 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) 52 { 53 return ochip->base + GPIO_OUT_OFF; 54 } 55 56 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) 57 { 58 return ochip->base + GPIO_IO_CONF_OFF; 59 } 60 61 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) 62 { 63 return ochip->base + GPIO_BLINK_EN_OFF; 64 } 65 66 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) 67 { 68 return ochip->base + GPIO_IN_POL_OFF; 69 } 70 71 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) 72 { 73 return ochip->base + GPIO_DATA_IN_OFF; 74 } 75 76 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) 77 { 78 return ochip->base + GPIO_EDGE_CAUSE_OFF; 79 } 80 81 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) 82 { 83 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; 84 } 85 86 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) 87 { 88 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 89 } 90 91 92 static struct orion_gpio_chip orion_gpio_chips[2]; 93 static int orion_gpio_chip_count; 94 95 static inline void 96 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) 97 { 98 u32 u; 99 100 u = readl(GPIO_IO_CONF(ochip)); 101 if (input) 102 u |= 1 << pin; 103 else 104 u &= ~(1 << pin); 105 writel(u, GPIO_IO_CONF(ochip)); 106 } 107 108 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) 109 { 110 u32 u; 111 112 u = readl(GPIO_OUT(ochip)); 113 if (high) 114 u |= 1 << pin; 115 else 116 u &= ~(1 << pin); 117 writel(u, GPIO_OUT(ochip)); 118 } 119 120 static inline void 121 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) 122 { 123 u32 u; 124 125 u = readl(GPIO_BLINK_EN(ochip)); 126 if (blink) 127 u |= 1 << pin; 128 else 129 u &= ~(1 << pin); 130 writel(u, GPIO_BLINK_EN(ochip)); 131 } 132 133 static inline int 134 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) 135 { 136 if (pin >= ochip->chip.ngpio) 137 goto err_out; 138 139 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) 140 goto err_out; 141 142 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) 143 goto err_out; 144 145 return 1; 146 147 err_out: 148 pr_debug("%s: invalid GPIO %d\n", __func__, pin); 149 return false; 150 } 151 152 /* 153 * GPIO primitives. 154 */ 155 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) 156 { 157 struct orion_gpio_chip *ochip = 158 container_of(chip, struct orion_gpio_chip, chip); 159 160 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || 161 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 162 return 0; 163 164 return -EINVAL; 165 } 166 167 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 168 { 169 struct orion_gpio_chip *ochip = 170 container_of(chip, struct orion_gpio_chip, chip); 171 unsigned long flags; 172 173 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) 174 return -EINVAL; 175 176 spin_lock_irqsave(&ochip->lock, flags); 177 __set_direction(ochip, pin, 1); 178 spin_unlock_irqrestore(&ochip->lock, flags); 179 180 return 0; 181 } 182 183 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) 184 { 185 struct orion_gpio_chip *ochip = 186 container_of(chip, struct orion_gpio_chip, chip); 187 int val; 188 189 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { 190 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); 191 } else { 192 val = readl(GPIO_OUT(ochip)); 193 } 194 195 return (val >> pin) & 1; 196 } 197 198 static int 199 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) 200 { 201 struct orion_gpio_chip *ochip = 202 container_of(chip, struct orion_gpio_chip, chip); 203 unsigned long flags; 204 205 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 206 return -EINVAL; 207 208 spin_lock_irqsave(&ochip->lock, flags); 209 __set_blinking(ochip, pin, 0); 210 __set_level(ochip, pin, value); 211 __set_direction(ochip, pin, 0); 212 spin_unlock_irqrestore(&ochip->lock, flags); 213 214 return 0; 215 } 216 217 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 218 { 219 struct orion_gpio_chip *ochip = 220 container_of(chip, struct orion_gpio_chip, chip); 221 unsigned long flags; 222 223 spin_lock_irqsave(&ochip->lock, flags); 224 __set_level(ochip, pin, value); 225 spin_unlock_irqrestore(&ochip->lock, flags); 226 } 227 228 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 229 { 230 struct orion_gpio_chip *ochip = 231 container_of(chip, struct orion_gpio_chip, chip); 232 233 return irq_create_mapping(ochip->domain, 234 ochip->secondary_irq_base + pin); 235 } 236 237 /* 238 * Orion-specific GPIO API extensions. 239 */ 240 static struct orion_gpio_chip *orion_gpio_chip_find(int pin) 241 { 242 int i; 243 244 for (i = 0; i < orion_gpio_chip_count; i++) { 245 struct orion_gpio_chip *ochip = orion_gpio_chips + i; 246 struct gpio_chip *chip = &ochip->chip; 247 248 if (pin >= chip->base && pin < chip->base + chip->ngpio) 249 return ochip; 250 } 251 252 return NULL; 253 } 254 255 void __init orion_gpio_set_unused(unsigned pin) 256 { 257 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 258 259 if (ochip == NULL) 260 return; 261 262 pin -= ochip->chip.base; 263 264 /* Configure as output, drive low. */ 265 __set_level(ochip, pin, 0); 266 __set_direction(ochip, pin, 0); 267 } 268 269 void __init orion_gpio_set_valid(unsigned pin, int mode) 270 { 271 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 272 273 if (ochip == NULL) 274 return; 275 276 pin -= ochip->chip.base; 277 278 if (mode == 1) 279 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; 280 281 if (mode & GPIO_INPUT_OK) 282 __set_bit(pin, &ochip->valid_input); 283 else 284 __clear_bit(pin, &ochip->valid_input); 285 286 if (mode & GPIO_OUTPUT_OK) 287 __set_bit(pin, &ochip->valid_output); 288 else 289 __clear_bit(pin, &ochip->valid_output); 290 } 291 292 void orion_gpio_set_blink(unsigned pin, int blink) 293 { 294 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 295 unsigned long flags; 296 297 if (ochip == NULL) 298 return; 299 300 spin_lock_irqsave(&ochip->lock, flags); 301 __set_level(ochip, pin & 31, 0); 302 __set_blinking(ochip, pin & 31, blink); 303 spin_unlock_irqrestore(&ochip->lock, flags); 304 } 305 EXPORT_SYMBOL(orion_gpio_set_blink); 306 307 #define ORION_BLINK_HALF_PERIOD 100 /* ms */ 308 309 int orion_gpio_led_blink_set(unsigned gpio, int state, 310 unsigned long *delay_on, unsigned long *delay_off) 311 { 312 313 if (delay_on && delay_off && !*delay_on && !*delay_off) 314 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; 315 316 switch (state) { 317 case GPIO_LED_NO_BLINK_LOW: 318 case GPIO_LED_NO_BLINK_HIGH: 319 orion_gpio_set_blink(gpio, 0); 320 gpio_set_value(gpio, state); 321 break; 322 case GPIO_LED_BLINK: 323 orion_gpio_set_blink(gpio, 1); 324 } 325 return 0; 326 } 327 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); 328 329 330 /***************************************************************************** 331 * Orion GPIO IRQ 332 * 333 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 334 * value of the line or the opposite value. 335 * 336 * Level IRQ handlers: DATA_IN is used directly as cause register. 337 * Interrupt are masked by LEVEL_MASK registers. 338 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 339 * Interrupt are masked by EDGE_MASK registers. 340 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 341 * the polarity to catch the next line transaction. 342 * This is a race condition that might not perfectly 343 * work on some use cases. 344 * 345 * Every eight GPIO lines are grouped (OR'ed) before going up to main 346 * cause register. 347 * 348 * EDGE cause mask 349 * data-in /--------| |-----| |----\ 350 * -----| |----- ---- to main cause reg 351 * X \----------------| |----/ 352 * polarity LEVEL mask 353 * 354 ****************************************************************************/ 355 356 static int gpio_irq_set_type(struct irq_data *d, u32 type) 357 { 358 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 359 struct irq_chip_type *ct = irq_data_get_chip_type(d); 360 struct orion_gpio_chip *ochip = gc->private; 361 int pin; 362 u32 u; 363 364 pin = d->hwirq - ochip->secondary_irq_base; 365 366 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); 367 if (!u) { 368 return -EINVAL; 369 } 370 371 type &= IRQ_TYPE_SENSE_MASK; 372 if (type == IRQ_TYPE_NONE) 373 return -EINVAL; 374 375 /* Check if we need to change chip and handler */ 376 if (!(ct->type & type)) 377 if (irq_setup_alt_chip(d, type)) 378 return -EINVAL; 379 380 /* 381 * Configure interrupt polarity. 382 */ 383 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { 384 u = readl(GPIO_IN_POL(ochip)); 385 u &= ~(1 << pin); 386 writel(u, GPIO_IN_POL(ochip)); 387 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { 388 u = readl(GPIO_IN_POL(ochip)); 389 u |= 1 << pin; 390 writel(u, GPIO_IN_POL(ochip)); 391 } else if (type == IRQ_TYPE_EDGE_BOTH) { 392 u32 v; 393 394 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); 395 396 /* 397 * set initial polarity based on current input level 398 */ 399 u = readl(GPIO_IN_POL(ochip)); 400 if (v & (1 << pin)) 401 u |= 1 << pin; /* falling */ 402 else 403 u &= ~(1 << pin); /* rising */ 404 writel(u, GPIO_IN_POL(ochip)); 405 } 406 return 0; 407 } 408 409 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 410 { 411 struct orion_gpio_chip *ochip = irq_get_handler_data(irq); 412 u32 cause, type; 413 int i; 414 415 if (ochip == NULL) 416 return; 417 418 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); 419 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); 420 421 for (i = 0; i < ochip->chip.ngpio; i++) { 422 int irq; 423 424 irq = ochip->secondary_irq_base + i; 425 426 if (!(cause & (1 << i))) 427 continue; 428 429 type = irq_get_trigger_type(irq); 430 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 431 /* Swap polarity (race with GPIO line) */ 432 u32 polarity; 433 434 polarity = readl(GPIO_IN_POL(ochip)); 435 polarity ^= 1 << i; 436 writel(polarity, GPIO_IN_POL(ochip)); 437 } 438 generic_handle_irq(irq); 439 } 440 } 441 442 #ifdef CONFIG_DEBUG_FS 443 #include <linux/seq_file.h> 444 445 static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 446 { 447 struct orion_gpio_chip *ochip = 448 container_of(chip, struct orion_gpio_chip, chip); 449 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 450 int i; 451 452 out = readl_relaxed(GPIO_OUT(ochip)); 453 io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); 454 blink = readl_relaxed(GPIO_BLINK_EN(ochip)); 455 in_pol = readl_relaxed(GPIO_IN_POL(ochip)); 456 data_in = readl_relaxed(GPIO_DATA_IN(ochip)); 457 cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); 458 edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); 459 lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); 460 461 for (i = 0; i < chip->ngpio; i++) { 462 const char *label; 463 u32 msk; 464 bool is_out; 465 466 label = gpiochip_is_requested(chip, i); 467 if (!label) 468 continue; 469 470 msk = 1 << i; 471 is_out = !(io_conf & msk); 472 473 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 474 475 if (is_out) { 476 seq_printf(s, " out %s %s\n", 477 out & msk ? "hi" : "lo", 478 blink & msk ? "(blink )" : ""); 479 continue; 480 } 481 482 seq_printf(s, " in %s (act %s) - IRQ", 483 (data_in ^ in_pol) & msk ? "hi" : "lo", 484 in_pol & msk ? "lo" : "hi"); 485 if (!((edg_msk | lvl_msk) & msk)) { 486 seq_printf(s, " disabled\n"); 487 continue; 488 } 489 if (edg_msk & msk) 490 seq_printf(s, " edge "); 491 if (lvl_msk & msk) 492 seq_printf(s, " level"); 493 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 494 } 495 } 496 #else 497 #define orion_gpio_dbg_show NULL 498 #endif 499 500 void __init orion_gpio_init(struct device_node *np, 501 int gpio_base, int ngpio, 502 void __iomem *base, int mask_offset, 503 int secondary_irq_base, 504 int irqs[4]) 505 { 506 struct orion_gpio_chip *ochip; 507 struct irq_chip_generic *gc; 508 struct irq_chip_type *ct; 509 char gc_label[16]; 510 int i; 511 512 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) 513 return; 514 515 snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", 516 orion_gpio_chip_count); 517 518 ochip = orion_gpio_chips + orion_gpio_chip_count; 519 ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); 520 ochip->chip.request = orion_gpio_request; 521 ochip->chip.direction_input = orion_gpio_direction_input; 522 ochip->chip.get = orion_gpio_get; 523 ochip->chip.direction_output = orion_gpio_direction_output; 524 ochip->chip.set = orion_gpio_set; 525 ochip->chip.to_irq = orion_gpio_to_irq; 526 ochip->chip.base = gpio_base; 527 ochip->chip.ngpio = ngpio; 528 ochip->chip.can_sleep = 0; 529 #ifdef CONFIG_OF 530 ochip->chip.of_node = np; 531 #endif 532 ochip->chip.dbg_show = orion_gpio_dbg_show; 533 534 spin_lock_init(&ochip->lock); 535 ochip->base = (void __iomem *)base; 536 ochip->valid_input = 0; 537 ochip->valid_output = 0; 538 ochip->mask_offset = mask_offset; 539 ochip->secondary_irq_base = secondary_irq_base; 540 541 gpiochip_add(&ochip->chip); 542 543 /* 544 * Mask and clear GPIO interrupts. 545 */ 546 writel(0, GPIO_EDGE_CAUSE(ochip)); 547 writel(0, GPIO_EDGE_MASK(ochip)); 548 writel(0, GPIO_LEVEL_MASK(ochip)); 549 550 /* Setup the interrupt handlers. Each chip can have up to 4 551 * interrupt handlers, with each handler dealing with 8 GPIO 552 * pins. */ 553 554 for (i = 0; i < 4; i++) { 555 if (irqs[i]) { 556 irq_set_handler_data(irqs[i], ochip); 557 irq_set_chained_handler(irqs[i], gpio_irq_handler); 558 } 559 } 560 561 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, 562 secondary_irq_base, 563 ochip->base, handle_level_irq); 564 gc->private = ochip; 565 ct = gc->chip_types; 566 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 567 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 568 ct->chip.irq_mask = irq_gc_mask_clr_bit; 569 ct->chip.irq_unmask = irq_gc_mask_set_bit; 570 ct->chip.irq_set_type = gpio_irq_set_type; 571 ct->chip.name = ochip->chip.label; 572 573 ct++; 574 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; 575 ct->regs.ack = GPIO_EDGE_CAUSE_OFF; 576 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 577 ct->chip.irq_ack = irq_gc_ack_clr_bit; 578 ct->chip.irq_mask = irq_gc_mask_clr_bit; 579 ct->chip.irq_unmask = irq_gc_mask_set_bit; 580 ct->chip.irq_set_type = gpio_irq_set_type; 581 ct->handler = handle_edge_irq; 582 ct->chip.name = ochip->chip.label; 583 584 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, 585 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 586 587 /* Setup irq domain on top of the generic chip. */ 588 ochip->domain = irq_domain_add_legacy(np, 589 ochip->chip.ngpio, 590 ochip->secondary_irq_base, 591 ochip->secondary_irq_base, 592 &irq_domain_simple_ops, 593 ochip); 594 if (!ochip->domain) 595 panic("%s: couldn't allocate irq domain (DT).\n", 596 ochip->chip.label); 597 598 orion_gpio_chip_count++; 599 } 600 601 #ifdef CONFIG_OF 602 static void __init orion_gpio_of_init_one(struct device_node *np, 603 int irq_gpio_base) 604 { 605 int ngpio, gpio_base, mask_offset; 606 void __iomem *base; 607 int ret, i; 608 int irqs[4]; 609 int secondary_irq_base; 610 611 ret = of_property_read_u32(np, "ngpio", &ngpio); 612 if (ret) 613 goto out; 614 ret = of_property_read_u32(np, "mask-offset", &mask_offset); 615 if (ret == -EINVAL) 616 mask_offset = 0; 617 else 618 goto out; 619 base = of_iomap(np, 0); 620 if (!base) 621 goto out; 622 623 secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count); 624 gpio_base = 32 * orion_gpio_chip_count; 625 626 /* Get the interrupt numbers. Each chip can have up to 4 627 * interrupt handlers, with each handler dealing with 8 GPIO 628 * pins. */ 629 630 for (i = 0; i < 4; i++) 631 irqs[i] = irq_of_parse_and_map(np, i); 632 633 orion_gpio_init(np, gpio_base, ngpio, base, mask_offset, 634 secondary_irq_base, irqs); 635 return; 636 out: 637 pr_err("%s: %s: missing mandatory property\n", __func__, np->name); 638 } 639 640 void __init orion_gpio_of_init(int irq_gpio_base) 641 { 642 struct device_node *np; 643 644 for_each_compatible_node(np, NULL, "marvell,orion-gpio") 645 orion_gpio_of_init_one(np, irq_gpio_base); 646 } 647 #endif 648