1 /* 2 * Just-In-Time compiler for BPF filters on 32bit ARM 3 * 4 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef PFILTER_OPCODES_ARM_H 12 #define PFILTER_OPCODES_ARM_H 13 14 /* ARM 32bit Registers */ 15 #define ARM_R0 0 16 #define ARM_R1 1 17 #define ARM_R2 2 18 #define ARM_R3 3 19 #define ARM_R4 4 20 #define ARM_R5 5 21 #define ARM_R6 6 22 #define ARM_R7 7 23 #define ARM_R8 8 24 #define ARM_R9 9 25 #define ARM_R10 10 26 #define ARM_FP 11 /* Frame Pointer */ 27 #define ARM_IP 12 /* Intra-procedure scratch register */ 28 #define ARM_SP 13 /* Stack pointer: as load/store base reg */ 29 #define ARM_LR 14 /* Link Register */ 30 #define ARM_PC 15 /* Program counter */ 31 32 #define ARM_COND_EQ 0x0 /* == */ 33 #define ARM_COND_NE 0x1 /* != */ 34 #define ARM_COND_CS 0x2 /* unsigned >= */ 35 #define ARM_COND_HS ARM_COND_CS 36 #define ARM_COND_CC 0x3 /* unsigned < */ 37 #define ARM_COND_LO ARM_COND_CC 38 #define ARM_COND_MI 0x4 /* < 0 */ 39 #define ARM_COND_PL 0x5 /* >= 0 */ 40 #define ARM_COND_VS 0x6 /* Signed Overflow */ 41 #define ARM_COND_VC 0x7 /* No Signed Overflow */ 42 #define ARM_COND_HI 0x8 /* unsigned > */ 43 #define ARM_COND_LS 0x9 /* unsigned <= */ 44 #define ARM_COND_GE 0xa /* Signed >= */ 45 #define ARM_COND_LT 0xb /* Signed < */ 46 #define ARM_COND_GT 0xc /* Signed > */ 47 #define ARM_COND_LE 0xd /* Signed <= */ 48 #define ARM_COND_AL 0xe /* None */ 49 50 /* register shift types */ 51 #define SRTYPE_LSL 0 52 #define SRTYPE_LSR 1 53 #define SRTYPE_ASR 2 54 #define SRTYPE_ROR 3 55 #define SRTYPE_ASL (SRTYPE_LSL) 56 57 #define ARM_INST_ADD_R 0x00800000 58 #define ARM_INST_ADDS_R 0x00900000 59 #define ARM_INST_ADC_R 0x00a00000 60 #define ARM_INST_ADC_I 0x02a00000 61 #define ARM_INST_ADD_I 0x02800000 62 #define ARM_INST_ADDS_I 0x02900000 63 64 #define ARM_INST_AND_R 0x00000000 65 #define ARM_INST_AND_I 0x02000000 66 67 #define ARM_INST_BIC_R 0x01c00000 68 #define ARM_INST_BIC_I 0x03c00000 69 70 #define ARM_INST_B 0x0a000000 71 #define ARM_INST_BX 0x012FFF10 72 #define ARM_INST_BLX_R 0x012fff30 73 74 #define ARM_INST_CMP_R 0x01500000 75 #define ARM_INST_CMP_I 0x03500000 76 77 #define ARM_INST_EOR_R 0x00200000 78 #define ARM_INST_EOR_I 0x02200000 79 80 #define ARM_INST_LDRB_I 0x05d00000 81 #define ARM_INST_LDRB_R 0x07d00000 82 #define ARM_INST_LDRH_I 0x01d000b0 83 #define ARM_INST_LDRH_R 0x019000b0 84 #define ARM_INST_LDR_I 0x05900000 85 #define ARM_INST_LDR_R 0x07900000 86 87 #define ARM_INST_LDM 0x08900000 88 #define ARM_INST_LDM_IA 0x08b00000 89 90 #define ARM_INST_LSL_I 0x01a00000 91 #define ARM_INST_LSL_R 0x01a00010 92 93 #define ARM_INST_LSR_I 0x01a00020 94 #define ARM_INST_LSR_R 0x01a00030 95 96 #define ARM_INST_MOV_R 0x01a00000 97 #define ARM_INST_MOVS_R 0x01b00000 98 #define ARM_INST_MOV_I 0x03a00000 99 #define ARM_INST_MOVW 0x03000000 100 #define ARM_INST_MOVT 0x03400000 101 102 #define ARM_INST_MUL 0x00000090 103 104 #define ARM_INST_POP 0x08bd0000 105 #define ARM_INST_PUSH 0x092d0000 106 107 #define ARM_INST_ORR_R 0x01800000 108 #define ARM_INST_ORRS_R 0x01900000 109 #define ARM_INST_ORR_I 0x03800000 110 111 #define ARM_INST_REV 0x06bf0f30 112 #define ARM_INST_REV16 0x06bf0fb0 113 114 #define ARM_INST_RSB_I 0x02600000 115 #define ARM_INST_RSBS_I 0x02700000 116 #define ARM_INST_RSC_I 0x02e00000 117 118 #define ARM_INST_SUB_R 0x00400000 119 #define ARM_INST_SUBS_R 0x00500000 120 #define ARM_INST_RSB_R 0x00600000 121 #define ARM_INST_SUB_I 0x02400000 122 #define ARM_INST_SUBS_I 0x02500000 123 #define ARM_INST_SBC_I 0x02c00000 124 #define ARM_INST_SBC_R 0x00c00000 125 #define ARM_INST_SBCS_R 0x00d00000 126 127 #define ARM_INST_STR_I 0x05800000 128 #define ARM_INST_STRB_I 0x05c00000 129 #define ARM_INST_STRH_I 0x01c000b0 130 131 #define ARM_INST_TST_R 0x01100000 132 #define ARM_INST_TST_I 0x03100000 133 134 #define ARM_INST_UDIV 0x0730f010 135 136 #define ARM_INST_UMULL 0x00800090 137 138 #define ARM_INST_MLS 0x00600090 139 140 #define ARM_INST_UXTH 0x06ff0070 141 142 /* 143 * Use a suitable undefined instruction to use for ARM/Thumb2 faulting. 144 * We need to be careful not to conflict with those used by other modules 145 * (BUG, kprobes, etc) and the register_undef_hook() system. 146 * 147 * The ARM architecture reference manual guarantees that the following 148 * instruction space will produce an undefined instruction exception on 149 * all CPUs: 150 * 151 * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx ARMv7-AR, section A5.4 152 * Thumb: 1101 1110 xxxx xxxx ARMv7-M, section A5.2.6 153 */ 154 #define ARM_INST_UDF 0xe7fddef1 155 156 /* register */ 157 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) 158 /* immediate */ 159 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) 160 /* register with register-shift */ 161 #define _AL3_SR(inst) (inst | (1 << 4)) 162 163 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) 164 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) 165 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) 166 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) 167 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) 168 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) 169 170 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) 171 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) 172 173 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) 174 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) 175 176 #define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff)) 177 #define ARM_BX(rm) (ARM_INST_BX | (rm)) 178 #define ARM_BLX_R(rm) (ARM_INST_BLX_R | (rm)) 179 180 #define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm) 181 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) 182 183 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) 184 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) 185 186 #define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \ 187 | ((off) & 0xfff)) 188 #define ARM_LDR_R(rt, rn, rm) (ARM_INST_LDR_R | (rt) << 12 | (rn) << 16 \ 189 | (rm)) 190 #define ARM_LDRB_I(rt, rn, off) (ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \ 191 | (off)) 192 #define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \ 193 | (rm)) 194 #define ARM_LDRH_I(rt, rn, off) (ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \ 195 | (((off) & 0xf0) << 4) | ((off) & 0xf)) 196 #define ARM_LDRH_R(rt, rn, rm) (ARM_INST_LDRH_R | (rt) << 12 | (rn) << 16 \ 197 | (rm)) 198 199 #define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs)) 200 #define ARM_LDM_IA(rn, regs) (ARM_INST_LDM_IA | (rn) << 16 | (regs)) 201 202 #define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8) 203 #define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7) 204 205 #define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8) 206 #define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7) 207 #define ARM_ASR_R(rd, rn, rm) (_AL3_R(ARM_INST_ASR, rd, 0, rn) | (rm) << 8) 208 #define ARM_ASR_I(rd, rn, imm) (_AL3_I(ARM_INST_ASR, rd, 0, rn) | (imm) << 7) 209 210 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) 211 #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm) 212 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) 213 #define ARM_MOV_SR(rd, rm, type, rs) \ 214 (_AL3_SR(ARM_MOV_R(rd, rm)) | (type) << 5 | (rs) << 8) 215 #define ARM_MOV_SI(rd, rm, type, imm6) \ 216 (ARM_MOV_R(rd, rm) | (type) << 5 | (imm6) << 7) 217 218 #define ARM_MOVW(rd, imm) \ 219 (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) 220 221 #define ARM_MOVT(rd, imm) \ 222 (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) 223 224 #define ARM_MUL(rd, rm, rn) (ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn)) 225 226 #define ARM_POP(regs) (ARM_INST_POP | (regs)) 227 #define ARM_PUSH(regs) (ARM_INST_PUSH | (regs)) 228 229 #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) 230 #define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm) 231 #define ARM_ORR_SR(rd, rn, rm, type, rs) \ 232 (_AL3_SR(ARM_ORR_R(rd, rn, rm)) | (type) << 5 | (rs) << 8) 233 #define ARM_ORRS_R(rd, rn, rm) _AL3_R(ARM_INST_ORRS, rd, rn, rm) 234 #define ARM_ORRS_SR(rd, rn, rm, type, rs) \ 235 (_AL3_SR(ARM_ORRS_R(rd, rn, rm)) | (type) << 5 | (rs) << 8) 236 #define ARM_ORR_SI(rd, rn, rm, type, imm6) \ 237 (ARM_ORR_R(rd, rn, rm) | (type) << 5 | (imm6) << 7) 238 #define ARM_ORRS_SI(rd, rn, rm, type, imm6) \ 239 (ARM_ORRS_R(rd, rn, rm) | (type) << 5 | (imm6) << 7) 240 241 #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) 242 #define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm)) 243 244 #define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm) 245 #define ARM_RSBS_I(rd, rn, imm) _AL3_I(ARM_INST_RSBS, rd, rn, imm) 246 #define ARM_RSC_I(rd, rn, imm) _AL3_I(ARM_INST_RSC, rd, rn, imm) 247 248 #define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm) 249 #define ARM_SUBS_R(rd, rn, rm) _AL3_R(ARM_INST_SUBS, rd, rn, rm) 250 #define ARM_RSB_R(rd, rn, rm) _AL3_R(ARM_INST_RSB, rd, rn, rm) 251 #define ARM_SBC_R(rd, rn, rm) _AL3_R(ARM_INST_SBC, rd, rn, rm) 252 #define ARM_SBCS_R(rd, rn, rm) _AL3_R(ARM_INST_SBCS, rd, rn, rm) 253 #define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm) 254 #define ARM_SUBS_I(rd, rn, imm) _AL3_I(ARM_INST_SUBS, rd, rn, imm) 255 #define ARM_SBC_I(rd, rn, imm) _AL3_I(ARM_INST_SBC, rd, rn, imm) 256 257 #define ARM_STR_I(rt, rn, off) (ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \ 258 | ((off) & 0xfff)) 259 #define ARM_STRH_I(rt, rn, off) (ARM_INST_STRH_I | (rt) << 12 | (rn) << 16 \ 260 | (((off) & 0xf0) << 4) | ((off) & 0xf)) 261 #define ARM_STRB_I(rt, rn, off) (ARM_INST_STRB_I | (rt) << 12 | (rn) << 16 \ 262 | (((off) & 0xf0) << 4) | ((off) & 0xf)) 263 264 #define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm) 265 #define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm) 266 267 #define ARM_UDIV(rd, rn, rm) (ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8) 268 269 #define ARM_UMULL(rd_lo, rd_hi, rn, rm) (ARM_INST_UMULL | (rd_hi) << 16 \ 270 | (rd_lo) << 12 | (rm) << 8 | rn) 271 272 #define ARM_MLS(rd, rn, rm, ra) (ARM_INST_MLS | (rd) << 16 | (rn) | (rm) << 8 \ 273 | (ra) << 12) 274 #define ARM_UXTH(rd, rm) (ARM_INST_UXTH | (rd) << 12 | (rm)) 275 276 #endif /* PFILTER_OPCODES_ARM_H */ 277