1/* 2 * linux/arch/arm/mm/proc-xscale.S 3 * 4 * Author: Nicolas Pitre 5 * Created: November 2000 6 * Copyright: (C) 2000, 2001 MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * MMU functions for the Intel XScale CPUs 13 * 14 * 2001 Aug 21: 15 * some contributions by Brett Gaines <brett.w.gaines@intel.com> 16 * Copyright 2001 by Intel Corp. 17 * 18 * 2001 Sep 08: 19 * Completely revisited, many important fixes 20 * Nicolas Pitre <nico@fluxnic.net> 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <asm/assembler.h> 26#include <asm/hwcap.h> 27#include <asm/pgtable.h> 28#include <asm/pgtable-hwdef.h> 29#include <asm/page.h> 30#include <asm/ptrace.h> 31#include "proc-macros.S" 32 33/* 34 * This is the maximum size of an area which will be flushed. If the area 35 * is larger than this, then we flush the whole cache 36 */ 37#define MAX_AREA_SIZE 32768 38 39/* 40 * the cache line size of the I and D cache 41 */ 42#define CACHELINESIZE 32 43 44/* 45 * the size of the data cache 46 */ 47#define CACHESIZE 32768 48 49/* 50 * Virtual address used to allocate the cache when flushed 51 * 52 * This must be an address range which is _never_ used. It should 53 * apparently have a mapping in the corresponding page table for 54 * compatibility with future CPUs that _could_ require it. For instance we 55 * don't care. 56 * 57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 58 * the 2 areas in alternance each time the clean_d_cache macro is used. 59 * Without this the XScale core exhibits cache eviction problems and no one 60 * knows why. 61 * 62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 63 */ 64#define CLEAN_ADDR 0xfffe0000 65 66/* 67 * This macro is used to wait for a CP15 write and is needed 68 * when we have to ensure that the last operation to the co-pro 69 * was completed before continuing with operation. 70 */ 71 .macro cpwait, rd 72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 73 mov \rd, \rd @ wait for completion 74 sub pc, pc, #4 @ flush instruction pipeline 75 .endm 76 77 .macro cpwait_ret, lr, rd 78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 79 sub pc, \lr, \rd, LSR #32 @ wait for completion and 80 @ flush instruction pipeline 81 .endm 82 83/* 84 * This macro cleans the entire dcache using line allocate. 85 * The main loop has been unrolled to reduce loop overhead. 86 * rd and rs are two scratch registers. 87 */ 88 .macro clean_d_cache, rd, rs 89 ldr \rs, =clean_addr 90 ldr \rd, [\rs] 91 eor \rd, \rd, #CACHESIZE 92 str \rd, [\rs] 93 add \rs, \rd, #CACHESIZE 941: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 add \rd, \rd, #CACHELINESIZE 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 add \rd, \rd, #CACHELINESIZE 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 99 add \rd, \rd, #CACHELINESIZE 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 101 add \rd, \rd, #CACHELINESIZE 102 teq \rd, \rs 103 bne 1b 104 .endm 105 106 .data 107clean_addr: .word CLEAN_ADDR 108 109 .text 110 111/* 112 * cpu_xscale_proc_init() 113 * 114 * Nothing too exciting at the moment 115 */ 116ENTRY(cpu_xscale_proc_init) 117 @ enable write buffer coalescing. Some bootloader disable it 118 mrc p15, 0, r1, c1, c0, 1 119 bic r1, r1, #1 120 mcr p15, 0, r1, c1, c0, 1 121 ret lr 122 123/* 124 * cpu_xscale_proc_fin() 125 */ 126ENTRY(cpu_xscale_proc_fin) 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 128 bic r0, r0, #0x1800 @ ...IZ........... 129 bic r0, r0, #0x0006 @ .............CA. 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 131 ret lr 132 133/* 134 * cpu_xscale_reset(loc) 135 * 136 * Perform a soft reset of the system. Put the CPU into the 137 * same state as it would be if it had been reset, and branch 138 * to what would be the reset vector. 139 * 140 * loc: location to jump to for soft reset 141 * 142 * Beware PXA270 erratum E7. 143 */ 144 .align 5 145 .pushsection .idmap.text, "ax" 146ENTRY(cpu_xscale_reset) 147 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 148 msr cpsr_c, r1 @ reset CPSR 149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 151 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 152 bic r1, r1, #0x0086 @ ........B....CA. 153 bic r1, r1, #0x3900 @ ..VIZ..S........ 154 sub pc, pc, #4 @ flush pipeline 155 @ *** cache line aligned *** 156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 157 bic r1, r1, #0x0001 @ ...............M 158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 160 @ CAUTION: MMU turned off from this point. We count on the pipeline 161 @ already containing those two last instructions to survive. 162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 163 ret r0 164ENDPROC(cpu_xscale_reset) 165 .popsection 166 167/* 168 * cpu_xscale_do_idle() 169 * 170 * Cause the processor to idle 171 * 172 * For now we do nothing but go to idle mode for every case 173 * 174 * XScale supports clock switching, but using idle mode support 175 * allows external hardware to react to system state changes. 176 */ 177 .align 5 178 179ENTRY(cpu_xscale_do_idle) 180 mov r0, #1 181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 182 ret lr 183 184/* ================================= CACHE ================================ */ 185 186/* 187 * flush_icache_all() 188 * 189 * Unconditionally clean and invalidate the entire icache. 190 */ 191ENTRY(xscale_flush_icache_all) 192 mov r0, #0 193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 194 ret lr 195ENDPROC(xscale_flush_icache_all) 196 197/* 198 * flush_user_cache_all() 199 * 200 * Invalidate all cache entries in a particular address 201 * space. 202 */ 203ENTRY(xscale_flush_user_cache_all) 204 /* FALLTHROUGH */ 205 206/* 207 * flush_kern_cache_all() 208 * 209 * Clean and invalidate the entire cache. 210 */ 211ENTRY(xscale_flush_kern_cache_all) 212 mov r2, #VM_EXEC 213 mov ip, #0 214__flush_whole_cache: 215 clean_d_cache r0, r1 216 tst r2, #VM_EXEC 217 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 218 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 219 ret lr 220 221/* 222 * flush_user_cache_range(start, end, vm_flags) 223 * 224 * Invalidate a range of cache entries in the specified 225 * address space. 226 * 227 * - start - start address (may not be aligned) 228 * - end - end address (exclusive, may not be aligned) 229 * - vma - vma_area_struct describing address space 230 */ 231 .align 5 232ENTRY(xscale_flush_user_cache_range) 233 mov ip, #0 234 sub r3, r1, r0 @ calculate total size 235 cmp r3, #MAX_AREA_SIZE 236 bhs __flush_whole_cache 237 2381: tst r2, #VM_EXEC 239 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 240 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 241 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 242 add r0, r0, #CACHELINESIZE 243 cmp r0, r1 244 blo 1b 245 tst r2, #VM_EXEC 246 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 247 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 248 ret lr 249 250/* 251 * coherent_kern_range(start, end) 252 * 253 * Ensure coherency between the Icache and the Dcache in the 254 * region described by start. If you have non-snooping 255 * Harvard caches, you need to implement this function. 256 * 257 * - start - virtual start address 258 * - end - virtual end address 259 * 260 * Note: single I-cache line invalidation isn't used here since 261 * it also trashes the mini I-cache used by JTAG debuggers. 262 */ 263ENTRY(xscale_coherent_kern_range) 264 bic r0, r0, #CACHELINESIZE - 1 2651: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 266 add r0, r0, #CACHELINESIZE 267 cmp r0, r1 268 blo 1b 269 mov r0, #0 270 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 271 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 272 ret lr 273 274/* 275 * coherent_user_range(start, end) 276 * 277 * Ensure coherency between the Icache and the Dcache in the 278 * region described by start. If you have non-snooping 279 * Harvard caches, you need to implement this function. 280 * 281 * - start - virtual start address 282 * - end - virtual end address 283 */ 284ENTRY(xscale_coherent_user_range) 285 bic r0, r0, #CACHELINESIZE - 1 2861: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 287 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 288 add r0, r0, #CACHELINESIZE 289 cmp r0, r1 290 blo 1b 291 mov r0, #0 292 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 293 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 294 ret lr 295 296/* 297 * flush_kern_dcache_area(void *addr, size_t size) 298 * 299 * Ensure no D cache aliasing occurs, either with itself or 300 * the I cache 301 * 302 * - addr - kernel address 303 * - size - region size 304 */ 305ENTRY(xscale_flush_kern_dcache_area) 306 add r1, r0, r1 3071: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 309 add r0, r0, #CACHELINESIZE 310 cmp r0, r1 311 blo 1b 312 mov r0, #0 313 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 314 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 315 ret lr 316 317/* 318 * dma_inv_range(start, end) 319 * 320 * Invalidate (discard) the specified virtual address range. 321 * May not write back any entries. If 'start' or 'end' 322 * are not cache line aligned, those lines must be written 323 * back. 324 * 325 * - start - virtual start address 326 * - end - virtual end address 327 */ 328xscale_dma_inv_range: 329 tst r0, #CACHELINESIZE - 1 330 bic r0, r0, #CACHELINESIZE - 1 331 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 332 tst r1, #CACHELINESIZE - 1 333 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3341: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 335 add r0, r0, #CACHELINESIZE 336 cmp r0, r1 337 blo 1b 338 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 339 ret lr 340 341/* 342 * dma_clean_range(start, end) 343 * 344 * Clean the specified virtual address range. 345 * 346 * - start - virtual start address 347 * - end - virtual end address 348 */ 349xscale_dma_clean_range: 350 bic r0, r0, #CACHELINESIZE - 1 3511: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 352 add r0, r0, #CACHELINESIZE 353 cmp r0, r1 354 blo 1b 355 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 356 ret lr 357 358/* 359 * dma_flush_range(start, end) 360 * 361 * Clean and invalidate the specified virtual address range. 362 * 363 * - start - virtual start address 364 * - end - virtual end address 365 */ 366ENTRY(xscale_dma_flush_range) 367 bic r0, r0, #CACHELINESIZE - 1 3681: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 370 add r0, r0, #CACHELINESIZE 371 cmp r0, r1 372 blo 1b 373 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 374 ret lr 375 376/* 377 * dma_map_area(start, size, dir) 378 * - start - kernel virtual start address 379 * - size - size of region 380 * - dir - DMA direction 381 */ 382ENTRY(xscale_dma_map_area) 383 add r1, r1, r0 384 cmp r2, #DMA_TO_DEVICE 385 beq xscale_dma_clean_range 386 bcs xscale_dma_inv_range 387 b xscale_dma_flush_range 388ENDPROC(xscale_dma_map_area) 389 390/* 391 * dma_map_area(start, size, dir) 392 * - start - kernel virtual start address 393 * - size - size of region 394 * - dir - DMA direction 395 */ 396ENTRY(xscale_80200_A0_A1_dma_map_area) 397 add r1, r1, r0 398 teq r2, #DMA_TO_DEVICE 399 beq xscale_dma_clean_range 400 b xscale_dma_flush_range 401ENDPROC(xscale_80200_A0_A1_dma_map_area) 402 403/* 404 * dma_unmap_area(start, size, dir) 405 * - start - kernel virtual start address 406 * - size - size of region 407 * - dir - DMA direction 408 */ 409ENTRY(xscale_dma_unmap_area) 410 ret lr 411ENDPROC(xscale_dma_unmap_area) 412 413 .globl xscale_flush_kern_cache_louis 414 .equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all 415 416 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 417 define_cache_functions xscale 418 419/* 420 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't 421 * clear the dirty bits, which means that if we invalidate a dirty line, 422 * the dirty data can still be written back to external memory later on. 423 * 424 * The recommended workaround is to always do a clean D-cache line before 425 * doing an invalidate D-cache line, so on the affected processors, 426 * dma_inv_range() is implemented as dma_flush_range(). 427 * 428 * See erratum #25 of "Intel 80200 Processor Specification Update", 429 * revision January 22, 2003, available at: 430 * http://www.intel.com/design/iio/specupdt/273415.htm 431 */ 432.macro a0_alias basename 433 .globl xscale_80200_A0_A1_\basename 434 .type xscale_80200_A0_A1_\basename , %function 435 .equ xscale_80200_A0_A1_\basename , xscale_\basename 436.endm 437 438/* 439 * Most of the cache functions are unchanged for these processor revisions. 440 * Export suitable alias symbols for the unchanged functions: 441 */ 442 a0_alias flush_icache_all 443 a0_alias flush_user_cache_all 444 a0_alias flush_kern_cache_all 445 a0_alias flush_kern_cache_louis 446 a0_alias flush_user_cache_range 447 a0_alias coherent_kern_range 448 a0_alias coherent_user_range 449 a0_alias flush_kern_dcache_area 450 a0_alias dma_flush_range 451 a0_alias dma_unmap_area 452 453 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 454 define_cache_functions xscale_80200_A0_A1 455 456ENTRY(cpu_xscale_dcache_clean_area) 4571: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 458 add r0, r0, #CACHELINESIZE 459 subs r1, r1, #CACHELINESIZE 460 bhi 1b 461 ret lr 462 463/* =============================== PageTable ============================== */ 464 465/* 466 * cpu_xscale_switch_mm(pgd) 467 * 468 * Set the translation base pointer to be as described by pgd. 469 * 470 * pgd: new page tables 471 */ 472 .align 5 473ENTRY(cpu_xscale_switch_mm) 474 clean_d_cache r1, r2 475 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 476 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 477 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 478 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 479 cpwait_ret lr, ip 480 481/* 482 * cpu_xscale_set_pte_ext(ptep, pte, ext) 483 * 484 * Set a PTE and flush it out 485 * 486 * Errata 40: must set memory to write-through for user read-only pages. 487 */ 488cpu_xscale_mt_table: 489 .long 0x00 @ L_PTE_MT_UNCACHED 490 .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE 491 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH 492 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK 493 .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED 494 .long 0x00 @ unused 495 .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE 496 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC 497 .long 0x00 @ unused 498 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC 499 .long 0x00 @ unused 500 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED 501 .long 0x00 @ L_PTE_MT_DEV_NONSHARED 502 .long 0x00 @ unused 503 .long 0x00 @ unused 504 .long 0x00 @ unused 505 506 .align 5 507ENTRY(cpu_xscale_set_pte_ext) 508 xscale_set_pte_ext_prologue 509 510 @ 511 @ Erratum 40: must set memory to write-through for user read-only pages 512 @ 513 and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) 514 teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY 515 516 moveq r1, #L_PTE_MT_WRITETHROUGH 517 and r1, r1, #L_PTE_MT_MASK 518 adr ip, cpu_xscale_mt_table 519 ldr ip, [ip, r1] 520 bic r2, r2, #0x0c 521 orr r2, r2, ip 522 523 xscale_set_pte_ext_epilogue 524 ret lr 525 526 .ltorg 527 .align 528 529.globl cpu_xscale_suspend_size 530.equ cpu_xscale_suspend_size, 4 * 6 531#ifdef CONFIG_ARM_CPU_SUSPEND 532ENTRY(cpu_xscale_do_suspend) 533 stmfd sp!, {r4 - r9, lr} 534 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 535 mrc p15, 0, r5, c15, c1, 0 @ CP access reg 536 mrc p15, 0, r6, c13, c0, 0 @ PID 537 mrc p15, 0, r7, c3, c0, 0 @ domain ID 538 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg 539 mrc p15, 0, r9, c1, c0, 0 @ control reg 540 bic r4, r4, #2 @ clear frequency change bit 541 stmia r0, {r4 - r9} @ store cp regs 542 ldmfd sp!, {r4 - r9, pc} 543ENDPROC(cpu_xscale_do_suspend) 544 545ENTRY(cpu_xscale_do_resume) 546 ldmia r0, {r4 - r9} @ load cp regs 547 mov ip, #0 548 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 550 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 551 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 552 mcr p15, 0, r6, c13, c0, 0 @ PID 553 mcr p15, 0, r7, c3, c0, 0 @ domain ID 554 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 555 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg 556 mov r0, r9 @ control register 557 b cpu_resume_mmu 558ENDPROC(cpu_xscale_do_resume) 559#endif 560 561 .type __xscale_setup, #function 562__xscale_setup: 563 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 564 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 565 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 566 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 567 orr r0, r0, #1 << 13 @ Its undefined whether this 568 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 569 570 adr r5, xscale_crval 571 ldmia r5, {r5, r6} 572 mrc p15, 0, r0, c1, c0, 0 @ get control register 573 bic r0, r0, r5 574 orr r0, r0, r6 575 ret lr 576 .size __xscale_setup, . - __xscale_setup 577 578 /* 579 * R 580 * .RVI ZFRS BLDP WCAM 581 * ..11 1.01 .... .101 582 * 583 */ 584 .type xscale_crval, #object 585xscale_crval: 586 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 587 588 __INITDATA 589 590 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 591 define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1 592 593 .section ".rodata" 594 595 string cpu_arch_name, "armv5te" 596 string cpu_elf_name, "v5" 597 598 string cpu_80200_A0_A1_name, "XScale-80200 A0/A1" 599 string cpu_80200_name, "XScale-80200" 600 string cpu_80219_name, "XScale-80219" 601 string cpu_8032x_name, "XScale-IOP8032x Family" 602 string cpu_8033x_name, "XScale-IOP8033x Family" 603 string cpu_pxa250_name, "XScale-PXA250" 604 string cpu_pxa210_name, "XScale-PXA210" 605 string cpu_ixp42x_name, "XScale-IXP42x Family" 606 string cpu_ixp43x_name, "XScale-IXP43x Family" 607 string cpu_ixp46x_name, "XScale-IXP46x Family" 608 string cpu_ixp2400_name, "XScale-IXP2400" 609 string cpu_ixp2800_name, "XScale-IXP2800" 610 string cpu_pxa255_name, "XScale-PXA255" 611 string cpu_pxa270_name, "XScale-PXA270" 612 613 .align 614 615 .section ".proc.info.init", #alloc 616 617.macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache 618 .type __\name\()_proc_info,#object 619__\name\()_proc_info: 620 .long \cpu_val 621 .long \cpu_mask 622 .long PMD_TYPE_SECT | \ 623 PMD_SECT_BUFFERABLE | \ 624 PMD_SECT_CACHEABLE | \ 625 PMD_SECT_AP_WRITE | \ 626 PMD_SECT_AP_READ 627 .long PMD_TYPE_SECT | \ 628 PMD_SECT_AP_WRITE | \ 629 PMD_SECT_AP_READ 630 initfn __xscale_setup, __\name\()_proc_info 631 .long cpu_arch_name 632 .long cpu_elf_name 633 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 634 .long \cpu_name 635 .long xscale_processor_functions 636 .long v4wbi_tlb_fns 637 .long xscale_mc_user_fns 638 .ifb \cache 639 .long xscale_cache_fns 640 .else 641 .long \cache 642 .endif 643 .size __\name\()_proc_info, . - __\name\()_proc_info 644.endm 645 646 xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \ 647 cache=xscale_80200_A0_A1_cache_fns 648 xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name 649 xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name 650 xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name 651 xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name 652 xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name 653 xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name 654 xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name 655 xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name 656 xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name 657 xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name 658 xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name 659 xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name 660 xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name 661