xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision e1f7c9ee) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#ifdef CONFIG_ARM_LPAE
23#include "proc-v7-3level.S"
24#else
25#include "proc-v7-2level.S"
26#endif
27
28ENTRY(cpu_v7_proc_init)
29	ret	lr
30ENDPROC(cpu_v7_proc_init)
31
32ENTRY(cpu_v7_proc_fin)
33	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
34	bic	r0, r0, #0x1000			@ ...i............
35	bic	r0, r0, #0x0006			@ .............ca.
36	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37	ret	lr
38ENDPROC(cpu_v7_proc_fin)
39
40/*
41 *	cpu_v7_reset(loc)
42 *
43 *	Perform a soft reset of the system.  Put the CPU into the
44 *	same state as it would be if it had been reset, and branch
45 *	to what would be the reset vector.
46 *
47 *	- loc   - location to jump to for soft reset
48 *
49 *	This code must be executed using a flat identity mapping with
50 *      caches disabled.
51 */
52	.align	5
53	.pushsection	.idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
56	bic	r1, r1, #0x1			@ ...............m
57 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
59	isb
60	bx	r0
61ENDPROC(cpu_v7_reset)
62	.popsection
63
64/*
65 *	cpu_v7_do_idle()
66 *
67 *	Idle the processor (eg, wait for interrupt).
68 *
69 *	IRQs are already disabled.
70 */
71ENTRY(cpu_v7_do_idle)
72	dsb					@ WFI may enter a low-power mode
73	wfi
74	ret	lr
75ENDPROC(cpu_v7_do_idle)
76
77ENTRY(cpu_v7_dcache_clean_area)
78	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
79	ALT_UP_B(1f)
80	ret	lr
811:	dcache_line_size r2, r3
822:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
83	add	r0, r0, r2
84	subs	r1, r1, r2
85	bhi	2b
86	dsb	ishst
87	ret	lr
88ENDPROC(cpu_v7_dcache_clean_area)
89
90	string	cpu_v7_name, "ARMv7 Processor"
91	.align
92
93/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94.globl	cpu_v7_suspend_size
95.equ	cpu_v7_suspend_size, 4 * 9
96#ifdef CONFIG_ARM_CPU_SUSPEND
97ENTRY(cpu_v7_do_suspend)
98	stmfd	sp!, {r4 - r10, lr}
99	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
100	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
101	stmia	r0!, {r4 - r5}
102#ifdef CONFIG_MMU
103	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
104#ifdef CONFIG_ARM_LPAE
105	mrrc	p15, 1, r5, r7, c2	@ TTB 1
106#else
107	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
108#endif
109	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
110#endif
111	mrc	p15, 0, r8, c1, c0, 0	@ Control register
112	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
113	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
114	stmia	r0, {r5 - r11}
115	ldmfd	sp!, {r4 - r10, pc}
116ENDPROC(cpu_v7_do_suspend)
117
118ENTRY(cpu_v7_do_resume)
119	mov	ip, #0
120	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
121	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
122	ldmia	r0!, {r4 - r5}
123	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
124	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
125	ldmia	r0, {r5 - r11}
126#ifdef CONFIG_MMU
127	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
128	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
129#ifdef CONFIG_ARM_LPAE
130	mcrr	p15, 0, r1, ip, c2	@ TTB 0
131	mcrr	p15, 1, r5, r7, c2	@ TTB 1
132#else
133	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
134	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
135	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
136	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
137#endif
138	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
139	ldr	r4, =PRRR		@ PRRR
140	ldr	r5, =NMRR		@ NMRR
141	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
142	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
143#endif	/* CONFIG_MMU */
144	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
145	teq	r4, r9			@ Is it already set?
146	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
147	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
148	isb
149	dsb
150	mov	r0, r8			@ control register
151	b	cpu_resume_mmu
152ENDPROC(cpu_v7_do_resume)
153#endif
154
155/*
156 * Cortex-A9 processor functions
157 */
158	globl_equ	cpu_ca9mp_proc_init,	cpu_v7_proc_init
159	globl_equ	cpu_ca9mp_proc_fin,	cpu_v7_proc_fin
160	globl_equ	cpu_ca9mp_reset,	cpu_v7_reset
161	globl_equ	cpu_ca9mp_do_idle,	cpu_v7_do_idle
162	globl_equ	cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
163	globl_equ	cpu_ca9mp_switch_mm,	cpu_v7_switch_mm
164	globl_equ	cpu_ca9mp_set_pte_ext,	cpu_v7_set_pte_ext
165.globl	cpu_ca9mp_suspend_size
166.equ	cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
167#ifdef CONFIG_ARM_CPU_SUSPEND
168ENTRY(cpu_ca9mp_do_suspend)
169	stmfd	sp!, {r4 - r5}
170	mrc	p15, 0, r4, c15, c0, 1		@ Diagnostic register
171	mrc	p15, 0, r5, c15, c0, 0		@ Power register
172	stmia	r0!, {r4 - r5}
173	ldmfd	sp!, {r4 - r5}
174	b	cpu_v7_do_suspend
175ENDPROC(cpu_ca9mp_do_suspend)
176
177ENTRY(cpu_ca9mp_do_resume)
178	ldmia	r0!, {r4 - r5}
179	mrc	p15, 0, r10, c15, c0, 1		@ Read Diagnostic register
180	teq	r4, r10				@ Already restored?
181	mcrne	p15, 0, r4, c15, c0, 1		@ No, so restore it
182	mrc	p15, 0, r10, c15, c0, 0		@ Read Power register
183	teq	r5, r10				@ Already restored?
184	mcrne	p15, 0, r5, c15, c0, 0		@ No, so restore it
185	b	cpu_v7_do_resume
186ENDPROC(cpu_ca9mp_do_resume)
187#endif
188
189#ifdef CONFIG_CPU_PJ4B
190	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
191	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
192	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
193	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
194	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
195#ifdef CONFIG_PJ4B_ERRATA_4742
196ENTRY(cpu_pj4b_do_idle)
197	dsb					@ WFI may enter a low-power mode
198	wfi
199	dsb					@barrier
200	ret	lr
201ENDPROC(cpu_pj4b_do_idle)
202#else
203	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
204#endif
205	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
206#ifdef CONFIG_ARM_CPU_SUSPEND
207ENTRY(cpu_pj4b_do_suspend)
208	stmfd	sp!, {r6 - r10}
209	mrc	p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
210	mrc	p15, 1, r7, c15, c2, 0	@ save CP15 - Aux Func Modes Ctrl 0
211	mrc	p15, 1, r8, c15, c1, 2	@ save CP15 - Aux Debug Modes Ctrl 2
212	mrc	p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
213	mrc	p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
214	stmia	r0!, {r6 - r10}
215	ldmfd	sp!, {r6 - r10}
216	b cpu_v7_do_suspend
217ENDPROC(cpu_pj4b_do_suspend)
218
219ENTRY(cpu_pj4b_do_resume)
220	ldmia	r0!, {r6 - r10}
221	mcr	p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
222	mcr	p15, 1, r7, c15, c2, 0	@ restore CP15 - Aux Func Modes Ctrl 0
223	mcr	p15, 1, r8, c15, c1, 2	@ restore CP15 - Aux Debug Modes Ctrl 2
224	mcr	p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
225	mcr	p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
226	b cpu_v7_do_resume
227ENDPROC(cpu_pj4b_do_resume)
228#endif
229.globl	cpu_pj4b_suspend_size
230.equ	cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
231
232#endif
233
234/*
235 *	__v7_setup
236 *
237 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
238 *	on.  Return in r0 the new CP15 C1 control register setting.
239 *
240 *	This should be able to cover all ARMv7 cores.
241 *
242 *	It is assumed that:
243 *	- cache type register is implemented
244 */
245__v7_ca5mp_setup:
246__v7_ca9mp_setup:
247__v7_cr7mp_setup:
248	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
249	b	1f
250__v7_ca7mp_setup:
251__v7_ca12mp_setup:
252__v7_ca15mp_setup:
253__v7_b15mp_setup:
254__v7_ca17mp_setup:
255	mov	r10, #0
2561:
257#ifdef CONFIG_SMP
258	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
259	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
260	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
261	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
262	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
263	mcreq	p15, 0, r0, c1, c0, 1
264#endif
265	b	__v7_setup
266
267__v7_pj4b_setup:
268#ifdef CONFIG_CPU_PJ4B
269
270/* Auxiliary Debug Modes Control 1 Register */
271#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
272#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
273#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
274#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
275
276/* Auxiliary Debug Modes Control 2 Register */
277#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
278#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
279#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
280#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
281#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
282#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
283			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
284
285/* Auxiliary Functional Modes Control Register 0 */
286#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
287#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
288#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
289
290/* Auxiliary Debug Modes Control 0 Register */
291#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
292
293	/* Auxiliary Debug Modes Control 1 Register */
294	mrc	p15, 1,	r0, c15, c1, 1
295	orr     r0, r0, #PJ4B_CLEAN_LINE
296	orr     r0, r0, #PJ4B_BCK_OFF_STREX
297	orr     r0, r0, #PJ4B_INTER_PARITY
298	bic	r0, r0, #PJ4B_STATIC_BP
299	mcr	p15, 1,	r0, c15, c1, 1
300
301	/* Auxiliary Debug Modes Control 2 Register */
302	mrc	p15, 1,	r0, c15, c1, 2
303	bic	r0, r0, #PJ4B_FAST_LDR
304	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
305	mcr	p15, 1,	r0, c15, c1, 2
306
307	/* Auxiliary Functional Modes Control Register 0 */
308	mrc	p15, 1,	r0, c15, c2, 0
309#ifdef CONFIG_SMP
310	orr	r0, r0, #PJ4B_SMP_CFB
311#endif
312	orr	r0, r0, #PJ4B_L1_PAR_CHK
313	orr	r0, r0, #PJ4B_BROADCAST_CACHE
314	mcr	p15, 1,	r0, c15, c2, 0
315
316	/* Auxiliary Debug Modes Control 0 Register */
317	mrc	p15, 1,	r0, c15, c1, 0
318	orr	r0, r0, #PJ4B_WFI_WFE
319	mcr	p15, 1,	r0, c15, c1, 0
320
321#endif /* CONFIG_CPU_PJ4B */
322
323__v7_setup:
324	adr	r12, __v7_setup_stack		@ the local stack
325	stmia	r12, {r0-r5, r7, r9, r11, lr}
326	bl      v7_flush_dcache_louis
327	ldmia	r12, {r0-r5, r7, r9, r11, lr}
328
329	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
330	and	r10, r0, #0xff000000		@ ARM?
331	teq	r10, #0x41000000
332	bne	3f
333	and	r5, r0, #0x00f00000		@ variant
334	and	r6, r0, #0x0000000f		@ revision
335	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
336	ubfx	r0, r0, #4, #12			@ primary part number
337
338	/* Cortex-A8 Errata */
339	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
340	teq	r0, r10
341	bne	2f
342#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
343
344	teq	r5, #0x00100000			@ only present in r1p*
345	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
346	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
347	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
348#endif
349#ifdef CONFIG_ARM_ERRATA_458693
350	teq	r6, #0x20			@ only present in r2p0
351	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
352	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
353	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
354	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
355#endif
356#ifdef CONFIG_ARM_ERRATA_460075
357	teq	r6, #0x20			@ only present in r2p0
358	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
359	tsteq	r10, #1 << 22
360	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
361	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
362#endif
363	b	3f
364
365	/* Cortex-A9 Errata */
3662:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
367	teq	r0, r10
368	bne	3f
369#ifdef CONFIG_ARM_ERRATA_742230
370	cmp	r6, #0x22			@ only present up to r2p2
371	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
372	orrle	r10, r10, #1 << 4		@ set bit #4
373	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
374#endif
375#ifdef CONFIG_ARM_ERRATA_742231
376	teq	r6, #0x20			@ present in r2p0
377	teqne	r6, #0x21			@ present in r2p1
378	teqne	r6, #0x22			@ present in r2p2
379	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
380	orreq	r10, r10, #1 << 12		@ set bit #12
381	orreq	r10, r10, #1 << 22		@ set bit #22
382	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
383#endif
384#ifdef CONFIG_ARM_ERRATA_743622
385	teq	r5, #0x00200000			@ only present in r2p*
386	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
387	orreq	r10, r10, #1 << 6		@ set bit #6
388	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
389#endif
390#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
391	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
392	ALT_UP_B(1f)
393	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
394	orrlt	r10, r10, #1 << 11		@ set bit #11
395	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
3961:
397#endif
398
399	/* Cortex-A15 Errata */
4003:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
401	teq	r0, r10
402	bne	4f
403
404#ifdef CONFIG_ARM_ERRATA_773022
405	cmp	r6, #0x4			@ only present up to r0p4
406	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
407	orrle	r10, r10, #1 << 1		@ disable loop buffer
408	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
409#endif
410
4114:	mov	r10, #0
412	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
413#ifdef CONFIG_MMU
414	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
415	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
416	ldr	r5, =PRRR			@ PRRR
417	ldr	r6, =NMRR			@ NMRR
418	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
419	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
420#endif
421	dsb					@ Complete invalidations
422#ifndef CONFIG_ARM_THUMBEE
423	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
424	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
425	teq	r0, #(1 << 12)			@ check if ThumbEE is present
426	bne	1f
427	mov	r5, #0
428	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
429	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
430	orr	r0, r0, #1			@ set the 1st bit in order to
431	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
4321:
433#endif
434	adr	r5, v7_crval
435	ldmia	r5, {r5, r6}
436 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
437#ifdef CONFIG_SWP_EMULATE
438	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
439	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
440#endif
441   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
442	bic	r0, r0, r5			@ clear bits them
443	orr	r0, r0, r6			@ set them
444 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
445	ret	lr				@ return to head.S:__ret
446ENDPROC(__v7_setup)
447
448	.align	2
449__v7_setup_stack:
450	.space	4 * 11				@ 11 registers
451
452	__INITDATA
453
454	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
455	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
456	define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
457#ifdef CONFIG_CPU_PJ4B
458	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
459#endif
460
461	.section ".rodata"
462
463	string	cpu_arch_name, "armv7"
464	string	cpu_elf_name, "v7"
465	.align
466
467	.section ".proc.info.init", #alloc, #execinstr
468
469	/*
470	 * Standard v7 proc info content
471	 */
472.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
473	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
474			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
475	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
476			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
477	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
478		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
479	W(b)	\initfunc
480	.long	cpu_arch_name
481	.long	cpu_elf_name
482	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
483		HWCAP_EDSP | HWCAP_TLS | \hwcaps
484	.long	cpu_v7_name
485	.long	\proc_fns
486	.long	v7wbi_tlb_fns
487	.long	v6_user_fns
488	.long	v7_cache_fns
489.endm
490
491#ifndef CONFIG_ARM_LPAE
492	/*
493	 * ARM Ltd. Cortex A5 processor.
494	 */
495	.type   __v7_ca5mp_proc_info, #object
496__v7_ca5mp_proc_info:
497	.long	0x410fc050
498	.long	0xff0ffff0
499	__v7_proc __v7_ca5mp_setup
500	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
501
502	/*
503	 * ARM Ltd. Cortex A9 processor.
504	 */
505	.type   __v7_ca9mp_proc_info, #object
506__v7_ca9mp_proc_info:
507	.long	0x410fc090
508	.long	0xff0ffff0
509	__v7_proc __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
510	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
511
512#endif	/* CONFIG_ARM_LPAE */
513
514	/*
515	 * Marvell PJ4B processor.
516	 */
517#ifdef CONFIG_CPU_PJ4B
518	.type   __v7_pj4b_proc_info, #object
519__v7_pj4b_proc_info:
520	.long	0x560f5800
521	.long	0xff0fff00
522	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
523	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
524#endif
525
526	/*
527	 * ARM Ltd. Cortex R7 processor.
528	 */
529	.type	__v7_cr7mp_proc_info, #object
530__v7_cr7mp_proc_info:
531	.long	0x410fc170
532	.long	0xff0ffff0
533	__v7_proc __v7_cr7mp_setup
534	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
535
536	/*
537	 * ARM Ltd. Cortex A7 processor.
538	 */
539	.type	__v7_ca7mp_proc_info, #object
540__v7_ca7mp_proc_info:
541	.long	0x410fc070
542	.long	0xff0ffff0
543	__v7_proc __v7_ca7mp_setup
544	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
545
546	/*
547	 * ARM Ltd. Cortex A12 processor.
548	 */
549	.type	__v7_ca12mp_proc_info, #object
550__v7_ca12mp_proc_info:
551	.long	0x410fc0d0
552	.long	0xff0ffff0
553	__v7_proc __v7_ca12mp_setup
554	.size	__v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
555
556	/*
557	 * ARM Ltd. Cortex A15 processor.
558	 */
559	.type	__v7_ca15mp_proc_info, #object
560__v7_ca15mp_proc_info:
561	.long	0x410fc0f0
562	.long	0xff0ffff0
563	__v7_proc __v7_ca15mp_setup
564	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
565
566	/*
567	 * Broadcom Corporation Brahma-B15 processor.
568	 */
569	.type	__v7_b15mp_proc_info, #object
570__v7_b15mp_proc_info:
571	.long	0x420f00f0
572	.long	0xff0ffff0
573	__v7_proc __v7_b15mp_setup
574	.size	__v7_b15mp_proc_info, . - __v7_b15mp_proc_info
575
576	/*
577	 * ARM Ltd. Cortex A17 processor.
578	 */
579	.type	__v7_ca17mp_proc_info, #object
580__v7_ca17mp_proc_info:
581	.long	0x410fc0e0
582	.long	0xff0ffff0
583	__v7_proc __v7_ca17mp_setup
584	.size	__v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
585
586	/*
587	 * Qualcomm Inc. Krait processors.
588	 */
589	.type	__krait_proc_info, #object
590__krait_proc_info:
591	.long	0x510f0400		@ Required ID value
592	.long	0xff0ffc00		@ Mask for ID
593	/*
594	 * Some Krait processors don't indicate support for SDIV and UDIV
595	 * instructions in the ARM instruction set, even though they actually
596	 * do support them.
597	 */
598	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
599	.size	__krait_proc_info, . - __krait_proc_info
600
601	/*
602	 * Match any ARMv7 processor core.
603	 */
604	.type	__v7_proc_info, #object
605__v7_proc_info:
606	.long	0x000f0000		@ Required ID value
607	.long	0x000f0000		@ Mask for ID
608	__v7_proc __v7_setup
609	.size	__v7_proc_info, . - __v7_proc_info
610