xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision c4ee0af3) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#ifdef CONFIG_ARM_LPAE
23#include "proc-v7-3level.S"
24#else
25#include "proc-v7-2level.S"
26#endif
27
28ENTRY(cpu_v7_proc_init)
29	mov	pc, lr
30ENDPROC(cpu_v7_proc_init)
31
32ENTRY(cpu_v7_proc_fin)
33	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
34	bic	r0, r0, #0x1000			@ ...i............
35	bic	r0, r0, #0x0006			@ .............ca.
36	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37	mov	pc, lr
38ENDPROC(cpu_v7_proc_fin)
39
40/*
41 *	cpu_v7_reset(loc)
42 *
43 *	Perform a soft reset of the system.  Put the CPU into the
44 *	same state as it would be if it had been reset, and branch
45 *	to what would be the reset vector.
46 *
47 *	- loc   - location to jump to for soft reset
48 *
49 *	This code must be executed using a flat identity mapping with
50 *      caches disabled.
51 */
52	.align	5
53	.pushsection	.idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
56	bic	r1, r1, #0x1			@ ...............m
57 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
59	isb
60	bx	r0
61ENDPROC(cpu_v7_reset)
62	.popsection
63
64/*
65 *	cpu_v7_do_idle()
66 *
67 *	Idle the processor (eg, wait for interrupt).
68 *
69 *	IRQs are already disabled.
70 */
71ENTRY(cpu_v7_do_idle)
72	dsb					@ WFI may enter a low-power mode
73	wfi
74	mov	pc, lr
75ENDPROC(cpu_v7_do_idle)
76
77ENTRY(cpu_v7_dcache_clean_area)
78	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
79	ALT_UP_B(1f)
80	mov	pc, lr
811:	dcache_line_size r2, r3
822:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
83	add	r0, r0, r2
84	subs	r1, r1, r2
85	bhi	2b
86	dsb	ishst
87	mov	pc, lr
88ENDPROC(cpu_v7_dcache_clean_area)
89
90	string	cpu_v7_name, "ARMv7 Processor"
91	.align
92
93/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94.globl	cpu_v7_suspend_size
95.equ	cpu_v7_suspend_size, 4 * 9
96#ifdef CONFIG_ARM_CPU_SUSPEND
97ENTRY(cpu_v7_do_suspend)
98	stmfd	sp!, {r4 - r10, lr}
99	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
100	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
101	stmia	r0!, {r4 - r5}
102#ifdef CONFIG_MMU
103	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
104#ifdef CONFIG_ARM_LPAE
105	mrrc	p15, 1, r5, r7, c2	@ TTB 1
106#else
107	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
108#endif
109	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
110#endif
111	mrc	p15, 0, r8, c1, c0, 0	@ Control register
112	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
113	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
114	stmia	r0, {r5 - r11}
115	ldmfd	sp!, {r4 - r10, pc}
116ENDPROC(cpu_v7_do_suspend)
117
118ENTRY(cpu_v7_do_resume)
119	mov	ip, #0
120	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
121	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
122	ldmia	r0!, {r4 - r5}
123	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
124	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
125	ldmia	r0, {r5 - r11}
126#ifdef CONFIG_MMU
127	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
128	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
129#ifdef CONFIG_ARM_LPAE
130	mcrr	p15, 0, r1, ip, c2	@ TTB 0
131	mcrr	p15, 1, r5, r7, c2	@ TTB 1
132#else
133	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
134	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
135	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
136	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
137#endif
138	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
139	ldr	r4, =PRRR		@ PRRR
140	ldr	r5, =NMRR		@ NMRR
141	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
142	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
143#endif	/* CONFIG_MMU */
144	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
145	teq	r4, r9			@ Is it already set?
146	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
147	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
148	isb
149	dsb
150	mov	r0, r8			@ control register
151	b	cpu_resume_mmu
152ENDPROC(cpu_v7_do_resume)
153#endif
154
155#ifdef CONFIG_CPU_PJ4B
156	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
157	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
158	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
159	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
160	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
161#ifdef CONFIG_PJ4B_ERRATA_4742
162ENTRY(cpu_pj4b_do_idle)
163	dsb					@ WFI may enter a low-power mode
164	wfi
165	dsb					@barrier
166	mov	pc, lr
167ENDPROC(cpu_pj4b_do_idle)
168#else
169	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
170#endif
171	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
172	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
173	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
174	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size
175
176#endif
177
178/*
179 *	__v7_setup
180 *
181 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
182 *	on.  Return in r0 the new CP15 C1 control register setting.
183 *
184 *	This should be able to cover all ARMv7 cores.
185 *
186 *	It is assumed that:
187 *	- cache type register is implemented
188 */
189__v7_ca5mp_setup:
190__v7_ca9mp_setup:
191__v7_cr7mp_setup:
192	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
193	b	1f
194__v7_ca7mp_setup:
195__v7_ca15mp_setup:
196	mov	r10, #0
1971:
198#ifdef CONFIG_SMP
199	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
200	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
201	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
202	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
203	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
204	mcreq	p15, 0, r0, c1, c0, 1
205#endif
206	b	__v7_setup
207
208__v7_pj4b_setup:
209#ifdef CONFIG_CPU_PJ4B
210
211/* Auxiliary Debug Modes Control 1 Register */
212#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
213#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
214#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
215#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
216
217/* Auxiliary Debug Modes Control 2 Register */
218#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
219#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
220#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
221#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
222#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
223#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
224			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
225
226/* Auxiliary Functional Modes Control Register 0 */
227#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
228#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
229#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
230
231/* Auxiliary Debug Modes Control 0 Register */
232#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
233
234	/* Auxiliary Debug Modes Control 1 Register */
235	mrc	p15, 1,	r0, c15, c1, 1
236	orr     r0, r0, #PJ4B_CLEAN_LINE
237	orr     r0, r0, #PJ4B_BCK_OFF_STREX
238	orr     r0, r0, #PJ4B_INTER_PARITY
239	bic	r0, r0, #PJ4B_STATIC_BP
240	mcr	p15, 1,	r0, c15, c1, 1
241
242	/* Auxiliary Debug Modes Control 2 Register */
243	mrc	p15, 1,	r0, c15, c1, 2
244	bic	r0, r0, #PJ4B_FAST_LDR
245	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
246	mcr	p15, 1,	r0, c15, c1, 2
247
248	/* Auxiliary Functional Modes Control Register 0 */
249	mrc	p15, 1,	r0, c15, c2, 0
250#ifdef CONFIG_SMP
251	orr	r0, r0, #PJ4B_SMP_CFB
252#endif
253	orr	r0, r0, #PJ4B_L1_PAR_CHK
254	orr	r0, r0, #PJ4B_BROADCAST_CACHE
255	mcr	p15, 1,	r0, c15, c2, 0
256
257	/* Auxiliary Debug Modes Control 0 Register */
258	mrc	p15, 1,	r0, c15, c1, 0
259	orr	r0, r0, #PJ4B_WFI_WFE
260	mcr	p15, 1,	r0, c15, c1, 0
261
262#endif /* CONFIG_CPU_PJ4B */
263
264__v7_setup:
265	adr	r12, __v7_setup_stack		@ the local stack
266	stmia	r12, {r0-r5, r7, r9, r11, lr}
267	bl      v7_flush_dcache_louis
268	ldmia	r12, {r0-r5, r7, r9, r11, lr}
269
270	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
271	and	r10, r0, #0xff000000		@ ARM?
272	teq	r10, #0x41000000
273	bne	3f
274	and	r5, r0, #0x00f00000		@ variant
275	and	r6, r0, #0x0000000f		@ revision
276	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
277	ubfx	r0, r0, #4, #12			@ primary part number
278
279	/* Cortex-A8 Errata */
280	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
281	teq	r0, r10
282	bne	2f
283#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
284
285	teq	r5, #0x00100000			@ only present in r1p*
286	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
287	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
288	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
289#endif
290#ifdef CONFIG_ARM_ERRATA_458693
291	teq	r6, #0x20			@ only present in r2p0
292	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
293	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
294	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
295	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
296#endif
297#ifdef CONFIG_ARM_ERRATA_460075
298	teq	r6, #0x20			@ only present in r2p0
299	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
300	tsteq	r10, #1 << 22
301	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
302	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
303#endif
304	b	3f
305
306	/* Cortex-A9 Errata */
3072:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
308	teq	r0, r10
309	bne	3f
310#ifdef CONFIG_ARM_ERRATA_742230
311	cmp	r6, #0x22			@ only present up to r2p2
312	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
313	orrle	r10, r10, #1 << 4		@ set bit #4
314	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
315#endif
316#ifdef CONFIG_ARM_ERRATA_742231
317	teq	r6, #0x20			@ present in r2p0
318	teqne	r6, #0x21			@ present in r2p1
319	teqne	r6, #0x22			@ present in r2p2
320	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
321	orreq	r10, r10, #1 << 12		@ set bit #12
322	orreq	r10, r10, #1 << 22		@ set bit #22
323	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
324#endif
325#ifdef CONFIG_ARM_ERRATA_743622
326	teq	r5, #0x00200000			@ only present in r2p*
327	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
328	orreq	r10, r10, #1 << 6		@ set bit #6
329	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
330#endif
331#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
332	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
333	ALT_UP_B(1f)
334	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
335	orrlt	r10, r10, #1 << 11		@ set bit #11
336	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
3371:
338#endif
339
340	/* Cortex-A15 Errata */
3413:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
342	teq	r0, r10
343	bne	4f
344
345#ifdef CONFIG_ARM_ERRATA_773022
346	cmp	r6, #0x4			@ only present up to r0p4
347	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
348	orrle	r10, r10, #1 << 1		@ disable loop buffer
349	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
350#endif
351
3524:	mov	r10, #0
353	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
354	dsb
355#ifdef CONFIG_MMU
356	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
357	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
358	ldr	r5, =PRRR			@ PRRR
359	ldr	r6, =NMRR			@ NMRR
360	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
361	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
362#endif
363#ifndef CONFIG_ARM_THUMBEE
364	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
365	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
366	teq	r0, #(1 << 12)			@ check if ThumbEE is present
367	bne	1f
368	mov	r5, #0
369	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
370	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
371	orr	r0, r0, #1			@ set the 1st bit in order to
372	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
3731:
374#endif
375	adr	r5, v7_crval
376	ldmia	r5, {r5, r6}
377 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
378#ifdef CONFIG_SWP_EMULATE
379	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
380	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
381#endif
382   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
383	bic	r0, r0, r5			@ clear bits them
384	orr	r0, r0, r6			@ set them
385 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
386	mov	pc, lr				@ return to head.S:__ret
387ENDPROC(__v7_setup)
388
389	.align	2
390__v7_setup_stack:
391	.space	4 * 11				@ 11 registers
392
393	__INITDATA
394
395	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
396	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
397#ifdef CONFIG_CPU_PJ4B
398	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
399#endif
400
401	.section ".rodata"
402
403	string	cpu_arch_name, "armv7"
404	string	cpu_elf_name, "v7"
405	.align
406
407	.section ".proc.info.init", #alloc, #execinstr
408
409	/*
410	 * Standard v7 proc info content
411	 */
412.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
413	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
414			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
415	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
416			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
417	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
418		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
419	W(b)	\initfunc
420	.long	cpu_arch_name
421	.long	cpu_elf_name
422	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
423		HWCAP_EDSP | HWCAP_TLS | \hwcaps
424	.long	cpu_v7_name
425	.long	\proc_fns
426	.long	v7wbi_tlb_fns
427	.long	v6_user_fns
428	.long	v7_cache_fns
429.endm
430
431#ifndef CONFIG_ARM_LPAE
432	/*
433	 * ARM Ltd. Cortex A5 processor.
434	 */
435	.type   __v7_ca5mp_proc_info, #object
436__v7_ca5mp_proc_info:
437	.long	0x410fc050
438	.long	0xff0ffff0
439	__v7_proc __v7_ca5mp_setup
440	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
441
442	/*
443	 * ARM Ltd. Cortex A9 processor.
444	 */
445	.type   __v7_ca9mp_proc_info, #object
446__v7_ca9mp_proc_info:
447	.long	0x410fc090
448	.long	0xff0ffff0
449	__v7_proc __v7_ca9mp_setup
450	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
451
452#endif	/* CONFIG_ARM_LPAE */
453
454	/*
455	 * Marvell PJ4B processor.
456	 */
457#ifdef CONFIG_CPU_PJ4B
458	.type   __v7_pj4b_proc_info, #object
459__v7_pj4b_proc_info:
460	.long	0x560f5800
461	.long	0xff0fff00
462	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
463	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
464#endif
465
466	/*
467	 * ARM Ltd. Cortex R7 processor.
468	 */
469	.type	__v7_cr7mp_proc_info, #object
470__v7_cr7mp_proc_info:
471	.long	0x410fc170
472	.long	0xff0ffff0
473	__v7_proc __v7_cr7mp_setup
474	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
475
476	/*
477	 * ARM Ltd. Cortex A7 processor.
478	 */
479	.type	__v7_ca7mp_proc_info, #object
480__v7_ca7mp_proc_info:
481	.long	0x410fc070
482	.long	0xff0ffff0
483	__v7_proc __v7_ca7mp_setup
484	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
485
486	/*
487	 * ARM Ltd. Cortex A15 processor.
488	 */
489	.type	__v7_ca15mp_proc_info, #object
490__v7_ca15mp_proc_info:
491	.long	0x410fc0f0
492	.long	0xff0ffff0
493	__v7_proc __v7_ca15mp_setup
494	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
495
496	/*
497	 * Qualcomm Inc. Krait processors.
498	 */
499	.type	__krait_proc_info, #object
500__krait_proc_info:
501	.long	0x510f0400		@ Required ID value
502	.long	0xff0ffc00		@ Mask for ID
503	/*
504	 * Some Krait processors don't indicate support for SDIV and UDIV
505	 * instructions in the ARM instruction set, even though they actually
506	 * do support them.
507	 */
508	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
509	.size	__krait_proc_info, . - __krait_proc_info
510
511	/*
512	 * Match any ARMv7 processor core.
513	 */
514	.type	__v7_proc_info, #object
515__v7_proc_info:
516	.long	0x000f0000		@ Required ID value
517	.long	0x000f0000		@ Mask for ID
518	__v7_proc __v7_setup
519	.size	__v7_proc_info, . - __v7_proc_info
520