xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision afb46f79) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#ifdef CONFIG_ARM_LPAE
23#include "proc-v7-3level.S"
24#else
25#include "proc-v7-2level.S"
26#endif
27
28ENTRY(cpu_v7_proc_init)
29	mov	pc, lr
30ENDPROC(cpu_v7_proc_init)
31
32ENTRY(cpu_v7_proc_fin)
33	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
34	bic	r0, r0, #0x1000			@ ...i............
35	bic	r0, r0, #0x0006			@ .............ca.
36	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37	mov	pc, lr
38ENDPROC(cpu_v7_proc_fin)
39
40/*
41 *	cpu_v7_reset(loc)
42 *
43 *	Perform a soft reset of the system.  Put the CPU into the
44 *	same state as it would be if it had been reset, and branch
45 *	to what would be the reset vector.
46 *
47 *	- loc   - location to jump to for soft reset
48 *
49 *	This code must be executed using a flat identity mapping with
50 *      caches disabled.
51 */
52	.align	5
53	.pushsection	.idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
56	bic	r1, r1, #0x1			@ ...............m
57 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
59	isb
60	bx	r0
61ENDPROC(cpu_v7_reset)
62	.popsection
63
64/*
65 *	cpu_v7_do_idle()
66 *
67 *	Idle the processor (eg, wait for interrupt).
68 *
69 *	IRQs are already disabled.
70 */
71ENTRY(cpu_v7_do_idle)
72	dsb					@ WFI may enter a low-power mode
73	wfi
74	mov	pc, lr
75ENDPROC(cpu_v7_do_idle)
76
77ENTRY(cpu_v7_dcache_clean_area)
78	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
79	ALT_UP_B(1f)
80	mov	pc, lr
811:	dcache_line_size r2, r3
822:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
83	add	r0, r0, r2
84	subs	r1, r1, r2
85	bhi	2b
86	dsb	ishst
87	mov	pc, lr
88ENDPROC(cpu_v7_dcache_clean_area)
89
90	string	cpu_v7_name, "ARMv7 Processor"
91	.align
92
93/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
94.globl	cpu_v7_suspend_size
95.equ	cpu_v7_suspend_size, 4 * 9
96#ifdef CONFIG_ARM_CPU_SUSPEND
97ENTRY(cpu_v7_do_suspend)
98	stmfd	sp!, {r4 - r10, lr}
99	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
100	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
101	stmia	r0!, {r4 - r5}
102#ifdef CONFIG_MMU
103	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
104#ifdef CONFIG_ARM_LPAE
105	mrrc	p15, 1, r5, r7, c2	@ TTB 1
106#else
107	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
108#endif
109	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
110#endif
111	mrc	p15, 0, r8, c1, c0, 0	@ Control register
112	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
113	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
114	stmia	r0, {r5 - r11}
115	ldmfd	sp!, {r4 - r10, pc}
116ENDPROC(cpu_v7_do_suspend)
117
118ENTRY(cpu_v7_do_resume)
119	mov	ip, #0
120	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
121	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
122	ldmia	r0!, {r4 - r5}
123	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
124	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
125	ldmia	r0, {r5 - r11}
126#ifdef CONFIG_MMU
127	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
128	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
129#ifdef CONFIG_ARM_LPAE
130	mcrr	p15, 0, r1, ip, c2	@ TTB 0
131	mcrr	p15, 1, r5, r7, c2	@ TTB 1
132#else
133	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
134	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
135	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
136	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
137#endif
138	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
139	ldr	r4, =PRRR		@ PRRR
140	ldr	r5, =NMRR		@ NMRR
141	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
142	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
143#endif	/* CONFIG_MMU */
144	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
145	teq	r4, r9			@ Is it already set?
146	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
147	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
148	isb
149	dsb
150	mov	r0, r8			@ control register
151	b	cpu_resume_mmu
152ENDPROC(cpu_v7_do_resume)
153#endif
154
155#ifdef CONFIG_CPU_PJ4B
156	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
157	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
158	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
159	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
160	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
161#ifdef CONFIG_PJ4B_ERRATA_4742
162ENTRY(cpu_pj4b_do_idle)
163	dsb					@ WFI may enter a low-power mode
164	wfi
165	dsb					@barrier
166	mov	pc, lr
167ENDPROC(cpu_pj4b_do_idle)
168#else
169	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
170#endif
171	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
172	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
173	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
174	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size
175
176#endif
177
178/*
179 *	__v7_setup
180 *
181 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
182 *	on.  Return in r0 the new CP15 C1 control register setting.
183 *
184 *	This should be able to cover all ARMv7 cores.
185 *
186 *	It is assumed that:
187 *	- cache type register is implemented
188 */
189__v7_ca5mp_setup:
190__v7_ca9mp_setup:
191__v7_cr7mp_setup:
192	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
193	b	1f
194__v7_ca7mp_setup:
195__v7_ca12mp_setup:
196__v7_ca15mp_setup:
197	mov	r10, #0
1981:
199#ifdef CONFIG_SMP
200	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
201	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
202	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
203	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
204	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
205	mcreq	p15, 0, r0, c1, c0, 1
206#endif
207	b	__v7_setup
208
209__v7_pj4b_setup:
210#ifdef CONFIG_CPU_PJ4B
211
212/* Auxiliary Debug Modes Control 1 Register */
213#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
214#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
215#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
216#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
217
218/* Auxiliary Debug Modes Control 2 Register */
219#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
220#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
221#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
222#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
223#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
224#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
225			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
226
227/* Auxiliary Functional Modes Control Register 0 */
228#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
229#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
230#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
231
232/* Auxiliary Debug Modes Control 0 Register */
233#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
234
235	/* Auxiliary Debug Modes Control 1 Register */
236	mrc	p15, 1,	r0, c15, c1, 1
237	orr     r0, r0, #PJ4B_CLEAN_LINE
238	orr     r0, r0, #PJ4B_BCK_OFF_STREX
239	orr     r0, r0, #PJ4B_INTER_PARITY
240	bic	r0, r0, #PJ4B_STATIC_BP
241	mcr	p15, 1,	r0, c15, c1, 1
242
243	/* Auxiliary Debug Modes Control 2 Register */
244	mrc	p15, 1,	r0, c15, c1, 2
245	bic	r0, r0, #PJ4B_FAST_LDR
246	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
247	mcr	p15, 1,	r0, c15, c1, 2
248
249	/* Auxiliary Functional Modes Control Register 0 */
250	mrc	p15, 1,	r0, c15, c2, 0
251#ifdef CONFIG_SMP
252	orr	r0, r0, #PJ4B_SMP_CFB
253#endif
254	orr	r0, r0, #PJ4B_L1_PAR_CHK
255	orr	r0, r0, #PJ4B_BROADCAST_CACHE
256	mcr	p15, 1,	r0, c15, c2, 0
257
258	/* Auxiliary Debug Modes Control 0 Register */
259	mrc	p15, 1,	r0, c15, c1, 0
260	orr	r0, r0, #PJ4B_WFI_WFE
261	mcr	p15, 1,	r0, c15, c1, 0
262
263#endif /* CONFIG_CPU_PJ4B */
264
265__v7_setup:
266	adr	r12, __v7_setup_stack		@ the local stack
267	stmia	r12, {r0-r5, r7, r9, r11, lr}
268	bl      v7_flush_dcache_louis
269	ldmia	r12, {r0-r5, r7, r9, r11, lr}
270
271	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
272	and	r10, r0, #0xff000000		@ ARM?
273	teq	r10, #0x41000000
274	bne	3f
275	and	r5, r0, #0x00f00000		@ variant
276	and	r6, r0, #0x0000000f		@ revision
277	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
278	ubfx	r0, r0, #4, #12			@ primary part number
279
280	/* Cortex-A8 Errata */
281	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
282	teq	r0, r10
283	bne	2f
284#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
285
286	teq	r5, #0x00100000			@ only present in r1p*
287	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
288	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
289	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
290#endif
291#ifdef CONFIG_ARM_ERRATA_458693
292	teq	r6, #0x20			@ only present in r2p0
293	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
294	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
295	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
296	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
297#endif
298#ifdef CONFIG_ARM_ERRATA_460075
299	teq	r6, #0x20			@ only present in r2p0
300	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
301	tsteq	r10, #1 << 22
302	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
303	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
304#endif
305	b	3f
306
307	/* Cortex-A9 Errata */
3082:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
309	teq	r0, r10
310	bne	3f
311#ifdef CONFIG_ARM_ERRATA_742230
312	cmp	r6, #0x22			@ only present up to r2p2
313	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
314	orrle	r10, r10, #1 << 4		@ set bit #4
315	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
316#endif
317#ifdef CONFIG_ARM_ERRATA_742231
318	teq	r6, #0x20			@ present in r2p0
319	teqne	r6, #0x21			@ present in r2p1
320	teqne	r6, #0x22			@ present in r2p2
321	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
322	orreq	r10, r10, #1 << 12		@ set bit #12
323	orreq	r10, r10, #1 << 22		@ set bit #22
324	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
325#endif
326#ifdef CONFIG_ARM_ERRATA_743622
327	teq	r5, #0x00200000			@ only present in r2p*
328	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
329	orreq	r10, r10, #1 << 6		@ set bit #6
330	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
331#endif
332#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
333	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
334	ALT_UP_B(1f)
335	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
336	orrlt	r10, r10, #1 << 11		@ set bit #11
337	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
3381:
339#endif
340
341	/* Cortex-A15 Errata */
3423:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
343	teq	r0, r10
344	bne	4f
345
346#ifdef CONFIG_ARM_ERRATA_773022
347	cmp	r6, #0x4			@ only present up to r0p4
348	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
349	orrle	r10, r10, #1 << 1		@ disable loop buffer
350	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
351#endif
352
3534:	mov	r10, #0
354	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
355#ifdef CONFIG_MMU
356	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
357	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
358	ldr	r5, =PRRR			@ PRRR
359	ldr	r6, =NMRR			@ NMRR
360	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
361	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
362#endif
363	dsb					@ Complete invalidations
364#ifndef CONFIG_ARM_THUMBEE
365	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
366	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
367	teq	r0, #(1 << 12)			@ check if ThumbEE is present
368	bne	1f
369	mov	r5, #0
370	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
371	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
372	orr	r0, r0, #1			@ set the 1st bit in order to
373	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
3741:
375#endif
376	adr	r5, v7_crval
377	ldmia	r5, {r5, r6}
378 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
379#ifdef CONFIG_SWP_EMULATE
380	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
381	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
382#endif
383   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
384	bic	r0, r0, r5			@ clear bits them
385	orr	r0, r0, r6			@ set them
386 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
387	mov	pc, lr				@ return to head.S:__ret
388ENDPROC(__v7_setup)
389
390	.align	2
391__v7_setup_stack:
392	.space	4 * 11				@ 11 registers
393
394	__INITDATA
395
396	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
397	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
398#ifdef CONFIG_CPU_PJ4B
399	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
400#endif
401
402	.section ".rodata"
403
404	string	cpu_arch_name, "armv7"
405	string	cpu_elf_name, "v7"
406	.align
407
408	.section ".proc.info.init", #alloc, #execinstr
409
410	/*
411	 * Standard v7 proc info content
412	 */
413.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
414	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
415			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
416	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
417			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
418	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
419		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
420	W(b)	\initfunc
421	.long	cpu_arch_name
422	.long	cpu_elf_name
423	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
424		HWCAP_EDSP | HWCAP_TLS | \hwcaps
425	.long	cpu_v7_name
426	.long	\proc_fns
427	.long	v7wbi_tlb_fns
428	.long	v6_user_fns
429	.long	v7_cache_fns
430.endm
431
432#ifndef CONFIG_ARM_LPAE
433	/*
434	 * ARM Ltd. Cortex A5 processor.
435	 */
436	.type   __v7_ca5mp_proc_info, #object
437__v7_ca5mp_proc_info:
438	.long	0x410fc050
439	.long	0xff0ffff0
440	__v7_proc __v7_ca5mp_setup
441	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
442
443	/*
444	 * ARM Ltd. Cortex A9 processor.
445	 */
446	.type   __v7_ca9mp_proc_info, #object
447__v7_ca9mp_proc_info:
448	.long	0x410fc090
449	.long	0xff0ffff0
450	__v7_proc __v7_ca9mp_setup
451	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
452
453#endif	/* CONFIG_ARM_LPAE */
454
455	/*
456	 * Marvell PJ4B processor.
457	 */
458#ifdef CONFIG_CPU_PJ4B
459	.type   __v7_pj4b_proc_info, #object
460__v7_pj4b_proc_info:
461	.long	0x560f5800
462	.long	0xff0fff00
463	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
464	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
465#endif
466
467	/*
468	 * ARM Ltd. Cortex R7 processor.
469	 */
470	.type	__v7_cr7mp_proc_info, #object
471__v7_cr7mp_proc_info:
472	.long	0x410fc170
473	.long	0xff0ffff0
474	__v7_proc __v7_cr7mp_setup
475	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
476
477	/*
478	 * ARM Ltd. Cortex A7 processor.
479	 */
480	.type	__v7_ca7mp_proc_info, #object
481__v7_ca7mp_proc_info:
482	.long	0x410fc070
483	.long	0xff0ffff0
484	__v7_proc __v7_ca7mp_setup
485	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
486
487	/*
488	 * ARM Ltd. Cortex A12 processor.
489	 */
490	.type	__v7_ca12mp_proc_info, #object
491__v7_ca12mp_proc_info:
492	.long	0x410fc0d0
493	.long	0xff0ffff0
494	__v7_proc __v7_ca12mp_setup
495	.size	__v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
496
497	/*
498	 * ARM Ltd. Cortex A15 processor.
499	 */
500	.type	__v7_ca15mp_proc_info, #object
501__v7_ca15mp_proc_info:
502	.long	0x410fc0f0
503	.long	0xff0ffff0
504	__v7_proc __v7_ca15mp_setup
505	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
506
507	/*
508	 * Qualcomm Inc. Krait processors.
509	 */
510	.type	__krait_proc_info, #object
511__krait_proc_info:
512	.long	0x510f0400		@ Required ID value
513	.long	0xff0ffc00		@ Mask for ID
514	/*
515	 * Some Krait processors don't indicate support for SDIV and UDIV
516	 * instructions in the ARM instruction set, even though they actually
517	 * do support them.
518	 */
519	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
520	.size	__krait_proc_info, . - __krait_proc_info
521
522	/*
523	 * Match any ARMv7 processor core.
524	 */
525	.type	__v7_proc_info, #object
526__v7_proc_info:
527	.long	0x000f0000		@ Required ID value
528	.long	0x000f0000		@ Mask for ID
529	__v7_proc __v7_setup
530	.size	__v7_proc_info, . - __v7_proc_info
531