xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision 545e4006) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <asm/asm-offsets.h>
15#include <asm/elf.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h>
18
19#include "proc-macros.S"
20
21#define TTB_C		(1 << 0)
22#define TTB_S		(1 << 1)
23#define TTB_RGN_OC_WT	(2 << 3)
24#define TTB_RGN_OC_WB	(3 << 3)
25
26ENTRY(cpu_v7_proc_init)
27	mov	pc, lr
28
29ENTRY(cpu_v7_proc_fin)
30	mov	pc, lr
31
32/*
33 *	cpu_v7_reset(loc)
34 *
35 *	Perform a soft reset of the system.  Put the CPU into the
36 *	same state as it would be if it had been reset, and branch
37 *	to what would be the reset vector.
38 *
39 *	- loc   - location to jump to for soft reset
40 *
41 *	It is assumed that:
42 */
43	.align	5
44ENTRY(cpu_v7_reset)
45	mov	pc, r0
46
47/*
48 *	cpu_v7_do_idle()
49 *
50 *	Idle the processor (eg, wait for interrupt).
51 *
52 *	IRQs are already disabled.
53 */
54ENTRY(cpu_v7_do_idle)
55	.long	0xe320f003			@ ARM V7 WFI instruction
56	mov	pc, lr
57
58ENTRY(cpu_v7_dcache_clean_area)
59#ifndef TLB_CAN_READ_FROM_L1_CACHE
60	dcache_line_size r2, r3
611:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
62	add	r0, r0, r2
63	subs	r1, r1, r2
64	bhi	1b
65	dsb
66#endif
67	mov	pc, lr
68
69/*
70 *	cpu_v7_switch_mm(pgd_phys, tsk)
71 *
72 *	Set the translation table base pointer to be pgd_phys
73 *
74 *	- pgd_phys - physical address of new TTB
75 *
76 *	It is assumed that:
77 *	- we are not using split page tables
78 */
79ENTRY(cpu_v7_switch_mm)
80#ifdef CONFIG_MMU
81	mov	r2, #0
82	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
83	orr	r0, r0, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB
84	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
85	isb
861:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
87	isb
88	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
89	isb
90#endif
91	mov	pc, lr
92
93/*
94 *	cpu_v7_set_pte_ext(ptep, pte)
95 *
96 *	Set a level 2 translation table entry.
97 *
98 *	- ptep  - pointer to level 2 translation table entry
99 *		  (hardware version is stored at -1024 bytes)
100 *	- pte   - PTE value to store
101 *	- ext	- value for extended PTE bits
102 *
103 *	Permissions:
104 *	  YUWD  APX AP1 AP0	SVC	User
105 *	  0xxx   0   0   0	no acc	no acc
106 *	  100x   1   0   1	r/o	no acc
107 *	  10x0   1   0   1	r/o	no acc
108 *	  1011   0   0   1	r/w	no acc
109 *	  110x   0   1   0	r/w	r/o
110 *	  11x0   0   1   0	r/w	r/o
111 *	  1111   0   1   1	r/w	r/w
112 */
113ENTRY(cpu_v7_set_pte_ext)
114#ifdef CONFIG_MMU
115	str	r1, [r0], #-2048		@ linux version
116
117	bic	r3, r1, #0x000003f0
118	bic	r3, r3, #0x00000003
119	orr	r3, r3, r2
120	orr	r3, r3, #PTE_EXT_AP0 | 2
121
122	tst	r1, #L_PTE_WRITE
123	tstne	r1, #L_PTE_DIRTY
124	orreq	r3, r3, #PTE_EXT_APX
125
126	tst	r1, #L_PTE_USER
127	orrne	r3, r3, #PTE_EXT_AP1
128	tstne	r3, #PTE_EXT_APX
129	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
130
131	tst	r1, #L_PTE_YOUNG
132	biceq	r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
133
134	tst	r1, #L_PTE_EXEC
135	orreq	r3, r3, #PTE_EXT_XN
136
137	tst	r1, #L_PTE_PRESENT
138	moveq	r3, #0
139
140	str	r3, [r0]
141	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
142#endif
143	mov	pc, lr
144
145cpu_v7_name:
146	.ascii	"ARMv7 Processor"
147	.align
148
149	.section ".text.init", #alloc, #execinstr
150
151/*
152 *	__v7_setup
153 *
154 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
155 *	on.  Return in r0 the new CP15 C1 control register setting.
156 *
157 *	We automatically detect if we have a Harvard cache, and use the
158 *	Harvard cache control instructions insead of the unified cache
159 *	control instructions.
160 *
161 *	This should be able to cover all ARMv7 cores.
162 *
163 *	It is assumed that:
164 *	- cache type register is implemented
165 */
166__v7_setup:
167	adr	r12, __v7_setup_stack		@ the local stack
168	stmia	r12, {r0-r5, r7, r9, r11, lr}
169	bl	v7_flush_dcache_all
170	ldmia	r12, {r0-r5, r7, r9, r11, lr}
171	mov	r10, #0
172#ifdef HARVARD_CACHE
173	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
174#endif
175	dsb
176#ifdef CONFIG_MMU
177	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
178	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
179	orr	r4, r4, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB
180	mcr	p15, 0, r4, c2, c0, 0		@ load TTB0
181	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
182	mov	r10, #0x1f			@ domains 0, 1 = manager
183	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
184#endif
185	adr	r5, v7_crval
186	ldmia	r5, {r5, r6}
187   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
188	bic	r0, r0, r5			@ clear bits them
189	orr	r0, r0, r6			@ set them
190	mov	pc, lr				@ return to head.S:__ret
191
192	/*
193	 *         V X F   I D LR
194	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
195	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
196	 *         0 110       0011 1.00 .111 1101 < we want
197	 */
198	.type	v7_crval, #object
199v7_crval:
200	crval	clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
201
202__v7_setup_stack:
203	.space	4 * 11				@ 11 registers
204
205	.type	v7_processor_functions, #object
206ENTRY(v7_processor_functions)
207	.word	v7_early_abort
208	.word	pabort_ifar
209	.word	cpu_v7_proc_init
210	.word	cpu_v7_proc_fin
211	.word	cpu_v7_reset
212	.word	cpu_v7_do_idle
213	.word	cpu_v7_dcache_clean_area
214	.word	cpu_v7_switch_mm
215	.word	cpu_v7_set_pte_ext
216	.size	v7_processor_functions, . - v7_processor_functions
217
218	.type	cpu_arch_name, #object
219cpu_arch_name:
220	.asciz	"armv7"
221	.size	cpu_arch_name, . - cpu_arch_name
222
223	.type	cpu_elf_name, #object
224cpu_elf_name:
225	.asciz	"v7"
226	.size	cpu_elf_name, . - cpu_elf_name
227	.align
228
229	.section ".proc.info.init", #alloc, #execinstr
230
231	/*
232	 * Match any ARMv7 processor core.
233	 */
234	.type	__v7_proc_info, #object
235__v7_proc_info:
236	.long	0x000f0000		@ Required ID value
237	.long	0x000f0000		@ Mask for ID
238	.long   PMD_TYPE_SECT | \
239		PMD_SECT_BUFFERABLE | \
240		PMD_SECT_CACHEABLE | \
241		PMD_SECT_AP_WRITE | \
242		PMD_SECT_AP_READ
243	.long   PMD_TYPE_SECT | \
244		PMD_SECT_XN | \
245		PMD_SECT_AP_WRITE | \
246		PMD_SECT_AP_READ
247	b	__v7_setup
248	.long	cpu_arch_name
249	.long	cpu_elf_name
250	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
251	.long	cpu_v7_name
252	.long	v7_processor_functions
253	.long	v7wbi_tlb_fns
254	.long	v6_user_fns
255	.long	v7_cache_fns
256	.size	__v7_proc_info, . - __v7_proc_info
257