xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision 5104d265) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#ifdef CONFIG_ARM_LPAE
23#include "proc-v7-3level.S"
24#else
25#include "proc-v7-2level.S"
26#endif
27
28ENTRY(cpu_v7_proc_init)
29	mov	pc, lr
30ENDPROC(cpu_v7_proc_init)
31
32ENTRY(cpu_v7_proc_fin)
33	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
34	bic	r0, r0, #0x1000			@ ...i............
35	bic	r0, r0, #0x0006			@ .............ca.
36	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37	mov	pc, lr
38ENDPROC(cpu_v7_proc_fin)
39
40/*
41 *	cpu_v7_reset(loc)
42 *
43 *	Perform a soft reset of the system.  Put the CPU into the
44 *	same state as it would be if it had been reset, and branch
45 *	to what would be the reset vector.
46 *
47 *	- loc   - location to jump to for soft reset
48 *
49 *	This code must be executed using a flat identity mapping with
50 *      caches disabled.
51 */
52	.align	5
53	.pushsection	.idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
56	bic	r1, r1, #0x1			@ ...............m
57 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
59	isb
60	bx	r0
61ENDPROC(cpu_v7_reset)
62	.popsection
63
64/*
65 *	cpu_v7_do_idle()
66 *
67 *	Idle the processor (eg, wait for interrupt).
68 *
69 *	IRQs are already disabled.
70 */
71ENTRY(cpu_v7_do_idle)
72	dsb					@ WFI may enter a low-power mode
73	wfi
74	mov	pc, lr
75ENDPROC(cpu_v7_do_idle)
76
77ENTRY(cpu_v7_dcache_clean_area)
78	ALT_SMP(mov	pc, lr)			@ MP extensions imply L1 PTW
79	ALT_UP(W(nop))
80	dcache_line_size r2, r3
811:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
82	add	r0, r0, r2
83	subs	r1, r1, r2
84	bhi	1b
85	dsb
86	mov	pc, lr
87ENDPROC(cpu_v7_dcache_clean_area)
88
89	string	cpu_v7_name, "ARMv7 Processor"
90	.align
91
92/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93.globl	cpu_v7_suspend_size
94.equ	cpu_v7_suspend_size, 4 * 8
95#ifdef CONFIG_ARM_CPU_SUSPEND
96ENTRY(cpu_v7_do_suspend)
97	stmfd	sp!, {r4 - r10, lr}
98	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
99	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
100	stmia	r0!, {r4 - r5}
101#ifdef CONFIG_MMU
102	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
103	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
104	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
105#endif
106	mrc	p15, 0, r8, c1, c0, 0	@ Control register
107	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
108	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
109	stmia	r0, {r6 - r11}
110	ldmfd	sp!, {r4 - r10, pc}
111ENDPROC(cpu_v7_do_suspend)
112
113ENTRY(cpu_v7_do_resume)
114	mov	ip, #0
115	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
116	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
117	ldmia	r0!, {r4 - r5}
118	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
119	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
120	ldmia	r0, {r6 - r11}
121#ifdef CONFIG_MMU
122	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
123	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
124#ifndef CONFIG_ARM_LPAE
125	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
126	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
127#endif
128	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
129	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
130	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
131	ldr	r4, =PRRR		@ PRRR
132	ldr	r5, =NMRR		@ NMRR
133	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
134	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
135#endif	/* CONFIG_MMU */
136	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
137	teq	r4, r9			@ Is it already set?
138	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
139	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
140	isb
141	dsb
142	mov	r0, r8			@ control register
143	b	cpu_resume_mmu
144ENDPROC(cpu_v7_do_resume)
145#endif
146
147#ifdef CONFIG_CPU_PJ4B
148	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
149	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
150	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
151	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
152	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
153#ifdef CONFIG_PJ4B_ERRATA_4742
154ENTRY(cpu_pj4b_do_idle)
155	dsb					@ WFI may enter a low-power mode
156	wfi
157	dsb					@barrier
158	mov	pc, lr
159ENDPROC(cpu_pj4b_do_idle)
160#else
161	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
162#endif
163	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
164	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
165	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
166	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size
167
168#endif
169
170/*
171 *	__v7_setup
172 *
173 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
174 *	on.  Return in r0 the new CP15 C1 control register setting.
175 *
176 *	This should be able to cover all ARMv7 cores.
177 *
178 *	It is assumed that:
179 *	- cache type register is implemented
180 */
181__v7_ca5mp_setup:
182__v7_ca9mp_setup:
183__v7_cr7mp_setup:
184	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
185	b	1f
186__v7_ca7mp_setup:
187__v7_ca15mp_setup:
188	mov	r10, #0
1891:
190#ifdef CONFIG_SMP
191	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
192	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
193	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
194	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
195	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
196	mcreq	p15, 0, r0, c1, c0, 1
197#endif
198	b	__v7_setup
199
200__v7_pj4b_setup:
201#ifdef CONFIG_CPU_PJ4B
202
203/* Auxiliary Debug Modes Control 1 Register */
204#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
205#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
206#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
207#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
208
209/* Auxiliary Debug Modes Control 2 Register */
210#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
211#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
212#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
213#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
214#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
215#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
216			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
217
218/* Auxiliary Functional Modes Control Register 0 */
219#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
220#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
221#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
222
223/* Auxiliary Debug Modes Control 0 Register */
224#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
225
226	/* Auxiliary Debug Modes Control 1 Register */
227	mrc	p15, 1,	r0, c15, c1, 1
228	orr     r0, r0, #PJ4B_CLEAN_LINE
229	orr     r0, r0, #PJ4B_BCK_OFF_STREX
230	orr     r0, r0, #PJ4B_INTER_PARITY
231	bic	r0, r0, #PJ4B_STATIC_BP
232	mcr	p15, 1,	r0, c15, c1, 1
233
234	/* Auxiliary Debug Modes Control 2 Register */
235	mrc	p15, 1,	r0, c15, c1, 2
236	bic	r0, r0, #PJ4B_FAST_LDR
237	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
238	mcr	p15, 1,	r0, c15, c1, 2
239
240	/* Auxiliary Functional Modes Control Register 0 */
241	mrc	p15, 1,	r0, c15, c2, 0
242#ifdef CONFIG_SMP
243	orr	r0, r0, #PJ4B_SMP_CFB
244#endif
245	orr	r0, r0, #PJ4B_L1_PAR_CHK
246	orr	r0, r0, #PJ4B_BROADCAST_CACHE
247	mcr	p15, 1,	r0, c15, c2, 0
248
249	/* Auxiliary Debug Modes Control 0 Register */
250	mrc	p15, 1,	r0, c15, c1, 0
251	orr	r0, r0, #PJ4B_WFI_WFE
252	mcr	p15, 1,	r0, c15, c1, 0
253
254#endif /* CONFIG_CPU_PJ4B */
255
256__v7_setup:
257	adr	r12, __v7_setup_stack		@ the local stack
258	stmia	r12, {r0-r5, r7, r9, r11, lr}
259	bl      v7_flush_dcache_louis
260	ldmia	r12, {r0-r5, r7, r9, r11, lr}
261
262	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
263	and	r10, r0, #0xff000000		@ ARM?
264	teq	r10, #0x41000000
265	bne	3f
266	and	r5, r0, #0x00f00000		@ variant
267	and	r6, r0, #0x0000000f		@ revision
268	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
269	ubfx	r0, r0, #4, #12			@ primary part number
270
271	/* Cortex-A8 Errata */
272	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
273	teq	r0, r10
274	bne	2f
275#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
276
277	teq	r5, #0x00100000			@ only present in r1p*
278	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
279	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
280	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
281#endif
282#ifdef CONFIG_ARM_ERRATA_458693
283	teq	r6, #0x20			@ only present in r2p0
284	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
285	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
286	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
287	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
288#endif
289#ifdef CONFIG_ARM_ERRATA_460075
290	teq	r6, #0x20			@ only present in r2p0
291	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
292	tsteq	r10, #1 << 22
293	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
294	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
295#endif
296	b	3f
297
298	/* Cortex-A9 Errata */
2992:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
300	teq	r0, r10
301	bne	3f
302#ifdef CONFIG_ARM_ERRATA_742230
303	cmp	r6, #0x22			@ only present up to r2p2
304	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
305	orrle	r10, r10, #1 << 4		@ set bit #4
306	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
307#endif
308#ifdef CONFIG_ARM_ERRATA_742231
309	teq	r6, #0x20			@ present in r2p0
310	teqne	r6, #0x21			@ present in r2p1
311	teqne	r6, #0x22			@ present in r2p2
312	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
313	orreq	r10, r10, #1 << 12		@ set bit #12
314	orreq	r10, r10, #1 << 22		@ set bit #22
315	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
316#endif
317#ifdef CONFIG_ARM_ERRATA_743622
318	teq	r5, #0x00200000			@ only present in r2p*
319	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
320	orreq	r10, r10, #1 << 6		@ set bit #6
321	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
322#endif
323#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
324	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
325	ALT_UP_B(1f)
326	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
327	orrlt	r10, r10, #1 << 11		@ set bit #11
328	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
3291:
330#endif
331
3323:	mov	r10, #0
333	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
334	dsb
335#ifdef CONFIG_MMU
336	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
337	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
338	ldr	r5, =PRRR			@ PRRR
339	ldr	r6, =NMRR			@ NMRR
340	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
341	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
342#endif
343#ifndef CONFIG_ARM_THUMBEE
344	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
345	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
346	teq	r0, #(1 << 12)			@ check if ThumbEE is present
347	bne	1f
348	mov	r5, #0
349	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
350	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
351	orr	r0, r0, #1			@ set the 1st bit in order to
352	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
3531:
354#endif
355	adr	r5, v7_crval
356	ldmia	r5, {r5, r6}
357#ifdef CONFIG_CPU_ENDIAN_BE8
358	orr	r6, r6, #1 << 25		@ big-endian page tables
359#endif
360#ifdef CONFIG_SWP_EMULATE
361	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
362	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
363#endif
364   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
365	bic	r0, r0, r5			@ clear bits them
366	orr	r0, r0, r6			@ set them
367 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
368	mov	pc, lr				@ return to head.S:__ret
369ENDPROC(__v7_setup)
370
371	.align	2
372__v7_setup_stack:
373	.space	4 * 11				@ 11 registers
374
375	__INITDATA
376
377	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
378	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
379#ifdef CONFIG_CPU_PJ4B
380	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
381#endif
382
383	.section ".rodata"
384
385	string	cpu_arch_name, "armv7"
386	string	cpu_elf_name, "v7"
387	.align
388
389	.section ".proc.info.init", #alloc, #execinstr
390
391	/*
392	 * Standard v7 proc info content
393	 */
394.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
395	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
396			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
397	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
398			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
399	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
400		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
401	W(b)	\initfunc
402	.long	cpu_arch_name
403	.long	cpu_elf_name
404	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
405		HWCAP_EDSP | HWCAP_TLS | \hwcaps
406	.long	cpu_v7_name
407	.long	\proc_fns
408	.long	v7wbi_tlb_fns
409	.long	v6_user_fns
410	.long	v7_cache_fns
411.endm
412
413#ifndef CONFIG_ARM_LPAE
414	/*
415	 * ARM Ltd. Cortex A5 processor.
416	 */
417	.type   __v7_ca5mp_proc_info, #object
418__v7_ca5mp_proc_info:
419	.long	0x410fc050
420	.long	0xff0ffff0
421	__v7_proc __v7_ca5mp_setup
422	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
423
424	/*
425	 * ARM Ltd. Cortex A9 processor.
426	 */
427	.type   __v7_ca9mp_proc_info, #object
428__v7_ca9mp_proc_info:
429	.long	0x410fc090
430	.long	0xff0ffff0
431	__v7_proc __v7_ca9mp_setup
432	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
433
434#endif	/* CONFIG_ARM_LPAE */
435
436	/*
437	 * Marvell PJ4B processor.
438	 */
439#ifdef CONFIG_CPU_PJ4B
440	.type   __v7_pj4b_proc_info, #object
441__v7_pj4b_proc_info:
442	.long	0x560f5800
443	.long	0xff0fff00
444	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
445	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
446#endif
447
448	/*
449	 * ARM Ltd. Cortex R7 processor.
450	 */
451	.type	__v7_cr7mp_proc_info, #object
452__v7_cr7mp_proc_info:
453	.long	0x410fc170
454	.long	0xff0ffff0
455	__v7_proc __v7_cr7mp_setup
456	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
457
458	/*
459	 * ARM Ltd. Cortex A7 processor.
460	 */
461	.type	__v7_ca7mp_proc_info, #object
462__v7_ca7mp_proc_info:
463	.long	0x410fc070
464	.long	0xff0ffff0
465	__v7_proc __v7_ca7mp_setup
466	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
467
468	/*
469	 * ARM Ltd. Cortex A15 processor.
470	 */
471	.type	__v7_ca15mp_proc_info, #object
472__v7_ca15mp_proc_info:
473	.long	0x410fc0f0
474	.long	0xff0ffff0
475	__v7_proc __v7_ca15mp_setup
476	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
477
478	/*
479	 * Qualcomm Inc. Krait processors.
480	 */
481	.type	__krait_proc_info, #object
482__krait_proc_info:
483	.long	0x510f0400		@ Required ID value
484	.long	0xff0ffc00		@ Mask for ID
485	/*
486	 * Some Krait processors don't indicate support for SDIV and UDIV
487	 * instructions in the ARM instruction set, even though they actually
488	 * do support them.
489	 */
490	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
491	.size	__krait_proc_info, . - __krait_proc_info
492
493	/*
494	 * Match any ARMv7 processor core.
495	 */
496	.type	__v7_proc_info, #object
497__v7_proc_info:
498	.long	0x000f0000		@ Required ID value
499	.long	0x000f0000		@ Mask for ID
500	__v7_proc __v7_setup
501	.size	__v7_proc_info, . - __v7_proc_info
502