xref: /openbmc/linux/arch/arm/mm/proc-v7.S (revision 4800cd83) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#define TTB_S		(1 << 1)
23#define TTB_RGN_NC	(0 << 3)
24#define TTB_RGN_OC_WBWA	(1 << 3)
25#define TTB_RGN_OC_WT	(2 << 3)
26#define TTB_RGN_OC_WB	(3 << 3)
27#define TTB_NOS		(1 << 5)
28#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
32
33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
35#define PMD_FLAGS_UP	PMD_SECT_WB
36
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
40
41ENTRY(cpu_v7_proc_init)
42	mov	pc, lr
43ENDPROC(cpu_v7_proc_init)
44
45ENTRY(cpu_v7_proc_fin)
46	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
47	bic	r0, r0, #0x1000			@ ...i............
48	bic	r0, r0, #0x0006			@ .............ca.
49	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
50	mov	pc, lr
51ENDPROC(cpu_v7_proc_fin)
52
53/*
54 *	cpu_v7_reset(loc)
55 *
56 *	Perform a soft reset of the system.  Put the CPU into the
57 *	same state as it would be if it had been reset, and branch
58 *	to what would be the reset vector.
59 *
60 *	- loc   - location to jump to for soft reset
61 */
62	.align	5
63ENTRY(cpu_v7_reset)
64	mov	pc, r0
65ENDPROC(cpu_v7_reset)
66
67/*
68 *	cpu_v7_do_idle()
69 *
70 *	Idle the processor (eg, wait for interrupt).
71 *
72 *	IRQs are already disabled.
73 */
74ENTRY(cpu_v7_do_idle)
75	dsb					@ WFI may enter a low-power mode
76	wfi
77	mov	pc, lr
78ENDPROC(cpu_v7_do_idle)
79
80ENTRY(cpu_v7_dcache_clean_area)
81#ifndef TLB_CAN_READ_FROM_L1_CACHE
82	dcache_line_size r2, r3
831:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
84	add	r0, r0, r2
85	subs	r1, r1, r2
86	bhi	1b
87	dsb
88#endif
89	mov	pc, lr
90ENDPROC(cpu_v7_dcache_clean_area)
91
92/*
93 *	cpu_v7_switch_mm(pgd_phys, tsk)
94 *
95 *	Set the translation table base pointer to be pgd_phys
96 *
97 *	- pgd_phys - physical address of new TTB
98 *
99 *	It is assumed that:
100 *	- we are not using split page tables
101 */
102ENTRY(cpu_v7_switch_mm)
103#ifdef CONFIG_MMU
104	mov	r2, #0
105	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
106	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
107	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
108#ifdef CONFIG_ARM_ERRATA_430973
109	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
110#endif
111	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
112	isb
1131:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
114	isb
115	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
116	isb
117#endif
118	mov	pc, lr
119ENDPROC(cpu_v7_switch_mm)
120
121/*
122 *	cpu_v7_set_pte_ext(ptep, pte)
123 *
124 *	Set a level 2 translation table entry.
125 *
126 *	- ptep  - pointer to level 2 translation table entry
127 *		  (hardware version is stored at +2048 bytes)
128 *	- pte   - PTE value to store
129 *	- ext	- value for extended PTE bits
130 */
131ENTRY(cpu_v7_set_pte_ext)
132#ifdef CONFIG_MMU
133	str	r1, [r0]			@ linux version
134
135	bic	r3, r1, #0x000003f0
136	bic	r3, r3, #PTE_TYPE_MASK
137	orr	r3, r3, r2
138	orr	r3, r3, #PTE_EXT_AP0 | 2
139
140	tst	r1, #1 << 4
141	orrne	r3, r3, #PTE_EXT_TEX(1)
142
143	eor	r1, r1, #L_PTE_DIRTY
144	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
145	orrne	r3, r3, #PTE_EXT_APX
146
147	tst	r1, #L_PTE_USER
148	orrne	r3, r3, #PTE_EXT_AP1
149#ifdef CONFIG_CPU_USE_DOMAINS
150	@ allow kernel read/write access to read-only user pages
151	tstne	r3, #PTE_EXT_APX
152	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
153#endif
154
155	tst	r1, #L_PTE_XN
156	orrne	r3, r3, #PTE_EXT_XN
157
158	tst	r1, #L_PTE_YOUNG
159	tstne	r1, #L_PTE_PRESENT
160	moveq	r3, #0
161
162 ARM(	str	r3, [r0, #2048]! )
163 THUMB(	add	r0, r0, #2048 )
164 THUMB(	str	r3, [r0] )
165	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
166#endif
167	mov	pc, lr
168ENDPROC(cpu_v7_set_pte_ext)
169
170cpu_v7_name:
171	.ascii	"ARMv7 Processor"
172	.align
173
174	__CPUINIT
175
176/*
177 *	__v7_setup
178 *
179 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
180 *	on.  Return in r0 the new CP15 C1 control register setting.
181 *
182 *	We automatically detect if we have a Harvard cache, and use the
183 *	Harvard cache control instructions insead of the unified cache
184 *	control instructions.
185 *
186 *	This should be able to cover all ARMv7 cores.
187 *
188 *	It is assumed that:
189 *	- cache type register is implemented
190 */
191__v7_ca9mp_setup:
192#ifdef CONFIG_SMP
193	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
194	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
195	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
196	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
197	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
198#endif
199__v7_setup:
200	adr	r12, __v7_setup_stack		@ the local stack
201	stmia	r12, {r0-r5, r7, r9, r11, lr}
202	bl	v7_flush_dcache_all
203	ldmia	r12, {r0-r5, r7, r9, r11, lr}
204
205	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
206	and	r10, r0, #0xff000000		@ ARM?
207	teq	r10, #0x41000000
208	bne	3f
209	and	r5, r0, #0x00f00000		@ variant
210	and	r6, r0, #0x0000000f		@ revision
211	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
212	ubfx	r0, r0, #4, #12			@ primary part number
213
214	/* Cortex-A8 Errata */
215	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
216	teq	r0, r10
217	bne	2f
218#ifdef CONFIG_ARM_ERRATA_430973
219	teq	r5, #0x00100000			@ only present in r1p*
220	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
221	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
222	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
223#endif
224#ifdef CONFIG_ARM_ERRATA_458693
225	teq	r6, #0x20			@ only present in r2p0
226	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
227	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
228	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
229	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
230#endif
231#ifdef CONFIG_ARM_ERRATA_460075
232	teq	r6, #0x20			@ only present in r2p0
233	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
234	tsteq	r10, #1 << 22
235	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
236	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
237#endif
238	b	3f
239
240	/* Cortex-A9 Errata */
2412:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
242	teq	r0, r10
243	bne	3f
244#ifdef CONFIG_ARM_ERRATA_742230
245	cmp	r6, #0x22			@ only present up to r2p2
246	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
247	orrle	r10, r10, #1 << 4		@ set bit #4
248	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
249#endif
250#ifdef CONFIG_ARM_ERRATA_742231
251	teq	r6, #0x20			@ present in r2p0
252	teqne	r6, #0x21			@ present in r2p1
253	teqne	r6, #0x22			@ present in r2p2
254	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
255	orreq	r10, r10, #1 << 12		@ set bit #12
256	orreq	r10, r10, #1 << 22		@ set bit #22
257	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
258#endif
259#ifdef CONFIG_ARM_ERRATA_743622
260	teq	r6, #0x20			@ present in r2p0
261	teqne	r6, #0x21			@ present in r2p1
262	teqne	r6, #0x22			@ present in r2p2
263	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
264	orreq	r10, r10, #1 << 6		@ set bit #6
265	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
266#endif
267#ifdef CONFIG_ARM_ERRATA_751472
268	cmp	r6, #0x30			@ present prior to r3p0
269	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
270	orrlt	r10, r10, #1 << 11		@ set bit #11
271	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
272#endif
273
2743:	mov	r10, #0
275#ifdef HARVARD_CACHE
276	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
277#endif
278	dsb
279#ifdef CONFIG_MMU
280	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
281	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
282	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
283	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
284	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
285	/*
286	 * Memory region attributes with SCTLR.TRE=1
287	 *
288	 *   n = TEX[0],C,B
289	 *   TR = PRRR[2n+1:2n]		- memory type
290	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
291	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
292	 *
293	 *			n	TR	IR	OR
294	 *   UNCACHED		000	00
295	 *   BUFFERABLE		001	10	00	00
296	 *   WRITETHROUGH	010	10	10	10
297	 *   WRITEBACK		011	10	11	11
298	 *   reserved		110
299	 *   WRITEALLOC		111	10	01	01
300	 *   DEV_SHARED		100	01
301	 *   DEV_NONSHARED	100	01
302	 *   DEV_WC		001	10
303	 *   DEV_CACHED		011	10
304	 *
305	 * Other attributes:
306	 *
307	 *   DS0 = PRRR[16] = 0		- device shareable property
308	 *   DS1 = PRRR[17] = 1		- device shareable property
309	 *   NS0 = PRRR[18] = 0		- normal shareable property
310	 *   NS1 = PRRR[19] = 1		- normal shareable property
311	 *   NOS = PRRR[24+n] = 1	- not outer shareable
312	 */
313	ldr	r5, =0xff0a81a8			@ PRRR
314	ldr	r6, =0x40e040e0			@ NMRR
315	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
316	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
317#endif
318	adr	r5, v7_crval
319	ldmia	r5, {r5, r6}
320#ifdef CONFIG_CPU_ENDIAN_BE8
321	orr	r6, r6, #1 << 25		@ big-endian page tables
322#endif
323#ifdef CONFIG_SWP_EMULATE
324	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
325	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
326#endif
327   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
328	bic	r0, r0, r5			@ clear bits them
329	orr	r0, r0, r6			@ set them
330 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
331	mov	pc, lr				@ return to head.S:__ret
332ENDPROC(__v7_setup)
333
334	/*   AT
335	 *  TFR   EV X F   I D LR    S
336	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
337	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
338	 *    1    0 110       0011 1100 .111 1101 < we want
339	 */
340	.type	v7_crval, #object
341v7_crval:
342	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
343
344__v7_setup_stack:
345	.space	4 * 11				@ 11 registers
346
347	__INITDATA
348
349	.type	v7_processor_functions, #object
350ENTRY(v7_processor_functions)
351	.word	v7_early_abort
352	.word	v7_pabort
353	.word	cpu_v7_proc_init
354	.word	cpu_v7_proc_fin
355	.word	cpu_v7_reset
356	.word	cpu_v7_do_idle
357	.word	cpu_v7_dcache_clean_area
358	.word	cpu_v7_switch_mm
359	.word	cpu_v7_set_pte_ext
360	.size	v7_processor_functions, . - v7_processor_functions
361
362	.section ".rodata"
363
364	.type	cpu_arch_name, #object
365cpu_arch_name:
366	.asciz	"armv7"
367	.size	cpu_arch_name, . - cpu_arch_name
368
369	.type	cpu_elf_name, #object
370cpu_elf_name:
371	.asciz	"v7"
372	.size	cpu_elf_name, . - cpu_elf_name
373	.align
374
375	.section ".proc.info.init", #alloc, #execinstr
376
377	.type   __v7_ca9mp_proc_info, #object
378__v7_ca9mp_proc_info:
379	.long	0x410fc090		@ Required ID value
380	.long	0xff0ffff0		@ Mask for ID
381	ALT_SMP(.long \
382		PMD_TYPE_SECT | \
383		PMD_SECT_AP_WRITE | \
384		PMD_SECT_AP_READ | \
385		PMD_FLAGS_SMP)
386	ALT_UP(.long \
387		PMD_TYPE_SECT | \
388		PMD_SECT_AP_WRITE | \
389		PMD_SECT_AP_READ | \
390		PMD_FLAGS_UP)
391	.long   PMD_TYPE_SECT | \
392		PMD_SECT_XN | \
393		PMD_SECT_AP_WRITE | \
394		PMD_SECT_AP_READ
395	W(b)	__v7_ca9mp_setup
396	.long	cpu_arch_name
397	.long	cpu_elf_name
398	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
399	.long	cpu_v7_name
400	.long	v7_processor_functions
401	.long	v7wbi_tlb_fns
402	.long	v6_user_fns
403	.long	v7_cache_fns
404	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
405
406	/*
407	 * Match any ARMv7 processor core.
408	 */
409	.type	__v7_proc_info, #object
410__v7_proc_info:
411	.long	0x000f0000		@ Required ID value
412	.long	0x000f0000		@ Mask for ID
413	ALT_SMP(.long \
414		PMD_TYPE_SECT | \
415		PMD_SECT_AP_WRITE | \
416		PMD_SECT_AP_READ | \
417		PMD_FLAGS_SMP)
418	ALT_UP(.long \
419		PMD_TYPE_SECT | \
420		PMD_SECT_AP_WRITE | \
421		PMD_SECT_AP_READ | \
422		PMD_FLAGS_UP)
423	.long   PMD_TYPE_SECT | \
424		PMD_SECT_XN | \
425		PMD_SECT_AP_WRITE | \
426		PMD_SECT_AP_READ
427	W(b)	__v7_setup
428	.long	cpu_arch_name
429	.long	cpu_elf_name
430	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
431	.long	cpu_v7_name
432	.long	v7_processor_functions
433	.long	v7wbi_tlb_fns
434	.long	v6_user_fns
435	.long	v7_cache_fns
436	.size	__v7_proc_info, . - __v7_proc_info
437