1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv7 processor support. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable.h> 19 20#include "proc-macros.S" 21 22#ifdef CONFIG_ARM_LPAE 23#include "proc-v7-3level.S" 24#else 25#include "proc-v7-2level.S" 26#endif 27 28ENTRY(cpu_v7_proc_init) 29 ret lr 30ENDPROC(cpu_v7_proc_init) 31 32ENTRY(cpu_v7_proc_fin) 33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 34 bic r0, r0, #0x1000 @ ...i............ 35 bic r0, r0, #0x0006 @ .............ca. 36 mcr p15, 0, r0, c1, c0, 0 @ disable caches 37 ret lr 38ENDPROC(cpu_v7_proc_fin) 39 40/* 41 * cpu_v7_reset(loc) 42 * 43 * Perform a soft reset of the system. Put the CPU into the 44 * same state as it would be if it had been reset, and branch 45 * to what would be the reset vector. 46 * 47 * - loc - location to jump to for soft reset 48 * 49 * This code must be executed using a flat identity mapping with 50 * caches disabled. 51 */ 52 .align 5 53 .pushsection .idmap.text, "ax" 54ENTRY(cpu_v7_reset) 55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 56 bic r1, r1, #0x1 @ ...............m 57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 59 isb 60 bx r0 61ENDPROC(cpu_v7_reset) 62 .popsection 63 64/* 65 * cpu_v7_do_idle() 66 * 67 * Idle the processor (eg, wait for interrupt). 68 * 69 * IRQs are already disabled. 70 */ 71ENTRY(cpu_v7_do_idle) 72 dsb @ WFI may enter a low-power mode 73 wfi 74 ret lr 75ENDPROC(cpu_v7_do_idle) 76 77ENTRY(cpu_v7_dcache_clean_area) 78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW 79 ALT_UP_B(1f) 80 ret lr 811: dcache_line_size r2, r3 822: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 83 add r0, r0, r2 84 subs r1, r1, r2 85 bhi 2b 86 dsb ishst 87 ret lr 88ENDPROC(cpu_v7_dcache_clean_area) 89 90 string cpu_v7_name, "ARMv7 Processor" 91 .align 92 93/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 94.globl cpu_v7_suspend_size 95.equ cpu_v7_suspend_size, 4 * 9 96#ifdef CONFIG_ARM_CPU_SUSPEND 97ENTRY(cpu_v7_do_suspend) 98 stmfd sp!, {r4 - r10, lr} 99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 101 stmia r0!, {r4 - r5} 102#ifdef CONFIG_MMU 103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 104#ifdef CONFIG_ARM_LPAE 105 mrrc p15, 1, r5, r7, c2 @ TTB 1 106#else 107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1 108#endif 109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register 110#endif 111 mrc p15, 0, r8, c1, c0, 0 @ Control register 112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register 113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control 114 stmia r0, {r5 - r11} 115 ldmfd sp!, {r4 - r10, pc} 116ENDPROC(cpu_v7_do_suspend) 117 118ENTRY(cpu_v7_do_resume) 119 mov ip, #0 120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 122 ldmia r0!, {r4 - r5} 123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 125 ldmia r0, {r5 - r11} 126#ifdef CONFIG_MMU 127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 129#ifdef CONFIG_ARM_LPAE 130 mcrr p15, 0, r1, ip, c2 @ TTB 0 131 mcrr p15, 1, r5, r7, c2 @ TTB 1 132#else 133 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 134 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0 136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1 137#endif 138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register 139 ldr r4, =PRRR @ PRRR 140 ldr r5, =NMRR @ NMRR 141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 143#endif /* CONFIG_MMU */ 144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 145 teq r4, r9 @ Is it already set? 146 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it 147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 148 isb 149 dsb 150 mov r0, r8 @ control register 151 b cpu_resume_mmu 152ENDPROC(cpu_v7_do_resume) 153#endif 154 155/* 156 * Cortex-A8 157 */ 158 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init 159 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin 160 globl_equ cpu_ca8_reset, cpu_v7_reset 161 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle 162 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area 163 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext 164 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size 165#ifdef CONFIG_ARM_CPU_SUSPEND 166 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend 167 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume 168#endif 169 170/* 171 * Cortex-A9 processor functions 172 */ 173 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init 174 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin 175 globl_equ cpu_ca9mp_reset, cpu_v7_reset 176 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle 177 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area 178 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm 179 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext 180.globl cpu_ca9mp_suspend_size 181.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2 182#ifdef CONFIG_ARM_CPU_SUSPEND 183ENTRY(cpu_ca9mp_do_suspend) 184 stmfd sp!, {r4 - r5} 185 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register 186 mrc p15, 0, r5, c15, c0, 0 @ Power register 187 stmia r0!, {r4 - r5} 188 ldmfd sp!, {r4 - r5} 189 b cpu_v7_do_suspend 190ENDPROC(cpu_ca9mp_do_suspend) 191 192ENTRY(cpu_ca9mp_do_resume) 193 ldmia r0!, {r4 - r5} 194 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register 195 teq r4, r10 @ Already restored? 196 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it 197 mrc p15, 0, r10, c15, c0, 0 @ Read Power register 198 teq r5, r10 @ Already restored? 199 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it 200 b cpu_v7_do_resume 201ENDPROC(cpu_ca9mp_do_resume) 202#endif 203 204#ifdef CONFIG_CPU_PJ4B 205 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm 206 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext 207 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init 208 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin 209 globl_equ cpu_pj4b_reset, cpu_v7_reset 210#ifdef CONFIG_PJ4B_ERRATA_4742 211ENTRY(cpu_pj4b_do_idle) 212 dsb @ WFI may enter a low-power mode 213 wfi 214 dsb @barrier 215 ret lr 216ENDPROC(cpu_pj4b_do_idle) 217#else 218 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle 219#endif 220 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area 221#ifdef CONFIG_ARM_CPU_SUSPEND 222ENTRY(cpu_pj4b_do_suspend) 223 stmfd sp!, {r6 - r10} 224 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features 225 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 226 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 227 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 228 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC 229 stmia r0!, {r6 - r10} 230 ldmfd sp!, {r6 - r10} 231 b cpu_v7_do_suspend 232ENDPROC(cpu_pj4b_do_suspend) 233 234ENTRY(cpu_pj4b_do_resume) 235 ldmia r0!, {r6 - r10} 236 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features 237 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0 238 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2 239 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1 240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC 241 b cpu_v7_do_resume 242ENDPROC(cpu_pj4b_do_resume) 243#endif 244.globl cpu_pj4b_suspend_size 245.equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5 246 247#endif 248 249/* 250 * __v7_setup 251 * 252 * Initialise TLB, Caches, and MMU state ready to switch the MMU 253 * on. Return in r0 the new CP15 C1 control register setting. 254 * 255 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack 256 * r4: TTBR0 (low word) 257 * r5: TTBR0 (high word if LPAE) 258 * r8: TTBR1 259 * r9: Main ID register 260 * 261 * This should be able to cover all ARMv7 cores. 262 * 263 * It is assumed that: 264 * - cache type register is implemented 265 */ 266__v7_ca5mp_setup: 267__v7_ca9mp_setup: 268__v7_cr7mp_setup: 269 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting 270 b 1f 271__v7_ca7mp_setup: 272__v7_ca12mp_setup: 273__v7_ca15mp_setup: 274__v7_b15mp_setup: 275__v7_ca17mp_setup: 276 mov r10, #0 2771: 278#ifdef CONFIG_SMP 279 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 280 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 281 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 282 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 283 orreq r0, r0, r10 @ Enable CPU-specific SMP bits 284 mcreq p15, 0, r0, c1, c0, 1 285#endif 286 b __v7_setup 287 288/* 289 * Errata: 290 * r0, r10 available for use 291 * r1, r2, r4, r5, r9, r13: must be preserved 292 * r3: contains MIDR rX number in bits 23-20 293 * r6: contains MIDR rXpY as 8-bit XY number 294 * r9: MIDR 295 */ 296__ca8_errata: 297#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) 298 teq r3, #0x00100000 @ only present in r1p* 299 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register 300 orreq r0, r0, #(1 << 6) @ set IBE to 1 301 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register 302#endif 303#ifdef CONFIG_ARM_ERRATA_458693 304 teq r6, #0x20 @ only present in r2p0 305 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register 306 orreq r0, r0, #(1 << 5) @ set L1NEON to 1 307 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1 308 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register 309#endif 310#ifdef CONFIG_ARM_ERRATA_460075 311 teq r6, #0x20 @ only present in r2p0 312 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register 313 tsteq r0, #1 << 22 314 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit 315 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register 316#endif 317 b __errata_finish 318 319__ca9_errata: 320#ifdef CONFIG_ARM_ERRATA_742230 321 cmp r6, #0x22 @ only present up to r2p2 322 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register 323 orrle r0, r0, #1 << 4 @ set bit #4 324 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register 325#endif 326#ifdef CONFIG_ARM_ERRATA_742231 327 teq r6, #0x20 @ present in r2p0 328 teqne r6, #0x21 @ present in r2p1 329 teqne r6, #0x22 @ present in r2p2 330 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register 331 orreq r0, r0, #1 << 12 @ set bit #12 332 orreq r0, r0, #1 << 22 @ set bit #22 333 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register 334#endif 335#ifdef CONFIG_ARM_ERRATA_743622 336 teq r3, #0x00200000 @ only present in r2p* 337 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register 338 orreq r0, r0, #1 << 6 @ set bit #6 339 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register 340#endif 341#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) 342 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 343 ALT_UP_B(1f) 344 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register 345 orrlt r0, r0, #1 << 11 @ set bit #11 346 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register 3471: 348#endif 349 b __errata_finish 350 351__ca15_errata: 352#ifdef CONFIG_ARM_ERRATA_773022 353 cmp r6, #0x4 @ only present up to r0p4 354 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register 355 orrle r0, r0, #1 << 1 @ disable loop buffer 356 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register 357#endif 358 b __errata_finish 359 360__v7_pj4b_setup: 361#ifdef CONFIG_CPU_PJ4B 362 363/* Auxiliary Debug Modes Control 1 Register */ 364#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ 365#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ 366#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ 367 368/* Auxiliary Debug Modes Control 2 Register */ 369#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ 370#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ 371#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ 372#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ 373#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ 374#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ 375 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) 376 377/* Auxiliary Functional Modes Control Register 0 */ 378#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ 379#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ 380#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ 381 382/* Auxiliary Debug Modes Control 0 Register */ 383#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ 384 385 /* Auxiliary Debug Modes Control 1 Register */ 386 mrc p15, 1, r0, c15, c1, 1 387 orr r0, r0, #PJ4B_CLEAN_LINE 388 orr r0, r0, #PJ4B_INTER_PARITY 389 bic r0, r0, #PJ4B_STATIC_BP 390 mcr p15, 1, r0, c15, c1, 1 391 392 /* Auxiliary Debug Modes Control 2 Register */ 393 mrc p15, 1, r0, c15, c1, 2 394 bic r0, r0, #PJ4B_FAST_LDR 395 orr r0, r0, #PJ4B_AUX_DBG_CTRL2 396 mcr p15, 1, r0, c15, c1, 2 397 398 /* Auxiliary Functional Modes Control Register 0 */ 399 mrc p15, 1, r0, c15, c2, 0 400#ifdef CONFIG_SMP 401 orr r0, r0, #PJ4B_SMP_CFB 402#endif 403 orr r0, r0, #PJ4B_L1_PAR_CHK 404 orr r0, r0, #PJ4B_BROADCAST_CACHE 405 mcr p15, 1, r0, c15, c2, 0 406 407 /* Auxiliary Debug Modes Control 0 Register */ 408 mrc p15, 1, r0, c15, c1, 0 409 orr r0, r0, #PJ4B_WFI_WFE 410 mcr p15, 1, r0, c15, c1, 0 411 412#endif /* CONFIG_CPU_PJ4B */ 413 414__v7_setup: 415 adr r12, __v7_setup_stack @ the local stack 416 stmia r12, {r0-r5, r7, r9, r11, lr} 417 bl v7_invalidate_l1 418 ldmia r12, {r0-r5, r7, r9, r11, lr} 419 420 and r0, r9, #0xff000000 @ ARM? 421 teq r0, #0x41000000 422 bne __errata_finish 423 and r3, r9, #0x00f00000 @ variant 424 and r6, r9, #0x0000000f @ revision 425 orr r6, r6, r3, lsr #20-4 @ combine variant and revision 426 ubfx r0, r9, #4, #12 @ primary part number 427 428 /* Cortex-A8 Errata */ 429 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 430 teq r0, r10 431 beq __ca8_errata 432 433 /* Cortex-A9 Errata */ 434 ldr r10, =0x00000c09 @ Cortex-A9 primary part number 435 teq r0, r10 436 beq __ca9_errata 437 438 /* Cortex-A15 Errata */ 439 ldr r10, =0x00000c0f @ Cortex-A15 primary part number 440 teq r0, r10 441 beq __ca15_errata 442 443__errata_finish: 444 mov r10, #0 445 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 446#ifdef CONFIG_MMU 447 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 448 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup 449 ldr r3, =PRRR @ PRRR 450 ldr r6, =NMRR @ NMRR 451 mcr p15, 0, r3, c10, c2, 0 @ write PRRR 452 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 453#endif 454 dsb @ Complete invalidations 455#ifndef CONFIG_ARM_THUMBEE 456 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE 457 and r0, r0, #(0xf << 12) @ ThumbEE enabled field 458 teq r0, #(1 << 12) @ check if ThumbEE is present 459 bne 1f 460 mov r3, #0 461 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0 462 mrc p14, 6, r0, c0, c0, 0 @ load TEECR 463 orr r0, r0, #1 @ set the 1st bit in order to 464 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access 4651: 466#endif 467 adr r3, v7_crval 468 ldmia r3, {r3, r6} 469 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables 470#ifdef CONFIG_SWP_EMULATE 471 orr r3, r3, #(1 << 10) @ set SW bit in "clear" 472 bic r6, r6, #(1 << 10) @ clear it in "mmuset" 473#endif 474 mrc p15, 0, r0, c1, c0, 0 @ read control register 475 bic r0, r0, r3 @ clear bits them 476 orr r0, r0, r6 @ set them 477 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 478 ret lr @ return to head.S:__ret 479ENDPROC(__v7_setup) 480 481 .align 2 482__v7_setup_stack: 483 .space 4 * 11 @ 11 registers 484 485 __INITDATA 486 487 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 488 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 489#ifndef CONFIG_ARM_LPAE 490 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 491 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 492#endif 493#ifdef CONFIG_CPU_PJ4B 494 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 495#endif 496 497 .section ".rodata" 498 499 string cpu_arch_name, "armv7" 500 string cpu_elf_name, "v7" 501 .align 502 503 .section ".proc.info.init", #alloc 504 505 /* 506 * Standard v7 proc info content 507 */ 508.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions 509 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 510 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) 511 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 512 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) 513 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ 514 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags 515 initfn \initfunc, \name 516 .long cpu_arch_name 517 .long cpu_elf_name 518 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 519 HWCAP_EDSP | HWCAP_TLS | \hwcaps 520 .long cpu_v7_name 521 .long \proc_fns 522 .long v7wbi_tlb_fns 523 .long v6_user_fns 524 .long v7_cache_fns 525.endm 526 527#ifndef CONFIG_ARM_LPAE 528 /* 529 * ARM Ltd. Cortex A5 processor. 530 */ 531 .type __v7_ca5mp_proc_info, #object 532__v7_ca5mp_proc_info: 533 .long 0x410fc050 534 .long 0xff0ffff0 535 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup 536 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 537 538 /* 539 * ARM Ltd. Cortex A9 processor. 540 */ 541 .type __v7_ca9mp_proc_info, #object 542__v7_ca9mp_proc_info: 543 .long 0x410fc090 544 .long 0xff0ffff0 545 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions 546 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 547 548 /* 549 * ARM Ltd. Cortex A8 processor. 550 */ 551 .type __v7_ca8_proc_info, #object 552__v7_ca8_proc_info: 553 .long 0x410fc080 554 .long 0xff0ffff0 555 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions 556 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info 557 558#endif /* CONFIG_ARM_LPAE */ 559 560 /* 561 * Marvell PJ4B processor. 562 */ 563#ifdef CONFIG_CPU_PJ4B 564 .type __v7_pj4b_proc_info, #object 565__v7_pj4b_proc_info: 566 .long 0x560f5800 567 .long 0xff0fff00 568 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions 569 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 570#endif 571 572 /* 573 * ARM Ltd. Cortex R7 processor. 574 */ 575 .type __v7_cr7mp_proc_info, #object 576__v7_cr7mp_proc_info: 577 .long 0x410fc170 578 .long 0xff0ffff0 579 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup 580 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info 581 582 /* 583 * ARM Ltd. Cortex A7 processor. 584 */ 585 .type __v7_ca7mp_proc_info, #object 586__v7_ca7mp_proc_info: 587 .long 0x410fc070 588 .long 0xff0ffff0 589 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup 590 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 591 592 /* 593 * ARM Ltd. Cortex A12 processor. 594 */ 595 .type __v7_ca12mp_proc_info, #object 596__v7_ca12mp_proc_info: 597 .long 0x410fc0d0 598 .long 0xff0ffff0 599 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup 600 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info 601 602 /* 603 * ARM Ltd. Cortex A15 processor. 604 */ 605 .type __v7_ca15mp_proc_info, #object 606__v7_ca15mp_proc_info: 607 .long 0x410fc0f0 608 .long 0xff0ffff0 609 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup 610 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 611 612 /* 613 * Broadcom Corporation Brahma-B15 processor. 614 */ 615 .type __v7_b15mp_proc_info, #object 616__v7_b15mp_proc_info: 617 .long 0x420f00f0 618 .long 0xff0ffff0 619 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup 620 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info 621 622 /* 623 * ARM Ltd. Cortex A17 processor. 624 */ 625 .type __v7_ca17mp_proc_info, #object 626__v7_ca17mp_proc_info: 627 .long 0x410fc0e0 628 .long 0xff0ffff0 629 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup 630 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info 631 632 /* 633 * Qualcomm Inc. Krait processors. 634 */ 635 .type __krait_proc_info, #object 636__krait_proc_info: 637 .long 0x510f0400 @ Required ID value 638 .long 0xff0ffc00 @ Mask for ID 639 /* 640 * Some Krait processors don't indicate support for SDIV and UDIV 641 * instructions in the ARM instruction set, even though they actually 642 * do support them. They also don't indicate support for fused multiply 643 * instructions even though they actually do support them. 644 */ 645 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4 646 .size __krait_proc_info, . - __krait_proc_info 647 648 /* 649 * Match any ARMv7 processor core. 650 */ 651 .type __v7_proc_info, #object 652__v7_proc_info: 653 .long 0x000f0000 @ Required ID value 654 .long 0x000f0000 @ Mask for ID 655 __v7_proc __v7_proc_info, __v7_setup 656 .size __v7_proc_info, . - __v7_proc_info 657