1/* 2 * arch/arm/mm/proc-v7-3level.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2011 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * based on arch/arm/mm/proc-v7-2level.S 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22#include <asm/assembler.h> 23 24#define TTB_IRGN_NC (0 << 8) 25#define TTB_IRGN_WBWA (1 << 8) 26#define TTB_IRGN_WT (2 << 8) 27#define TTB_IRGN_WB (3 << 8) 28#define TTB_RGN_NC (0 << 10) 29#define TTB_RGN_OC_WBWA (1 << 10) 30#define TTB_RGN_OC_WT (2 << 10) 31#define TTB_RGN_OC_WB (3 << 10) 32#define TTB_S (3 << 12) 33#define TTB_EAE (1 << 31) 34 35/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 36#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB) 37#define PMD_FLAGS_UP (PMD_SECT_WB) 38 39/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 40#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA) 41#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S) 42 43#ifndef __ARMEB__ 44# define rpgdl r0 45# define rpgdh r1 46#else 47# define rpgdl r1 48# define rpgdh r0 49#endif 50 51/* 52 * cpu_v7_switch_mm(pgd_phys, tsk) 53 * 54 * Set the translation table base pointer to be pgd_phys (physical address of 55 * the new TTB). 56 */ 57ENTRY(cpu_v7_switch_mm) 58#ifdef CONFIG_MMU 59 mmid r2, r2 60 asid r2, r2 61 orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd 62 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0 63 isb 64#endif 65 ret lr 66ENDPROC(cpu_v7_switch_mm) 67 68#ifdef __ARMEB__ 69#define rl r3 70#define rh r2 71#else 72#define rl r2 73#define rh r3 74#endif 75 76/* 77 * cpu_v7_set_pte_ext(ptep, pte) 78 * 79 * Set a level 2 translation table entry. 80 * - ptep - pointer to level 3 translation table entry 81 * - pte - PTE value to store (64-bit in r2 and r3) 82 */ 83ENTRY(cpu_v7_set_pte_ext) 84#ifdef CONFIG_MMU 85 tst rl, #L_PTE_VALID 86 beq 1f 87 tst rh, #1 << (57 - 32) @ L_PTE_NONE 88 bicne rl, #L_PTE_VALID 89 bne 1f 90 91 eor ip, rh, #1 << (55 - 32) @ toggle L_PTE_DIRTY in temp reg to 92 @ test for !L_PTE_DIRTY || L_PTE_RDONLY 93 tst ip, #1 << (55 - 32) | 1 << (58 - 32) 94 orrne rl, #PTE_AP2 95 biceq rl, #PTE_AP2 96 971: strd r2, r3, [r0] 98 ALT_SMP(W(nop)) 99 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 100#endif 101 ret lr 102ENDPROC(cpu_v7_set_pte_ext) 103 104 /* 105 * Memory region attributes for LPAE (defined in pgtable-3level.h): 106 * 107 * n = AttrIndx[2:0] 108 * 109 * n MAIR 110 * UNCACHED 000 00000000 111 * BUFFERABLE 001 01000100 112 * DEV_WC 001 01000100 113 * WRITETHROUGH 010 10101010 114 * WRITEBACK 011 11101110 115 * DEV_CACHED 011 11101110 116 * DEV_SHARED 100 00000100 117 * DEV_NONSHARED 100 00000100 118 * unused 101 119 * unused 110 120 * WRITEALLOC 111 11111111 121 */ 122.equ PRRR, 0xeeaa4400 @ MAIR0 123.equ NMRR, 0xff000004 @ MAIR1 124 125 /* 126 * Macro for setting up the TTBRx and TTBCR registers. 127 * - \ttbr1 updated. 128 */ 129 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp 130 ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address 131 cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET? 132 mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister 133 orr \tmp, \tmp, #TTB_EAE 134 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) 135 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) 136 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) 137 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) 138 /* 139 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above), 140 * otherwise booting secondary CPUs would end up using TTBR1 for the 141 * identity mapping set up in TTBR0. 142 */ 143 orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ 144 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR 145 mov \tmp, \ttbr1, lsr #20 146 mov \ttbr1, \ttbr1, lsl #12 147 addls \ttbr1, \ttbr1, #TTBR1_OFFSET 148 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1 149 .endm 150 151 /* 152 * AT 153 * TFR EV X F IHD LR S 154 * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM 155 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 156 * 11 0 110 0 0011 1100 .111 1101 < we want 157 */ 158 .align 2 159 .type v7_crval, #object 160v7_crval: 161 crval clear=0x0122c302, mmuset=0x30c03c7d, ucset=0x00c01c7c 162