1/* 2 * arch/arm/mm/proc-v7-3level.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2011 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * based on arch/arm/mm/proc-v7-2level.S 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#define TTB_IRGN_NC (0 << 8) 24#define TTB_IRGN_WBWA (1 << 8) 25#define TTB_IRGN_WT (2 << 8) 26#define TTB_IRGN_WB (3 << 8) 27#define TTB_RGN_NC (0 << 10) 28#define TTB_RGN_OC_WBWA (1 << 10) 29#define TTB_RGN_OC_WT (2 << 10) 30#define TTB_RGN_OC_WB (3 << 10) 31#define TTB_S (3 << 12) 32#define TTB_EAE (1 << 31) 33 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 35#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB) 36#define PMD_FLAGS_UP (PMD_SECT_WB) 37 38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 39#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA) 40#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S) 41 42#ifndef __ARMEB__ 43# define rpgdl r0 44# define rpgdh r1 45#else 46# define rpgdl r1 47# define rpgdh r0 48#endif 49 50/* 51 * cpu_v7_switch_mm(pgd_phys, tsk) 52 * 53 * Set the translation table base pointer to be pgd_phys (physical address of 54 * the new TTB). 55 */ 56ENTRY(cpu_v7_switch_mm) 57#ifdef CONFIG_MMU 58 mmid r2, r2 59 asid r2, r2 60 orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd 61 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0 62 isb 63#endif 64 mov pc, lr 65ENDPROC(cpu_v7_switch_mm) 66 67#ifdef __ARMEB__ 68#define rl r3 69#define rh r2 70#else 71#define rl r2 72#define rh r3 73#endif 74 75/* 76 * cpu_v7_set_pte_ext(ptep, pte) 77 * 78 * Set a level 2 translation table entry. 79 * - ptep - pointer to level 3 translation table entry 80 * - pte - PTE value to store (64-bit in r2 and r3) 81 */ 82ENTRY(cpu_v7_set_pte_ext) 83#ifdef CONFIG_MMU 84 tst rl, #L_PTE_VALID 85 beq 1f 86 tst rh, #1 << (57 - 32) @ L_PTE_NONE 87 bicne rl, #L_PTE_VALID 88 bne 1f 89 tst rh, #1 << (55 - 32) @ L_PTE_DIRTY 90 orreq rl, #L_PTE_RDONLY 911: strd r2, r3, [r0] 92 ALT_SMP(W(nop)) 93 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 94#endif 95 mov pc, lr 96ENDPROC(cpu_v7_set_pte_ext) 97 98 /* 99 * Memory region attributes for LPAE (defined in pgtable-3level.h): 100 * 101 * n = AttrIndx[2:0] 102 * 103 * n MAIR 104 * UNCACHED 000 00000000 105 * BUFFERABLE 001 01000100 106 * DEV_WC 001 01000100 107 * WRITETHROUGH 010 10101010 108 * WRITEBACK 011 11101110 109 * DEV_CACHED 011 11101110 110 * DEV_SHARED 100 00000100 111 * DEV_NONSHARED 100 00000100 112 * unused 101 113 * unused 110 114 * WRITEALLOC 111 11111111 115 */ 116.equ PRRR, 0xeeaa4400 @ MAIR0 117.equ NMRR, 0xff000004 @ MAIR1 118 119 /* 120 * Macro for setting up the TTBRx and TTBCR registers. 121 * - \ttbr1 updated. 122 */ 123 .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp 124 ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address 125 mov \tmp, \tmp, lsr #ARCH_PGD_SHIFT 126 cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? 127 mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register 128 orr \tmp, \tmp, #TTB_EAE 129 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) 130 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) 131 ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) 132 ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) 133 /* 134 * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above), 135 * otherwise booting secondary CPUs would end up using TTBR1 for the 136 * identity mapping set up in TTBR0. 137 */ 138 orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ 139 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR 140 mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits 141 mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits 142 addls \ttbr1, \ttbr1, #TTBR1_OFFSET 143 mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 144 mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits 145 mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits 146 mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 147 mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 148 mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 149 .endm 150 151 /* 152 * AT 153 * TFR EV X F IHD LR S 154 * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM 155 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 156 * 11 0 110 1 0011 1100 .111 1101 < we want 157 */ 158 .align 2 159 .type v7_crval, #object 160v7_crval: 161 crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c 162