11b6ba46bSCatalin Marinas/* 21b6ba46bSCatalin Marinas * arch/arm/mm/proc-v7-3level.S 31b6ba46bSCatalin Marinas * 41b6ba46bSCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 51b6ba46bSCatalin Marinas * Copyright (C) 2011 ARM Ltd. 61b6ba46bSCatalin Marinas * Author: Catalin Marinas <catalin.marinas@arm.com> 71b6ba46bSCatalin Marinas * based on arch/arm/mm/proc-v7-2level.S 81b6ba46bSCatalin Marinas * 91b6ba46bSCatalin Marinas * This program is free software; you can redistribute it and/or modify 101b6ba46bSCatalin Marinas * it under the terms of the GNU General Public License version 2 as 111b6ba46bSCatalin Marinas * published by the Free Software Foundation. 121b6ba46bSCatalin Marinas * 131b6ba46bSCatalin Marinas * This program is distributed in the hope that it will be useful, 141b6ba46bSCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 151b6ba46bSCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 161b6ba46bSCatalin Marinas * GNU General Public License for more details. 171b6ba46bSCatalin Marinas * 181b6ba46bSCatalin Marinas * You should have received a copy of the GNU General Public License 191b6ba46bSCatalin Marinas * along with this program; if not, write to the Free Software 201b6ba46bSCatalin Marinas * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 211b6ba46bSCatalin Marinas */ 221b6ba46bSCatalin Marinas 231b6ba46bSCatalin Marinas#define TTB_IRGN_NC (0 << 8) 241b6ba46bSCatalin Marinas#define TTB_IRGN_WBWA (1 << 8) 251b6ba46bSCatalin Marinas#define TTB_IRGN_WT (2 << 8) 261b6ba46bSCatalin Marinas#define TTB_IRGN_WB (3 << 8) 271b6ba46bSCatalin Marinas#define TTB_RGN_NC (0 << 10) 281b6ba46bSCatalin Marinas#define TTB_RGN_OC_WBWA (1 << 10) 291b6ba46bSCatalin Marinas#define TTB_RGN_OC_WT (2 << 10) 301b6ba46bSCatalin Marinas#define TTB_RGN_OC_WB (3 << 10) 311b6ba46bSCatalin Marinas#define TTB_S (3 << 12) 321b6ba46bSCatalin Marinas#define TTB_EAE (1 << 31) 331b6ba46bSCatalin Marinas 341b6ba46bSCatalin Marinas/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 351b6ba46bSCatalin Marinas#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB) 361b6ba46bSCatalin Marinas#define PMD_FLAGS_UP (PMD_SECT_WB) 371b6ba46bSCatalin Marinas 381b6ba46bSCatalin Marinas/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 391b6ba46bSCatalin Marinas#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA) 401b6ba46bSCatalin Marinas#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S) 411b6ba46bSCatalin Marinas 4213f659b0SCyril Chemparathy#ifndef __ARMEB__ 4313f659b0SCyril Chemparathy# define rpgdl r0 4413f659b0SCyril Chemparathy# define rpgdh r1 4513f659b0SCyril Chemparathy#else 4613f659b0SCyril Chemparathy# define rpgdl r1 4713f659b0SCyril Chemparathy# define rpgdh r0 4813f659b0SCyril Chemparathy#endif 4913f659b0SCyril Chemparathy 501b6ba46bSCatalin Marinas/* 511b6ba46bSCatalin Marinas * cpu_v7_switch_mm(pgd_phys, tsk) 521b6ba46bSCatalin Marinas * 531b6ba46bSCatalin Marinas * Set the translation table base pointer to be pgd_phys (physical address of 541b6ba46bSCatalin Marinas * the new TTB). 551b6ba46bSCatalin Marinas */ 561b6ba46bSCatalin MarinasENTRY(cpu_v7_switch_mm) 571b6ba46bSCatalin Marinas#ifdef CONFIG_MMU 5813f659b0SCyril Chemparathy mmid r2, r2 5913f659b0SCyril Chemparathy asid r2, r2 6013f659b0SCyril Chemparathy orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd 6113f659b0SCyril Chemparathy mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0 621b6ba46bSCatalin Marinas isb 631b6ba46bSCatalin Marinas#endif 641b6ba46bSCatalin Marinas mov pc, lr 651b6ba46bSCatalin MarinasENDPROC(cpu_v7_switch_mm) 661b6ba46bSCatalin Marinas 671b6ba46bSCatalin Marinas/* 681b6ba46bSCatalin Marinas * cpu_v7_set_pte_ext(ptep, pte) 691b6ba46bSCatalin Marinas * 701b6ba46bSCatalin Marinas * Set a level 2 translation table entry. 711b6ba46bSCatalin Marinas * - ptep - pointer to level 3 translation table entry 721b6ba46bSCatalin Marinas * - pte - PTE value to store (64-bit in r2 and r3) 731b6ba46bSCatalin Marinas */ 741b6ba46bSCatalin MarinasENTRY(cpu_v7_set_pte_ext) 751b6ba46bSCatalin Marinas#ifdef CONFIG_MMU 76dbf62d50SWill Deacon tst r2, #L_PTE_VALID 771b6ba46bSCatalin Marinas beq 1f 7826ffd0d4SWill Deacon tst r3, #1 << (57 - 32) @ L_PTE_NONE 7926ffd0d4SWill Deacon bicne r2, #L_PTE_VALID 8026ffd0d4SWill Deacon bne 1f 811b6ba46bSCatalin Marinas tst r3, #1 << (55 - 32) @ L_PTE_DIRTY 821b6ba46bSCatalin Marinas orreq r2, #L_PTE_RDONLY 831b6ba46bSCatalin Marinas1: strd r2, r3, [r0] 84bf3f0f33SWill Deacon ALT_SMP(W(nop)) 85ae8a8b95SWill Deacon ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 861b6ba46bSCatalin Marinas#endif 871b6ba46bSCatalin Marinas mov pc, lr 881b6ba46bSCatalin MarinasENDPROC(cpu_v7_set_pte_ext) 891b6ba46bSCatalin Marinas 901b6ba46bSCatalin Marinas /* 911b6ba46bSCatalin Marinas * Memory region attributes for LPAE (defined in pgtable-3level.h): 921b6ba46bSCatalin Marinas * 931b6ba46bSCatalin Marinas * n = AttrIndx[2:0] 941b6ba46bSCatalin Marinas * 951b6ba46bSCatalin Marinas * n MAIR 961b6ba46bSCatalin Marinas * UNCACHED 000 00000000 971b6ba46bSCatalin Marinas * BUFFERABLE 001 01000100 981b6ba46bSCatalin Marinas * DEV_WC 001 01000100 991b6ba46bSCatalin Marinas * WRITETHROUGH 010 10101010 1001b6ba46bSCatalin Marinas * WRITEBACK 011 11101110 1011b6ba46bSCatalin Marinas * DEV_CACHED 011 11101110 1021b6ba46bSCatalin Marinas * DEV_SHARED 100 00000100 1031b6ba46bSCatalin Marinas * DEV_NONSHARED 100 00000100 1041b6ba46bSCatalin Marinas * unused 101 1051b6ba46bSCatalin Marinas * unused 110 1061b6ba46bSCatalin Marinas * WRITEALLOC 111 11111111 1071b6ba46bSCatalin Marinas */ 1081b6ba46bSCatalin Marinas.equ PRRR, 0xeeaa4400 @ MAIR0 1091b6ba46bSCatalin Marinas.equ NMRR, 0xff000004 @ MAIR1 1101b6ba46bSCatalin Marinas 1111b6ba46bSCatalin Marinas /* 1121b6ba46bSCatalin Marinas * Macro for setting up the TTBRx and TTBCR registers. 1131b6ba46bSCatalin Marinas * - \ttbr1 updated. 1141b6ba46bSCatalin Marinas */ 1151b6ba46bSCatalin Marinas .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp 1161b6ba46bSCatalin Marinas ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address 1174756dcbfSCyril Chemparathy mov \tmp, \tmp, lsr #ARCH_PGD_SHIFT 118a7fbc0d6SCyril Chemparathy cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? 1191b6ba46bSCatalin Marinas mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register 1201b6ba46bSCatalin Marinas orr \tmp, \tmp, #TTB_EAE 1211b6ba46bSCatalin Marinas ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) 1221b6ba46bSCatalin Marinas ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) 1231b6ba46bSCatalin Marinas ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) 1241b6ba46bSCatalin Marinas ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) 1251b6ba46bSCatalin Marinas /* 126a7fbc0d6SCyril Chemparathy * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above), 127a7fbc0d6SCyril Chemparathy * otherwise booting secondary CPUs would end up using TTBR1 for the 128a7fbc0d6SCyril Chemparathy * identity mapping set up in TTBR0. 1291b6ba46bSCatalin Marinas */ 130a7fbc0d6SCyril Chemparathy orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ 131a7fbc0d6SCyril Chemparathy mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR 1324756dcbfSCyril Chemparathy mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits 1334756dcbfSCyril Chemparathy mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits 134a7fbc0d6SCyril Chemparathy addls \ttbr1, \ttbr1, #TTBR1_OFFSET 1351b6ba46bSCatalin Marinas mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 1364756dcbfSCyril Chemparathy mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits 1374756dcbfSCyril Chemparathy mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits 1384756dcbfSCyril Chemparathy mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 1394756dcbfSCyril Chemparathy mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 1404756dcbfSCyril Chemparathy mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 1411b6ba46bSCatalin Marinas .endm 1421b6ba46bSCatalin Marinas 1431b6ba46bSCatalin Marinas /* 1441b6ba46bSCatalin Marinas * AT 1451b6ba46bSCatalin Marinas * TFR EV X F IHD LR S 1461b6ba46bSCatalin Marinas * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM 1471b6ba46bSCatalin Marinas * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 1481b6ba46bSCatalin Marinas * 11 0 110 1 0011 1100 .111 1101 < we want 1491b6ba46bSCatalin Marinas */ 1501b6ba46bSCatalin Marinas .align 2 1511b6ba46bSCatalin Marinas .type v7_crval, #object 1521b6ba46bSCatalin Marinasv7_crval: 1531b6ba46bSCatalin Marinas crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c 154