1/* 2 * arch/arm/mm/proc-v7-2level.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#define TTB_S (1 << 1) 12#define TTB_RGN_NC (0 << 3) 13#define TTB_RGN_OC_WBWA (1 << 3) 14#define TTB_RGN_OC_WT (2 << 3) 15#define TTB_RGN_OC_WB (3 << 3) 16#define TTB_NOS (1 << 5) 17#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 18#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 19#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 20#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 21 22/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 23#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 24#define PMD_FLAGS_UP PMD_SECT_WB 25 26/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 27#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 28#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 29 30/* 31 * cpu_v7_switch_mm(pgd_phys, tsk) 32 * 33 * Set the translation table base pointer to be pgd_phys 34 * 35 * - pgd_phys - physical address of new TTB 36 * 37 * It is assumed that: 38 * - we are not using split page tables 39 * 40 * Note that we always need to flush BTAC/BTB if IBE is set 41 * even on Cortex-A8 revisions not affected by 430973. 42 * If IBE is not set, the flush BTAC/BTB won't do anything. 43 */ 44ENTRY(cpu_v7_switch_mm) 45#ifdef CONFIG_MMU 46 mmid r1, r1 @ get mm->context.id 47 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 48 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 49#ifdef CONFIG_PID_IN_CONTEXTIDR 50 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 51 lsr r2, r2, #8 @ extract the PID 52 bfi r1, r2, #8, #24 @ insert into new context ID 53#endif 54#ifdef CONFIG_ARM_ERRATA_754322 55 dsb 56#endif 57 mcr p15, 0, r1, c13, c0, 1 @ set context ID 58 isb 59 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 60 isb 61#endif 62 bx lr 63ENDPROC(cpu_v7_switch_mm) 64 65/* 66 * cpu_v7_set_pte_ext(ptep, pte) 67 * 68 * Set a level 2 translation table entry. 69 * 70 * - ptep - pointer to level 2 translation table entry 71 * (hardware version is stored at +2048 bytes) 72 * - pte - PTE value to store 73 * - ext - value for extended PTE bits 74 */ 75ENTRY(cpu_v7_set_pte_ext) 76#ifdef CONFIG_MMU 77 str r1, [r0] @ linux version 78 79 bic r3, r1, #0x000003f0 80 bic r3, r3, #PTE_TYPE_MASK 81 orr r3, r3, r2 82 orr r3, r3, #PTE_EXT_AP0 | 2 83 84 tst r1, #1 << 4 85 orrne r3, r3, #PTE_EXT_TEX(1) 86 87 eor r1, r1, #L_PTE_DIRTY 88 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 89 orrne r3, r3, #PTE_EXT_APX 90 91 tst r1, #L_PTE_USER 92 orrne r3, r3, #PTE_EXT_AP1 93 94 tst r1, #L_PTE_XN 95 orrne r3, r3, #PTE_EXT_XN 96 97 tst r1, #L_PTE_YOUNG 98 tstne r1, #L_PTE_VALID 99 eorne r1, r1, #L_PTE_NONE 100 tstne r1, #L_PTE_NONE 101 moveq r3, #0 102 103 ARM( str r3, [r0, #2048]! ) 104 THUMB( add r0, r0, #2048 ) 105 THUMB( str r3, [r0] ) 106 ALT_SMP(W(nop)) 107 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 108#endif 109 bx lr 110ENDPROC(cpu_v7_set_pte_ext) 111 112 /* 113 * Memory region attributes with SCTLR.TRE=1 114 * 115 * n = TEX[0],C,B 116 * TR = PRRR[2n+1:2n] - memory type 117 * IR = NMRR[2n+1:2n] - inner cacheable property 118 * OR = NMRR[2n+17:2n+16] - outer cacheable property 119 * 120 * n TR IR OR 121 * UNCACHED 000 00 122 * BUFFERABLE 001 10 00 00 123 * WRITETHROUGH 010 10 10 10 124 * WRITEBACK 011 10 11 11 125 * reserved 110 126 * WRITEALLOC 111 10 01 01 127 * DEV_SHARED 100 01 128 * DEV_NONSHARED 100 01 129 * DEV_WC 001 10 130 * DEV_CACHED 011 10 131 * 132 * Other attributes: 133 * 134 * DS0 = PRRR[16] = 0 - device shareable property 135 * DS1 = PRRR[17] = 1 - device shareable property 136 * NS0 = PRRR[18] = 0 - normal shareable property 137 * NS1 = PRRR[19] = 1 - normal shareable property 138 * NOS = PRRR[24+n] = 1 - not outer shareable 139 */ 140.equ PRRR, 0xff0a81a8 141.equ NMRR, 0x40e040e0 142 143 /* 144 * Macro for setting up the TTBRx and TTBCR registers. 145 * - \ttb0 and \ttb1 updated with the corresponding flags. 146 */ 147 .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp 148 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 149 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP) 150 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP) 151 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) 152 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP) 153 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1 154 .endm 155 156 /* AT 157 * TFR EV X F I D LR S 158 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 159 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 160 * 01 0 110 0011 1100 .111 1101 < we want 161 */ 162 .align 2 163 .type v7_crval, #object 164v7_crval: 165 crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 166