1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv6 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable.h> 20 21#include "proc-macros.S" 22 23#define D_CACHE_LINE_SIZE 32 24 25#define TTB_C (1 << 0) 26#define TTB_S (1 << 1) 27#define TTB_IMP (1 << 2) 28#define TTB_RGN_NC (0 << 3) 29#define TTB_RGN_WBWA (1 << 3) 30#define TTB_RGN_WT (2 << 3) 31#define TTB_RGN_WB (3 << 3) 32 33#ifndef CONFIG_SMP 34#define TTB_FLAGS TTB_RGN_WBWA 35#else 36#define TTB_FLAGS TTB_RGN_WBWA|TTB_S 37#endif 38 39ENTRY(cpu_v6_proc_init) 40 mov pc, lr 41 42ENTRY(cpu_v6_proc_fin) 43 stmfd sp!, {lr} 44 cpsid if @ disable interrupts 45 bl v6_flush_kern_cache_all 46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 47 bic r0, r0, #0x1000 @ ...i............ 48 bic r0, r0, #0x0006 @ .............ca. 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 ldmfd sp!, {pc} 51 52/* 53 * cpu_v6_reset(loc) 54 * 55 * Perform a soft reset of the system. Put the CPU into the 56 * same state as it would be if it had been reset, and branch 57 * to what would be the reset vector. 58 * 59 * - loc - location to jump to for soft reset 60 * 61 * It is assumed that: 62 */ 63 .align 5 64ENTRY(cpu_v6_reset) 65 mov pc, r0 66 67/* 68 * cpu_v6_do_idle() 69 * 70 * Idle the processor (eg, wait for interrupt). 71 * 72 * IRQs are already disabled. 73 */ 74ENTRY(cpu_v6_do_idle) 75 mov r1, #0 76 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 77 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 78 mov pc, lr 79 80ENTRY(cpu_v6_dcache_clean_area) 81#ifndef TLB_CAN_READ_FROM_L1_CACHE 821: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 83 add r0, r0, #D_CACHE_LINE_SIZE 84 subs r1, r1, #D_CACHE_LINE_SIZE 85 bhi 1b 86#endif 87 mov pc, lr 88 89/* 90 * cpu_arm926_switch_mm(pgd_phys, tsk) 91 * 92 * Set the translation table base pointer to be pgd_phys 93 * 94 * - pgd_phys - physical address of new TTB 95 * 96 * It is assumed that: 97 * - we are not using split page tables 98 */ 99ENTRY(cpu_v6_switch_mm) 100#ifdef CONFIG_MMU 101 mov r2, #0 102 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 103 orr r0, r0, #TTB_FLAGS 104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 107 mcr p15, 0, r1, c13, c0, 1 @ set context ID 108#endif 109 mov pc, lr 110 111/* 112 * cpu_v6_set_pte_ext(ptep, pte, ext) 113 * 114 * Set a level 2 translation table entry. 115 * 116 * - ptep - pointer to level 2 translation table entry 117 * (hardware version is stored at -1024 bytes) 118 * - pte - PTE value to store 119 * - ext - value for extended PTE bits 120 */ 121 armv6_mt_table cpu_v6 122 123ENTRY(cpu_v6_set_pte_ext) 124#ifdef CONFIG_MMU 125 armv6_set_pte_ext cpu_v6 126#endif 127 mov pc, lr 128 129 130 131 132cpu_v6_name: 133 .asciz "ARMv6-compatible processor" 134 .align 135 136 __INIT 137 138/* 139 * __v6_setup 140 * 141 * Initialise TLB, Caches, and MMU state ready to switch the MMU 142 * on. Return in r0 the new CP15 C1 control register setting. 143 * 144 * We automatically detect if we have a Harvard cache, and use the 145 * Harvard cache control instructions insead of the unified cache 146 * control instructions. 147 * 148 * This should be able to cover all ARMv6 cores. 149 * 150 * It is assumed that: 151 * - cache type register is implemented 152 */ 153__v6_setup: 154#ifdef CONFIG_SMP 155 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 156 orr r0, r0, #0x20 157 mcr p15, 0, r0, c1, c0, 1 158#endif 159 160 mov r0, #0 161 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 162 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 163 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 164 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 165#ifdef CONFIG_MMU 166 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 167 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 168 orr r4, r4, #TTB_FLAGS 169 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 170#endif /* CONFIG_MMU */ 171 adr r5, v6_crval 172 ldmia r5, {r5, r6} 173#ifdef CONFIG_CPU_ENDIAN_BE8 174 orr r6, r6, #1 << 25 @ big-endian page tables 175#endif 176 mrc p15, 0, r0, c1, c0, 0 @ read control register 177 bic r0, r0, r5 @ clear bits them 178 orr r0, r0, r6 @ set them 179 mov pc, lr @ return to head.S:__ret 180 181 /* 182 * V X F I D LR 183 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 184 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 185 * 0 110 0011 1.00 .111 1101 < we want 186 */ 187 .type v6_crval, #object 188v6_crval: 189 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 190 191 .type v6_processor_functions, #object 192ENTRY(v6_processor_functions) 193 .word v6_early_abort 194 .word v6_pabort 195 .word cpu_v6_proc_init 196 .word cpu_v6_proc_fin 197 .word cpu_v6_reset 198 .word cpu_v6_do_idle 199 .word cpu_v6_dcache_clean_area 200 .word cpu_v6_switch_mm 201 .word cpu_v6_set_pte_ext 202 .size v6_processor_functions, . - v6_processor_functions 203 204 .type cpu_arch_name, #object 205cpu_arch_name: 206 .asciz "armv6" 207 .size cpu_arch_name, . - cpu_arch_name 208 209 .type cpu_elf_name, #object 210cpu_elf_name: 211 .asciz "v6" 212 .size cpu_elf_name, . - cpu_elf_name 213 .align 214 215 .section ".proc.info.init", #alloc, #execinstr 216 217 /* 218 * Match any ARMv6 processor core. 219 */ 220 .type __v6_proc_info, #object 221__v6_proc_info: 222 .long 0x0007b000 223 .long 0x0007f000 224 .long PMD_TYPE_SECT | \ 225 PMD_SECT_BUFFERABLE | \ 226 PMD_SECT_CACHEABLE | \ 227 PMD_SECT_AP_WRITE | \ 228 PMD_SECT_AP_READ 229 .long PMD_TYPE_SECT | \ 230 PMD_SECT_XN | \ 231 PMD_SECT_AP_WRITE | \ 232 PMD_SECT_AP_READ 233 b __v6_setup 234 .long cpu_arch_name 235 .long cpu_elf_name 236 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA 237 .long cpu_v6_name 238 .long v6_processor_functions 239 .long v6wbi_tlb_fns 240 .long v6_user_fns 241 .long v6_cache_fns 242 .size __v6_proc_info, . - __v6_proc_info 243