xref: /openbmc/linux/arch/arm/mm/proc-v6.S (revision 9c1f8594) 
1/*
2 *  linux/arch/arm/mm/proc-v6.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *  Modified by Catalin Marinas for noMMU support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *  This is the "shell" of the ARMv6 processor support.
12 */
13#include <linux/init.h>
14#include <linux/linkage.h>
15#include <asm/assembler.h>
16#include <asm/asm-offsets.h>
17#include <asm/hwcap.h>
18#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h>
20
21#include "proc-macros.S"
22
23#define D_CACHE_LINE_SIZE	32
24
25#define TTB_C		(1 << 0)
26#define TTB_S		(1 << 1)
27#define TTB_IMP		(1 << 2)
28#define TTB_RGN_NC	(0 << 3)
29#define TTB_RGN_WBWA	(1 << 3)
30#define TTB_RGN_WT	(2 << 3)
31#define TTB_RGN_WB	(3 << 3)
32
33#define TTB_FLAGS_UP	TTB_RGN_WBWA
34#define PMD_FLAGS_UP	PMD_SECT_WB
35#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
36#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
37
38ENTRY(cpu_v6_proc_init)
39	mov	pc, lr
40
41ENTRY(cpu_v6_proc_fin)
42	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
43	bic	r0, r0, #0x1000			@ ...i............
44	bic	r0, r0, #0x0006			@ .............ca.
45	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
46	mov	pc, lr
47
48/*
49 *	cpu_v6_reset(loc)
50 *
51 *	Perform a soft reset of the system.  Put the CPU into the
52 *	same state as it would be if it had been reset, and branch
53 *	to what would be the reset vector.
54 *
55 *	- loc   - location to jump to for soft reset
56 */
57	.align	5
58ENTRY(cpu_v6_reset)
59	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
60	bic	r1, r1, #0x1			@ ...............m
61	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
62	mov	r1, #0
63	mcr	p15, 0, r1, c7, c5, 4		@ ISB
64	mov	pc, r0
65
66/*
67 *	cpu_v6_do_idle()
68 *
69 *	Idle the processor (eg, wait for interrupt).
70 *
71 *	IRQs are already disabled.
72 */
73ENTRY(cpu_v6_do_idle)
74	mov	r1, #0
75	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
76	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
77	mov	pc, lr
78
79ENTRY(cpu_v6_dcache_clean_area)
80#ifndef TLB_CAN_READ_FROM_L1_CACHE
811:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
82	add	r0, r0, #D_CACHE_LINE_SIZE
83	subs	r1, r1, #D_CACHE_LINE_SIZE
84	bhi	1b
85#endif
86	mov	pc, lr
87
88/*
89 *	cpu_arm926_switch_mm(pgd_phys, tsk)
90 *
91 *	Set the translation table base pointer to be pgd_phys
92 *
93 *	- pgd_phys - physical address of new TTB
94 *
95 *	It is assumed that:
96 *	- we are not using split page tables
97 */
98ENTRY(cpu_v6_switch_mm)
99#ifdef CONFIG_MMU
100	mov	r2, #0
101	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
102	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
103	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
104	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
105	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
106	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
107	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
108#endif
109	mov	pc, lr
110
111/*
112 *	cpu_v6_set_pte_ext(ptep, pte, ext)
113 *
114 *	Set a level 2 translation table entry.
115 *
116 *	- ptep  - pointer to level 2 translation table entry
117 *		  (hardware version is stored at -1024 bytes)
118 *	- pte   - PTE value to store
119 *	- ext	- value for extended PTE bits
120 */
121	armv6_mt_table cpu_v6
122
123ENTRY(cpu_v6_set_pte_ext)
124#ifdef CONFIG_MMU
125	armv6_set_pte_ext cpu_v6
126#endif
127	mov	pc, lr
128
129/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
130.globl	cpu_v6_suspend_size
131.equ	cpu_v6_suspend_size, 4 * 8
132#ifdef CONFIG_PM_SLEEP
133ENTRY(cpu_v6_do_suspend)
134	stmfd	sp!, {r4 - r11, lr}
135	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
136	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
137	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
138	mrc	p15, 0, r7, c2, c0, 0	@ Translation table base 0
139	mrc	p15, 0, r8, c2, c0, 1	@ Translation table base 1
140	mrc	p15, 0, r9, c1, c0, 1	@ auxiliary control register
141	mrc	p15, 0, r10, c1, c0, 2	@ co-processor access control
142	mrc	p15, 0, r11, c1, c0, 0	@ control register
143	stmia	r0, {r4 - r11}
144	ldmfd	sp!, {r4- r11, pc}
145ENDPROC(cpu_v6_do_suspend)
146
147ENTRY(cpu_v6_do_resume)
148	mov	ip, #0
149	mcr	p15, 0, ip, c7, c14, 0	@ clean+invalidate D cache
150	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
151	mcr	p15, 0, ip, c7, c15, 0	@ clean+invalidate cache
152	mcr	p15, 0, ip, c7, c10, 4	@ drain write buffer
153	ldmia	r0, {r4 - r11}
154	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
155	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
156	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
157	mcr	p15, 0, r7, c2, c0, 0	@ Translation table base 0
158	mcr	p15, 0, r8, c2, c0, 1	@ Translation table base 1
159	mcr	p15, 0, r9, c1, c0, 1	@ auxiliary control register
160	mcr	p15, 0, r10, c1, c0, 2	@ co-processor access control
161	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
162	mcr	p15, 0, ip, c7, c5, 4	@ ISB
163	mov	r0, r11			@ control register
164	mov	r2, r7, lsr #14		@ get TTB0 base
165	mov	r2, r2, lsl #14
166	ldr	r3, cpu_resume_l1_flags
167	b	cpu_resume_mmu
168ENDPROC(cpu_v6_do_resume)
169cpu_resume_l1_flags:
170	ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
171	ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
172#endif
173
174	string	cpu_v6_name, "ARMv6-compatible processor"
175
176	.align
177
178	__CPUINIT
179
180/*
181 *	__v6_setup
182 *
183 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
184 *	on.  Return in r0 the new CP15 C1 control register setting.
185 *
186 *	We automatically detect if we have a Harvard cache, and use the
187 *	Harvard cache control instructions insead of the unified cache
188 *	control instructions.
189 *
190 *	This should be able to cover all ARMv6 cores.
191 *
192 *	It is assumed that:
193 *	- cache type register is implemented
194 */
195__v6_setup:
196#ifdef CONFIG_SMP
197	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)	@ Enable SMP/nAMP mode
198	ALT_UP(nop)
199	orr	r0, r0, #0x20
200	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
201	ALT_UP(nop)
202#endif
203
204	mov	r0, #0
205	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
206	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
207	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
208	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
209#ifdef CONFIG_MMU
210	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
211	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
212	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
213	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
214	ALT_SMP(orr	r8, r8, #TTB_FLAGS_SMP)
215	ALT_UP(orr	r8, r8, #TTB_FLAGS_UP)
216	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
217#endif /* CONFIG_MMU */
218	adr	r5, v6_crval
219	ldmia	r5, {r5, r6}
220#ifdef CONFIG_CPU_ENDIAN_BE8
221	orr	r6, r6, #1 << 25		@ big-endian page tables
222#endif
223	mrc	p15, 0, r0, c1, c0, 0		@ read control register
224	bic	r0, r0, r5			@ clear bits them
225	orr	r0, r0, r6			@ set them
226#ifdef CONFIG_ARM_ERRATA_364296
227	/*
228	 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
229	 * corruption with hit-under-miss enabled). The conditional code below
230	 * (setting the undocumented bit 31 in the auxiliary control register
231	 * and the FI bit in the control register) disables hit-under-miss
232	 * without putting the processor into full low interrupt latency mode.
233	 */
234	ldr	r6, =0x4107b362			@ id for ARM1136 r0p2
235	mrc	p15, 0, r5, c0, c0, 0		@ get processor id
236	teq	r5, r6				@ check for the faulty core
237	mrceq	p15, 0, r5, c1, c0, 1		@ load aux control reg
238	orreq	r5, r5, #(1 << 31)		@ set the undocumented bit 31
239	mcreq	p15, 0, r5, c1, c0, 1		@ write aux control reg
240	orreq	r0, r0, #(1 << 21)		@ low interrupt latency configuration
241#endif
242	mov	pc, lr				@ return to head.S:__ret
243
244	/*
245	 *         V X F   I D LR
246	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
247	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
248	 *         0 110       0011 1.00 .111 1101 < we want
249	 */
250	.type	v6_crval, #object
251v6_crval:
252	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
253
254	__INITDATA
255
256	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
257	define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
258
259	.section ".rodata"
260
261	string	cpu_arch_name, "armv6"
262	string	cpu_elf_name, "v6"
263	.align
264
265	.section ".proc.info.init", #alloc, #execinstr
266
267	/*
268	 * Match any ARMv6 processor core.
269	 */
270	.type	__v6_proc_info, #object
271__v6_proc_info:
272	.long	0x0007b000
273	.long	0x0007f000
274	ALT_SMP(.long \
275		PMD_TYPE_SECT | \
276		PMD_SECT_AP_WRITE | \
277		PMD_SECT_AP_READ | \
278		PMD_FLAGS_SMP)
279	ALT_UP(.long \
280		PMD_TYPE_SECT | \
281		PMD_SECT_AP_WRITE | \
282		PMD_SECT_AP_READ | \
283		PMD_FLAGS_UP)
284	.long   PMD_TYPE_SECT | \
285		PMD_SECT_XN | \
286		PMD_SECT_AP_WRITE | \
287		PMD_SECT_AP_READ
288	b	__v6_setup
289	.long	cpu_arch_name
290	.long	cpu_elf_name
291	/* See also feat_v6_fixup() for HWCAP_TLS */
292	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
293	.long	cpu_v6_name
294	.long	v6_processor_functions
295	.long	v6wbi_tlb_fns
296	.long	v6_user_fns
297	.long	v6_cache_fns
298	.size	__v6_proc_info, . - __v6_proc_info
299