1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv6 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/hwcap.h> 18#include <asm/pgtable-hwdef.h> 19#include <asm/pgtable.h> 20 21#include "proc-macros.S" 22 23#define D_CACHE_LINE_SIZE 32 24 25#define TTB_C (1 << 0) 26#define TTB_S (1 << 1) 27#define TTB_IMP (1 << 2) 28#define TTB_RGN_NC (0 << 3) 29#define TTB_RGN_WBWA (1 << 3) 30#define TTB_RGN_WT (2 << 3) 31#define TTB_RGN_WB (3 << 3) 32 33#define TTB_FLAGS_UP TTB_RGN_WBWA 34#define PMD_FLAGS_UP PMD_SECT_WB 35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S 36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 37 38ENTRY(cpu_v6_proc_init) 39 mov pc, lr 40 41ENTRY(cpu_v6_proc_fin) 42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 43 bic r0, r0, #0x1000 @ ...i............ 44 bic r0, r0, #0x0006 @ .............ca. 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 46 mov pc, lr 47 48/* 49 * cpu_v6_reset(loc) 50 * 51 * Perform a soft reset of the system. Put the CPU into the 52 * same state as it would be if it had been reset, and branch 53 * to what would be the reset vector. 54 * 55 * - loc - location to jump to for soft reset 56 */ 57 .align 5 58ENTRY(cpu_v6_reset) 59 mov pc, r0 60 61/* 62 * cpu_v6_do_idle() 63 * 64 * Idle the processor (eg, wait for interrupt). 65 * 66 * IRQs are already disabled. 67 */ 68ENTRY(cpu_v6_do_idle) 69 mov r1, #0 70 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 71 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 72 mov pc, lr 73 74ENTRY(cpu_v6_dcache_clean_area) 75#ifndef TLB_CAN_READ_FROM_L1_CACHE 761: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 77 add r0, r0, #D_CACHE_LINE_SIZE 78 subs r1, r1, #D_CACHE_LINE_SIZE 79 bhi 1b 80#endif 81 mov pc, lr 82 83/* 84 * cpu_arm926_switch_mm(pgd_phys, tsk) 85 * 86 * Set the translation table base pointer to be pgd_phys 87 * 88 * - pgd_phys - physical address of new TTB 89 * 90 * It is assumed that: 91 * - we are not using split page tables 92 */ 93ENTRY(cpu_v6_switch_mm) 94#ifdef CONFIG_MMU 95 mov r2, #0 96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 97 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 98 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 99 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 100 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 101 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 102 mcr p15, 0, r1, c13, c0, 1 @ set context ID 103#endif 104 mov pc, lr 105 106/* 107 * cpu_v6_set_pte_ext(ptep, pte, ext) 108 * 109 * Set a level 2 translation table entry. 110 * 111 * - ptep - pointer to level 2 translation table entry 112 * (hardware version is stored at -1024 bytes) 113 * - pte - PTE value to store 114 * - ext - value for extended PTE bits 115 */ 116 armv6_mt_table cpu_v6 117 118ENTRY(cpu_v6_set_pte_ext) 119#ifdef CONFIG_MMU 120 armv6_set_pte_ext cpu_v6 121#endif 122 mov pc, lr 123 124 125 126 .type cpu_v6_name, #object 127cpu_v6_name: 128 .asciz "ARMv6-compatible processor" 129 .size cpu_v6_name, . - cpu_v6_name 130 131 .type cpu_pj4_name, #object 132cpu_pj4_name: 133 .asciz "Marvell PJ4 processor" 134 .size cpu_pj4_name, . - cpu_pj4_name 135 136 .align 137 138 __CPUINIT 139 140/* 141 * __v6_setup 142 * 143 * Initialise TLB, Caches, and MMU state ready to switch the MMU 144 * on. Return in r0 the new CP15 C1 control register setting. 145 * 146 * We automatically detect if we have a Harvard cache, and use the 147 * Harvard cache control instructions insead of the unified cache 148 * control instructions. 149 * 150 * This should be able to cover all ARMv6 cores. 151 * 152 * It is assumed that: 153 * - cache type register is implemented 154 */ 155__v6_setup: 156#ifdef CONFIG_SMP 157 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode 158 ALT_UP(nop) 159 orr r0, r0, #0x20 160 ALT_SMP(mcr p15, 0, r0, c1, c0, 1) 161 ALT_UP(nop) 162#endif 163 164 mov r0, #0 165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 169#ifdef CONFIG_MMU 170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 172 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 173 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 174 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 175#endif /* CONFIG_MMU */ 176 adr r5, v6_crval 177 ldmia r5, {r5, r6} 178#ifdef CONFIG_CPU_ENDIAN_BE8 179 orr r6, r6, #1 << 25 @ big-endian page tables 180#endif 181 mrc p15, 0, r0, c1, c0, 0 @ read control register 182 bic r0, r0, r5 @ clear bits them 183 orr r0, r0, r6 @ set them 184 mov pc, lr @ return to head.S:__ret 185 186 /* 187 * V X F I D LR 188 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM 189 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 190 * 0 110 0011 1.00 .111 1101 < we want 191 */ 192 .type v6_crval, #object 193v6_crval: 194 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 195 196 __INITDATA 197 198 .type v6_processor_functions, #object 199ENTRY(v6_processor_functions) 200 .word v6_early_abort 201 .word v6_pabort 202 .word cpu_v6_proc_init 203 .word cpu_v6_proc_fin 204 .word cpu_v6_reset 205 .word cpu_v6_do_idle 206 .word cpu_v6_dcache_clean_area 207 .word cpu_v6_switch_mm 208 .word cpu_v6_set_pte_ext 209 .size v6_processor_functions, . - v6_processor_functions 210 211 .section ".rodata" 212 213 .type cpu_arch_name, #object 214cpu_arch_name: 215 .asciz "armv6" 216 .size cpu_arch_name, . - cpu_arch_name 217 218 .type cpu_elf_name, #object 219cpu_elf_name: 220 .asciz "v6" 221 .size cpu_elf_name, . - cpu_elf_name 222 .align 223 224 .section ".proc.info.init", #alloc, #execinstr 225 226 /* 227 * Match any ARMv6 processor core. 228 */ 229 .type __v6_proc_info, #object 230__v6_proc_info: 231 .long 0x0007b000 232 .long 0x0007f000 233 ALT_SMP(.long \ 234 PMD_TYPE_SECT | \ 235 PMD_SECT_AP_WRITE | \ 236 PMD_SECT_AP_READ | \ 237 PMD_FLAGS_SMP) 238 ALT_UP(.long \ 239 PMD_TYPE_SECT | \ 240 PMD_SECT_AP_WRITE | \ 241 PMD_SECT_AP_READ | \ 242 PMD_FLAGS_UP) 243 .long PMD_TYPE_SECT | \ 244 PMD_SECT_XN | \ 245 PMD_SECT_AP_WRITE | \ 246 PMD_SECT_AP_READ 247 b __v6_setup 248 .long cpu_arch_name 249 .long cpu_elf_name 250 /* See also feat_v6_fixup() for HWCAP_TLS */ 251 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS 252 .long cpu_v6_name 253 .long v6_processor_functions 254 .long v6wbi_tlb_fns 255 .long v6_user_fns 256 .long v6_cache_fns 257 .size __v6_proc_info, . - __v6_proc_info 258 259 .type __pj4_v6_proc_info, #object 260__pj4_v6_proc_info: 261 .long 0x560f5810 262 .long 0xff0ffff0 263 ALT_SMP(.long \ 264 PMD_TYPE_SECT | \ 265 PMD_SECT_AP_WRITE | \ 266 PMD_SECT_AP_READ | \ 267 PMD_FLAGS_SMP) 268 ALT_UP(.long \ 269 PMD_TYPE_SECT | \ 270 PMD_SECT_AP_WRITE | \ 271 PMD_SECT_AP_READ | \ 272 PMD_FLAGS_UP) 273 .long PMD_TYPE_SECT | \ 274 PMD_SECT_XN | \ 275 PMD_SECT_AP_WRITE | \ 276 PMD_SECT_AP_READ 277 b __v6_setup 278 .long cpu_arch_name 279 .long cpu_elf_name 280 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 281 .long cpu_pj4_name 282 .long v6_processor_functions 283 .long v6wbi_tlb_fns 284 .long v6_user_fns 285 .long v6_cache_fns 286 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info 287