xref: /openbmc/linux/arch/arm/mm/proc-v6.S (revision 3366e358) 
1/*
2 *  linux/arch/arm/mm/proc-v6.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *  Modified by Catalin Marinas for noMMU support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *  This is the "shell" of the ARMv6 processor support.
12 */
13#include <linux/init.h>
14#include <linux/linkage.h>
15#include <asm/assembler.h>
16#include <asm/asm-offsets.h>
17#include <asm/hwcap.h>
18#include <asm/pgtable-hwdef.h>
19#include <asm/pgtable.h>
20
21#include "proc-macros.S"
22
23#define D_CACHE_LINE_SIZE	32
24
25#define TTB_C		(1 << 0)
26#define TTB_S		(1 << 1)
27#define TTB_IMP		(1 << 2)
28#define TTB_RGN_NC	(0 << 3)
29#define TTB_RGN_WBWA	(1 << 3)
30#define TTB_RGN_WT	(2 << 3)
31#define TTB_RGN_WB	(3 << 3)
32
33#ifndef CONFIG_SMP
34#define TTB_FLAGS	TTB_RGN_WBWA
35#define PMD_FLAGS	PMD_SECT_WB
36#else
37#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
39#endif
40
41ENTRY(cpu_v6_proc_init)
42	mov	pc, lr
43
44ENTRY(cpu_v6_proc_fin)
45	stmfd	sp!, {lr}
46	cpsid	if				@ disable interrupts
47	bl	v6_flush_kern_cache_all
48	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
49	bic	r0, r0, #0x1000			@ ...i............
50	bic	r0, r0, #0x0006			@ .............ca.
51	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
52	ldmfd	sp!, {pc}
53
54/*
55 *	cpu_v6_reset(loc)
56 *
57 *	Perform a soft reset of the system.  Put the CPU into the
58 *	same state as it would be if it had been reset, and branch
59 *	to what would be the reset vector.
60 *
61 *	- loc   - location to jump to for soft reset
62 */
63	.align	5
64ENTRY(cpu_v6_reset)
65	mov	pc, r0
66
67/*
68 *	cpu_v6_do_idle()
69 *
70 *	Idle the processor (eg, wait for interrupt).
71 *
72 *	IRQs are already disabled.
73 */
74ENTRY(cpu_v6_do_idle)
75	mov	r1, #0
76	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
77	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
78	mov	pc, lr
79
80ENTRY(cpu_v6_dcache_clean_area)
81#ifndef TLB_CAN_READ_FROM_L1_CACHE
821:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
83	add	r0, r0, #D_CACHE_LINE_SIZE
84	subs	r1, r1, #D_CACHE_LINE_SIZE
85	bhi	1b
86#endif
87	mov	pc, lr
88
89/*
90 *	cpu_arm926_switch_mm(pgd_phys, tsk)
91 *
92 *	Set the translation table base pointer to be pgd_phys
93 *
94 *	- pgd_phys - physical address of new TTB
95 *
96 *	It is assumed that:
97 *	- we are not using split page tables
98 */
99ENTRY(cpu_v6_switch_mm)
100#ifdef CONFIG_MMU
101	mov	r2, #0
102	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
103	orr	r0, r0, #TTB_FLAGS
104	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
105	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
106	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
107	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
108#endif
109	mov	pc, lr
110
111/*
112 *	cpu_v6_set_pte_ext(ptep, pte, ext)
113 *
114 *	Set a level 2 translation table entry.
115 *
116 *	- ptep  - pointer to level 2 translation table entry
117 *		  (hardware version is stored at -1024 bytes)
118 *	- pte   - PTE value to store
119 *	- ext	- value for extended PTE bits
120 */
121	armv6_mt_table cpu_v6
122
123ENTRY(cpu_v6_set_pte_ext)
124#ifdef CONFIG_MMU
125	armv6_set_pte_ext cpu_v6
126#endif
127	mov	pc, lr
128
129
130
131	.type	cpu_v6_name, #object
132cpu_v6_name:
133	.asciz	"ARMv6-compatible processor"
134	.size	cpu_v6_name, . - cpu_v6_name
135
136	.type	cpu_pj4_name, #object
137cpu_pj4_name:
138	.asciz	"Marvell PJ4 processor"
139	.size	cpu_pj4_name, . - cpu_pj4_name
140
141	.align
142
143	__INIT
144
145/*
146 *	__v6_setup
147 *
148 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
149 *	on.  Return in r0 the new CP15 C1 control register setting.
150 *
151 *	We automatically detect if we have a Harvard cache, and use the
152 *	Harvard cache control instructions insead of the unified cache
153 *	control instructions.
154 *
155 *	This should be able to cover all ARMv6 cores.
156 *
157 *	It is assumed that:
158 *	- cache type register is implemented
159 */
160__v6_setup:
161#ifdef CONFIG_SMP
162	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
163	orr	r0, r0, #0x20
164	mcr	p15, 0, r0, c1, c0, 1
165#endif
166
167	mov	r0, #0
168	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
169	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
170	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
171	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
172#ifdef CONFIG_MMU
173	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
174	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
175	orr	r4, r4, #TTB_FLAGS
176	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
177#endif /* CONFIG_MMU */
178	adr	r5, v6_crval
179	ldmia	r5, {r5, r6}
180#ifdef CONFIG_CPU_ENDIAN_BE8
181	orr	r6, r6, #1 << 25		@ big-endian page tables
182#endif
183	mrc	p15, 0, r0, c1, c0, 0		@ read control register
184	bic	r0, r0, r5			@ clear bits them
185	orr	r0, r0, r6			@ set them
186	mov	pc, lr				@ return to head.S:__ret
187
188	/*
189	 *         V X F   I D LR
190	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
191	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
192	 *         0 110       0011 1.00 .111 1101 < we want
193	 */
194	.type	v6_crval, #object
195v6_crval:
196	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
197
198	.type	v6_processor_functions, #object
199ENTRY(v6_processor_functions)
200	.word	v6_early_abort
201	.word	v6_pabort
202	.word	cpu_v6_proc_init
203	.word	cpu_v6_proc_fin
204	.word	cpu_v6_reset
205	.word	cpu_v6_do_idle
206	.word	cpu_v6_dcache_clean_area
207	.word	cpu_v6_switch_mm
208	.word	cpu_v6_set_pte_ext
209	.size	v6_processor_functions, . - v6_processor_functions
210
211	.type	cpu_arch_name, #object
212cpu_arch_name:
213	.asciz	"armv6"
214	.size	cpu_arch_name, . - cpu_arch_name
215
216	.type	cpu_elf_name, #object
217cpu_elf_name:
218	.asciz	"v6"
219	.size	cpu_elf_name, . - cpu_elf_name
220	.align
221
222	.section ".proc.info.init", #alloc, #execinstr
223
224	/*
225	 * Match any ARMv6 processor core.
226	 */
227	.type	__v6_proc_info, #object
228__v6_proc_info:
229	.long	0x0007b000
230	.long	0x0007f000
231	.long   PMD_TYPE_SECT | \
232		PMD_SECT_AP_WRITE | \
233		PMD_SECT_AP_READ | \
234		PMD_FLAGS
235	.long   PMD_TYPE_SECT | \
236		PMD_SECT_XN | \
237		PMD_SECT_AP_WRITE | \
238		PMD_SECT_AP_READ
239	b	__v6_setup
240	.long	cpu_arch_name
241	.long	cpu_elf_name
242	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
243	.long	cpu_v6_name
244	.long	v6_processor_functions
245	.long	v6wbi_tlb_fns
246	.long	v6_user_fns
247	.long	v6_cache_fns
248	.size	__v6_proc_info, . - __v6_proc_info
249
250	.type	__pj4_v6_proc_info, #object
251__pj4_v6_proc_info:
252	.long	0x560f5810
253	.long	0xff0ffff0
254	.long   PMD_TYPE_SECT | \
255		PMD_SECT_AP_WRITE | \
256		PMD_SECT_AP_READ | \
257		PMD_FLAGS
258	.long   PMD_TYPE_SECT | \
259		PMD_SECT_XN | \
260		PMD_SECT_AP_WRITE | \
261		PMD_SECT_AP_READ
262	b	__v6_setup
263	.long	cpu_arch_name
264	.long	cpu_elf_name
265	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
266	.long	cpu_pj4_name
267	.long	v6_processor_functions
268	.long	v6wbi_tlb_fns
269	.long	v6_user_fns
270	.long	v6_cache_fns
271	.size	__pj4_v6_proc_info, . - __pj4_v6_proc_info
272