1/* 2 * linux/arch/arm/mm/proc-sa1100.S 3 * 4 * Copyright (C) 1997-2002 Russell King 5 * hacked for non-paged-MM by Hyok S. Choi, 2003. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * MMU functions for SA110 12 * 13 * These are the low level assembler for performing cache and TLB 14 * functions on the StrongARM-1100 and StrongARM-1110. 15 * 16 * Note that SA1100 and SA1110 share everything but their name and CPU ID. 17 * 18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl): 19 * Flush the read buffer at context switches 20 */ 21#include <linux/linkage.h> 22#include <linux/init.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/elf.h> 26#include <asm/hardware.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable.h> 29 30#include "proc-macros.S" 31 32/* 33 * the cache line size of the I and D cache 34 */ 35#define DCACHELINESIZE 32 36 37 __INIT 38 39/* 40 * cpu_sa1100_proc_init() 41 */ 42ENTRY(cpu_sa1100_proc_init) 43 mov r0, #0 44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 46 mov pc, lr 47 48 .previous 49 50/* 51 * cpu_sa1100_proc_fin() 52 * 53 * Prepare the CPU for reset: 54 * - Disable interrupts 55 * - Clean and turn off caches. 56 */ 57ENTRY(cpu_sa1100_proc_fin) 58 stmfd sp!, {lr} 59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 60 msr cpsr_c, ip 61 bl v4wb_flush_kern_cache_all 62 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 63 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 64 bic r0, r0, #0x1000 @ ...i............ 65 bic r0, r0, #0x000e @ ............wca. 66 mcr p15, 0, r0, c1, c0, 0 @ disable caches 67 ldmfd sp!, {pc} 68 69/* 70 * cpu_sa1100_reset(loc) 71 * 72 * Perform a soft reset of the system. Put the CPU into the 73 * same state as it would be if it had been reset, and branch 74 * to what would be the reset vector. 75 * 76 * loc: location to jump to for soft reset 77 */ 78 .align 5 79ENTRY(cpu_sa1100_reset) 80 mov ip, #0 81 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 82 mcr p15, 0, ip, c7, c10, 4 @ drain WB 83#ifdef CONFIG_MMU 84 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 85#endif 86 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 87 bic ip, ip, #0x000f @ ............wcam 88 bic ip, ip, #0x1100 @ ...i...s........ 89 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 90 mov pc, r0 91 92/* 93 * cpu_sa1100_do_idle(type) 94 * 95 * Cause the processor to idle 96 * 97 * type: call type: 98 * 0 = slow idle 99 * 1 = fast idle 100 * 2 = switch to slow processor clock 101 * 3 = switch to fast processor clock 102 */ 103 .align 5 104ENTRY(cpu_sa1100_do_idle) 105 mov r0, r0 @ 4 nop padding 106 mov r0, r0 107 mov r0, r0 108 mov r0, r0 @ 4 nop padding 109 mov r0, r0 110 mov r0, r0 111 mov r0, #0 112 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address 113 @ --- aligned to a cache line 114 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 115 ldr r1, [r1, #0] @ force switch to MCLK 116 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt 117 mov r0, r0 @ safety 118 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching 119 mov pc, lr 120 121/* ================================= CACHE ================================ */ 122 123/* 124 * cpu_sa1100_dcache_clean_area(addr,sz) 125 * 126 * Clean the specified entry of any caches such that the MMU 127 * translation fetches will obtain correct data. 128 * 129 * addr: cache-unaligned virtual address 130 */ 131 .align 5 132ENTRY(cpu_sa1100_dcache_clean_area) 1331: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 134 add r0, r0, #DCACHELINESIZE 135 subs r1, r1, #DCACHELINESIZE 136 bhi 1b 137 mov pc, lr 138 139/* =============================== PageTable ============================== */ 140 141/* 142 * cpu_sa1100_switch_mm(pgd) 143 * 144 * Set the translation base pointer to be as described by pgd. 145 * 146 * pgd: new page tables 147 */ 148 .align 5 149ENTRY(cpu_sa1100_switch_mm) 150#ifdef CONFIG_MMU 151 str lr, [sp, #-4]! 152 bl v4wb_flush_kern_cache_all @ clears IP 153 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 154 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 156 ldr pc, [sp], #4 157#else 158 mov pc, lr 159#endif 160 161/* 162 * cpu_sa1100_set_pte_ext(ptep, pte, ext) 163 * 164 * Set a PTE and flush it out 165 */ 166 .align 5 167ENTRY(cpu_sa1100_set_pte_ext) 168#ifdef CONFIG_MMU 169 str r1, [r0], #-2048 @ linux version 170 171 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 172 173 bic r2, r1, #PTE_SMALL_AP_MASK 174 bic r2, r2, #PTE_TYPE_MASK 175 orr r2, r2, #PTE_TYPE_SMALL 176 177 tst r1, #L_PTE_USER @ User? 178 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 179 180 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 181 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 182 183 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 184 movne r2, #0 185 186 str r2, [r0] @ hardware version 187 mov r0, r0 188 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 189 mcr p15, 0, r0, c7, c10, 4 @ drain WB 190#endif 191 mov pc, lr 192 193 __INIT 194 195 .type __sa1100_setup, #function 196__sa1100_setup: 197 mov r0, #0 198 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 199 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 200#ifdef CONFIG_MMU 201 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 202#endif 203 adr r5, sa1100_crval 204 ldmia r5, {r5, r6} 205 mrc p15, 0, r0, c1, c0 @ get control register v4 206 bic r0, r0, r5 207 orr r0, r0, r6 208 mov pc, lr 209 .size __sa1100_setup, . - __sa1100_setup 210 211 /* 212 * R 213 * .RVI ZFRS BLDP WCAM 214 * ..11 0001 ..11 1101 215 * 216 */ 217 .type sa1100_crval, #object 218sa1100_crval: 219 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130 220 221 __INITDATA 222 223/* 224 * Purpose : Function pointers used to access above functions - all calls 225 * come through these 226 */ 227 228/* 229 * SA1100 and SA1110 share the same function calls 230 */ 231 .type sa1100_processor_functions, #object 232ENTRY(sa1100_processor_functions) 233 .word v4_early_abort 234 .word pabort_noifar 235 .word cpu_sa1100_proc_init 236 .word cpu_sa1100_proc_fin 237 .word cpu_sa1100_reset 238 .word cpu_sa1100_do_idle 239 .word cpu_sa1100_dcache_clean_area 240 .word cpu_sa1100_switch_mm 241 .word cpu_sa1100_set_pte_ext 242 .size sa1100_processor_functions, . - sa1100_processor_functions 243 244 .section ".rodata" 245 246 .type cpu_arch_name, #object 247cpu_arch_name: 248 .asciz "armv4" 249 .size cpu_arch_name, . - cpu_arch_name 250 251 .type cpu_elf_name, #object 252cpu_elf_name: 253 .asciz "v4" 254 .size cpu_elf_name, . - cpu_elf_name 255 256 .type cpu_sa1100_name, #object 257cpu_sa1100_name: 258 .asciz "StrongARM-1100" 259 .size cpu_sa1100_name, . - cpu_sa1100_name 260 261 .type cpu_sa1110_name, #object 262cpu_sa1110_name: 263 .asciz "StrongARM-1110" 264 .size cpu_sa1110_name, . - cpu_sa1110_name 265 266 .align 267 268 .section ".proc.info.init", #alloc, #execinstr 269 270 .type __sa1100_proc_info,#object 271__sa1100_proc_info: 272 .long 0x4401a110 273 .long 0xfffffff0 274 .long PMD_TYPE_SECT | \ 275 PMD_SECT_BUFFERABLE | \ 276 PMD_SECT_CACHEABLE | \ 277 PMD_SECT_AP_WRITE | \ 278 PMD_SECT_AP_READ 279 .long PMD_TYPE_SECT | \ 280 PMD_SECT_AP_WRITE | \ 281 PMD_SECT_AP_READ 282 b __sa1100_setup 283 .long cpu_arch_name 284 .long cpu_elf_name 285 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT 286 .long cpu_sa1100_name 287 .long sa1100_processor_functions 288 .long v4wb_tlb_fns 289 .long v4_mc_user_fns 290 .long v4wb_cache_fns 291 .size __sa1100_proc_info, . - __sa1100_proc_info 292 293 .type __sa1110_proc_info,#object 294__sa1110_proc_info: 295 .long 0x6901b110 296 .long 0xfffffff0 297 .long PMD_TYPE_SECT | \ 298 PMD_SECT_BUFFERABLE | \ 299 PMD_SECT_CACHEABLE | \ 300 PMD_SECT_AP_WRITE | \ 301 PMD_SECT_AP_READ 302 .long PMD_TYPE_SECT | \ 303 PMD_SECT_AP_WRITE | \ 304 PMD_SECT_AP_READ 305 b __sa1100_setup 306 .long cpu_arch_name 307 .long cpu_elf_name 308 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT 309 .long cpu_sa1110_name 310 .long sa1100_processor_functions 311 .long v4wb_tlb_fns 312 .long v4_mc_user_fns 313 .long v4wb_cache_fns 314 .size __sa1110_proc_info, . - __sa1110_proc_info 315