xref: /openbmc/linux/arch/arm/mm/proc-sa1100.S (revision 1da177e4) 
1/*
2 *  linux/arch/arm/mm/proc-sa1100.S
3 *
4 *  Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  MMU functions for SA110
11 *
12 *  These are the low level assembler for performing cache and TLB
13 *  functions on the StrongARM-1100 and StrongARM-1110.
14 *
15 *  Note that SA1100 and SA1110 share everything but their name and CPU ID.
16 *
17 *  12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
18 *    Flush the read buffer at context switches
19 */
20#include <linux/linkage.h>
21#include <linux/init.h>
22#include <asm/assembler.h>
23#include <asm/constants.h>
24#include <asm/procinfo.h>
25#include <asm/hardware.h>
26#include <asm/pgtable.h>
27
28/*
29 * the cache line size of the I and D cache
30 */
31#define DCACHELINESIZE	32
32#define FLUSH_OFFSET	32768
33
34	.macro flush_1100_dcache rd, ra, re
35	ldr	\rd, =flush_base
36	ldr	\ra, [\rd]
37	eor	\ra, \ra, #FLUSH_OFFSET
38	str	\ra, [\rd]
39	add	\re, \ra, #8192			@ only necessary for 8k
401001:	ldr	\rd, [\ra], #DCACHELINESIZE
41	teq	\re, \ra
42	bne	1001b
43#ifdef FLUSH_BASE_MINICACHE
44	add	\ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
45	add	\re, \ra, #512			@ only 512 bytes
461002:	ldr	\rd, [\ra], #DCACHELINESIZE
47	teq	\re, \ra
48	bne	1002b
49#endif
50	.endm
51
52	.data
53flush_base:
54	.long	FLUSH_BASE
55	.text
56
57	__INIT
58
59/*
60 * cpu_sa1100_proc_init()
61 */
62ENTRY(cpu_sa1100_proc_init)
63	mov	r0, #0
64	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
65	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
66	mov	pc, lr
67
68	.previous
69
70/*
71 * cpu_sa1100_proc_fin()
72 *
73 * Prepare the CPU for reset:
74 *  - Disable interrupts
75 *  - Clean and turn off caches.
76 */
77ENTRY(cpu_sa1100_proc_fin)
78	stmfd	sp!, {lr}
79	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
80	msr	cpsr_c, ip
81	flush_1100_dcache r0, r1, r2		@ clean caches
82	mov	r0, #0
83	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
84	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
85	bic	r0, r0, #0x1000			@ ...i............
86	bic	r0, r0, #0x000e			@ ............wca.
87	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
88	ldmfd	sp!, {pc}
89
90/*
91 * cpu_sa1100_reset(loc)
92 *
93 * Perform a soft reset of the system.  Put the CPU into the
94 * same state as it would be if it had been reset, and branch
95 * to what would be the reset vector.
96 *
97 * loc: location to jump to for soft reset
98 */
99	.align	5
100ENTRY(cpu_sa1100_reset)
101	mov	ip, #0
102	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
103	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
104	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
105	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
106	bic	ip, ip, #0x000f			@ ............wcam
107	bic	ip, ip, #0x1100			@ ...i...s........
108	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
109	mov	pc, r0
110
111/*
112 * cpu_sa1100_do_idle(type)
113 *
114 * Cause the processor to idle
115 *
116 * type: call type:
117 *   0 = slow idle
118 *   1 = fast idle
119 *   2 = switch to slow processor clock
120 *   3 = switch to fast processor clock
121 */
122	.align	5
123ENTRY(cpu_sa1100_do_idle)
124	mov	r0, r0				@ 4 nop padding
125	mov	r0, r0
126	mov	r0, r0
127	mov	r0, r0				@ 4 nop padding
128	mov	r0, r0
129	mov	r0, r0
130	mov	r0, #0
131	ldr	r1, =UNCACHEABLE_ADDR		@ ptr to uncacheable address
132	@ --- aligned to a cache line
133	mcr	p15, 0, r0, c15, c2, 2		@ disable clock switching
134	ldr	r1, [r1, #0]			@ force switch to MCLK
135	mcr	p15, 0, r0, c15, c8, 2		@ wait for interrupt
136	mov	r0, r0				@ safety
137	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
138	mov	pc, lr
139
140/* ================================= CACHE ================================ */
141
142/*
143 * cpu_sa1100_dcache_clean_area(addr,sz)
144 *
145 * Clean the specified entry of any caches such that the MMU
146 * translation fetches will obtain correct data.
147 *
148 * addr: cache-unaligned virtual address
149 */
150	.align	5
151ENTRY(cpu_sa1100_dcache_clean_area)
1521:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
153	add	r0, r0, #DCACHELINESIZE
154	subs	r1, r1, #DCACHELINESIZE
155	bhi	1b
156	mov	pc, lr
157
158/* =============================== PageTable ============================== */
159
160/*
161 * cpu_sa1100_switch_mm(pgd)
162 *
163 * Set the translation base pointer to be as described by pgd.
164 *
165 * pgd: new page tables
166 */
167	.align	5
168ENTRY(cpu_sa1100_switch_mm)
169	flush_1100_dcache r3, ip, r1
170	mov	ip, #0
171	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
172	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
173	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
174	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
175	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
176	mov	pc, lr
177
178/*
179 * cpu_sa1100_set_pte(ptep, pte)
180 *
181 * Set a PTE and flush it out
182 */
183	.align	5
184ENTRY(cpu_sa1100_set_pte)
185	str	r1, [r0], #-2048		@ linux version
186
187	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
188
189	bic	r2, r1, #PTE_SMALL_AP_MASK
190	bic	r2, r2, #PTE_TYPE_MASK
191	orr	r2, r2, #PTE_TYPE_SMALL
192
193	tst	r1, #L_PTE_USER			@ User?
194	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
195
196	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
197	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
198
199	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
200	movne	r2, #0
201
202	str	r2, [r0]			@ hardware version
203	mov	r0, r0
204	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
205	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
206	mov	pc, lr
207
208	__INIT
209
210	.type	__sa1100_setup, #function
211__sa1100_setup:
212	mov	r0, #0
213	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
214	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
215	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
216	mrc	p15, 0, r0, c1, c0		@ get control register v4
217	ldr	r5, sa1100_cr1_clear
218	bic	r0, r0, r5
219	ldr	r5, sa1100_cr1_set
220	orr	r0, r0, r5
221	mov	pc, lr
222	.size	__sa1100_setup, . - __sa1100_setup
223
224	/*
225	 *  R
226	 * .RVI ZFRS BLDP WCAM
227	 * ..11 0001 ..11 1101
228	 *
229	 */
230	.type	sa1100_cr1_clear, #object
231	.type	sa1100_cr1_set, #object
232sa1100_cr1_clear:
233	.word	0x3f3f
234sa1100_cr1_set:
235	.word	0x313d
236
237	__INITDATA
238
239/*
240 * Purpose : Function pointers used to access above functions - all calls
241 *	     come through these
242 */
243
244/*
245 * SA1100 and SA1110 share the same function calls
246 */
247	.type	sa1100_processor_functions, #object
248ENTRY(sa1100_processor_functions)
249	.word	v4_early_abort
250	.word	cpu_sa1100_proc_init
251	.word	cpu_sa1100_proc_fin
252	.word	cpu_sa1100_reset
253	.word	cpu_sa1100_do_idle
254	.word	cpu_sa1100_dcache_clean_area
255	.word	cpu_sa1100_switch_mm
256	.word	cpu_sa1100_set_pte
257	.size	sa1100_processor_functions, . - sa1100_processor_functions
258
259	.section ".rodata"
260
261	.type	cpu_arch_name, #object
262cpu_arch_name:
263	.asciz	"armv4"
264	.size	cpu_arch_name, . - cpu_arch_name
265
266	.type	cpu_elf_name, #object
267cpu_elf_name:
268	.asciz	"v4"
269	.size	cpu_elf_name, . - cpu_elf_name
270
271	.type	cpu_sa1100_name, #object
272cpu_sa1100_name:
273	.asciz	"StrongARM-1100"
274	.size	cpu_sa1100_name, . - cpu_sa1100_name
275
276	.type	cpu_sa1110_name, #object
277cpu_sa1110_name:
278	.asciz	"StrongARM-1110"
279	.size	cpu_sa1110_name, . - cpu_sa1110_name
280
281	.align
282
283	.section ".proc.info", #alloc, #execinstr
284
285	.type	__sa1100_proc_info,#object
286__sa1100_proc_info:
287	.long	0x4401a110
288	.long	0xfffffff0
289	.long   PMD_TYPE_SECT | \
290		PMD_SECT_BUFFERABLE | \
291		PMD_SECT_CACHEABLE | \
292		PMD_SECT_AP_WRITE | \
293		PMD_SECT_AP_READ
294	b	__sa1100_setup
295	.long	cpu_arch_name
296	.long	cpu_elf_name
297	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
298	.long	cpu_sa1100_name
299	.long	sa1100_processor_functions
300	.long	v4wb_tlb_fns
301	.long	v4_mc_user_fns
302	.long	v4wb_cache_fns
303	.size	__sa1100_proc_info, . - __sa1100_proc_info
304
305	.type	__sa1110_proc_info,#object
306__sa1110_proc_info:
307	.long	0x6901b110
308	.long	0xfffffff0
309	.long   PMD_TYPE_SECT | \
310		PMD_SECT_BUFFERABLE | \
311		PMD_SECT_CACHEABLE | \
312		PMD_SECT_AP_WRITE | \
313		PMD_SECT_AP_READ
314	b	__sa1100_setup
315	.long	cpu_arch_name
316	.long	cpu_elf_name
317	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
318	.long	cpu_sa1110_name
319	.long	sa1100_processor_functions
320	.long	v4wb_tlb_fns
321	.long	v4_mc_user_fns
322	.long	v4wb_cache_fns
323	.size	__sa1110_proc_info, . - __sa1110_proc_info
324