xref: /openbmc/linux/arch/arm/mm/proc-sa110.S (revision 95e9fd10) 
1/*
2 *  linux/arch/arm/mm/proc-sa110.S
3 *
4 *  Copyright (C) 1997-2002 Russell King
5 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *  MMU functions for SA110
12 *
13 *  These are the low level assembler for performing cache and TLB
14 *  functions on the StrongARM-110.
15 */
16#include <linux/linkage.h>
17#include <linux/init.h>
18#include <asm/assembler.h>
19#include <asm/asm-offsets.h>
20#include <asm/hwcap.h>
21#include <mach/hardware.h>
22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h>
24#include <asm/ptrace.h>
25
26#include "proc-macros.S"
27
28/*
29 * the cache line size of the I and D cache
30 */
31#define DCACHELINESIZE	32
32
33	.text
34
35/*
36 * cpu_sa110_proc_init()
37 */
38ENTRY(cpu_sa110_proc_init)
39	mov	r0, #0
40	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
41	mov	pc, lr
42
43/*
44 * cpu_sa110_proc_fin()
45 */
46ENTRY(cpu_sa110_proc_fin)
47	mov	r0, #0
48	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
49	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
50	bic	r0, r0, #0x1000			@ ...i............
51	bic	r0, r0, #0x000e			@ ............wca.
52	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
53	mov	pc, lr
54
55/*
56 * cpu_sa110_reset(loc)
57 *
58 * Perform a soft reset of the system.  Put the CPU into the
59 * same state as it would be if it had been reset, and branch
60 * to what would be the reset vector.
61 *
62 * loc: location to jump to for soft reset
63 */
64	.align	5
65	.pushsection	.idmap.text, "ax"
66ENTRY(cpu_sa110_reset)
67	mov	ip, #0
68	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
69	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
70#ifdef CONFIG_MMU
71	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
72#endif
73	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
74	bic	ip, ip, #0x000f			@ ............wcam
75	bic	ip, ip, #0x1100			@ ...i...s........
76	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
77	mov	pc, r0
78ENDPROC(cpu_sa110_reset)
79	.popsection
80
81/*
82 * cpu_sa110_do_idle(type)
83 *
84 * Cause the processor to idle
85 *
86 * type: call type:
87 *   0 = slow idle
88 *   1 = fast idle
89 *   2 = switch to slow processor clock
90 *   3 = switch to fast processor clock
91 */
92	.align	5
93
94ENTRY(cpu_sa110_do_idle)
95	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
96	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
97	ldr	r1, [r1, #0]			@ force switch to MCLK
98	mov	r0, r0				@ safety
99	mov	r0, r0				@ safety
100	mov	r0, r0				@ safety
101	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
102	mov	r0, r0				@ safety
103	mov	r0, r0				@ safety
104	mov	r0, r0				@ safety
105	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
106	mov	pc, lr
107
108/* ================================= CACHE ================================ */
109
110/*
111 * cpu_sa110_dcache_clean_area(addr,sz)
112 *
113 * Clean the specified entry of any caches such that the MMU
114 * translation fetches will obtain correct data.
115 *
116 * addr: cache-unaligned virtual address
117 */
118	.align	5
119ENTRY(cpu_sa110_dcache_clean_area)
1201:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
121	add	r0, r0, #DCACHELINESIZE
122	subs	r1, r1, #DCACHELINESIZE
123	bhi	1b
124	mov	pc, lr
125
126/* =============================== PageTable ============================== */
127
128/*
129 * cpu_sa110_switch_mm(pgd)
130 *
131 * Set the translation base pointer to be as described by pgd.
132 *
133 * pgd: new page tables
134 */
135	.align	5
136ENTRY(cpu_sa110_switch_mm)
137#ifdef CONFIG_MMU
138	str	lr, [sp, #-4]!
139	bl	v4wb_flush_kern_cache_all	@ clears IP
140	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
141	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
142	ldr	pc, [sp], #4
143#else
144	mov	pc, lr
145#endif
146
147/*
148 * cpu_sa110_set_pte_ext(ptep, pte, ext)
149 *
150 * Set a PTE and flush it out
151 */
152	.align	5
153ENTRY(cpu_sa110_set_pte_ext)
154#ifdef CONFIG_MMU
155	armv3_set_pte_ext wc_disable=0
156	mov	r0, r0
157	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
158	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
159#endif
160	mov	pc, lr
161
162	__CPUINIT
163
164	.type	__sa110_setup, #function
165__sa110_setup:
166	mov	r10, #0
167	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
168	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
169#ifdef CONFIG_MMU
170	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
171#endif
172
173	adr	r5, sa110_crval
174	ldmia	r5, {r5, r6}
175	mrc	p15, 0, r0, c1, c0		@ get control register v4
176	bic	r0, r0, r5
177	orr	r0, r0, r6
178	mov	pc, lr
179	.size	__sa110_setup, . - __sa110_setup
180
181	/*
182	 *  R
183	 * .RVI ZFRS BLDP WCAM
184	 * ..01 0001 ..11 1101
185	 *
186	 */
187	.type	sa110_crval, #object
188sa110_crval:
189	crval	clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
190
191	__INITDATA
192
193	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
194	define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
195
196	.section ".rodata"
197
198	string	cpu_arch_name, "armv4"
199	string	cpu_elf_name, "v4"
200	string	cpu_sa110_name, "StrongARM-110"
201
202	.align
203
204	.section ".proc.info.init", #alloc, #execinstr
205
206	.type	__sa110_proc_info,#object
207__sa110_proc_info:
208	.long	0x4401a100
209	.long	0xfffffff0
210	.long   PMD_TYPE_SECT | \
211		PMD_SECT_BUFFERABLE | \
212		PMD_SECT_CACHEABLE | \
213		PMD_SECT_AP_WRITE | \
214		PMD_SECT_AP_READ
215	.long   PMD_TYPE_SECT | \
216		PMD_SECT_AP_WRITE | \
217		PMD_SECT_AP_READ
218	b	__sa110_setup
219	.long	cpu_arch_name
220	.long	cpu_elf_name
221	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
222	.long	cpu_sa110_name
223	.long	sa110_processor_functions
224	.long	v4wb_tlb_fns
225	.long	v4wb_user_fns
226	.long	v4wb_cache_fns
227	.size	__sa110_proc_info, . - __sa110_proc_info
228