xref: /openbmc/linux/arch/arm/mm/proc-sa110.S (revision 1da177e4) 
1/*
2 *  linux/arch/arm/mm/proc-sa110.S
3 *
4 *  Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  MMU functions for SA110
11 *
12 *  These are the low level assembler for performing cache and TLB
13 *  functions on the StrongARM-110.
14 */
15#include <linux/linkage.h>
16#include <linux/init.h>
17#include <asm/assembler.h>
18#include <asm/constants.h>
19#include <asm/procinfo.h>
20#include <asm/hardware.h>
21#include <asm/pgtable.h>
22#include <asm/ptrace.h>
23
24/*
25 * the cache line size of the I and D cache
26 */
27#define DCACHELINESIZE	32
28#define FLUSH_OFFSET	32768
29
30	.macro flush_110_dcache	rd, ra, re
31	ldr	\rd, =flush_base
32	ldr	\ra, [\rd]
33	eor	\ra, \ra, #FLUSH_OFFSET
34	str	\ra, [\rd]
35	add	\re, \ra, #16384		@ only necessary for 16k
361001:	ldr	\rd, [\ra], #DCACHELINESIZE
37	teq	\re, \ra
38	bne	1001b
39	.endm
40
41	.data
42flush_base:
43	.long	FLUSH_BASE
44	.text
45
46/*
47 * cpu_sa110_proc_init()
48 */
49ENTRY(cpu_sa110_proc_init)
50	mov	r0, #0
51	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
52	mov	pc, lr
53
54/*
55 * cpu_sa110_proc_fin()
56 */
57ENTRY(cpu_sa110_proc_fin)
58	stmfd	sp!, {lr}
59	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
60	msr	cpsr_c, ip
61	bl	v4wb_flush_kern_cache_all	@ clean caches
621:	mov	r0, #0
63	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
64	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
65	bic	r0, r0, #0x1000			@ ...i............
66	bic	r0, r0, #0x000e			@ ............wca.
67	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
68	ldmfd	sp!, {pc}
69
70/*
71 * cpu_sa110_reset(loc)
72 *
73 * Perform a soft reset of the system.  Put the CPU into the
74 * same state as it would be if it had been reset, and branch
75 * to what would be the reset vector.
76 *
77 * loc: location to jump to for soft reset
78 */
79	.align	5
80ENTRY(cpu_sa110_reset)
81	mov	ip, #0
82	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
83	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
84	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
85	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
86	bic	ip, ip, #0x000f			@ ............wcam
87	bic	ip, ip, #0x1100			@ ...i...s........
88	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
89	mov	pc, r0
90
91/*
92 * cpu_sa110_do_idle(type)
93 *
94 * Cause the processor to idle
95 *
96 * type: call type:
97 *   0 = slow idle
98 *   1 = fast idle
99 *   2 = switch to slow processor clock
100 *   3 = switch to fast processor clock
101 */
102	.align	5
103
104ENTRY(cpu_sa110_do_idle)
105	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
106	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
107	ldr	r1, [r1, #0]			@ force switch to MCLK
108	mov	r0, r0				@ safety
109	mov	r0, r0				@ safety
110	mov	r0, r0				@ safety
111	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
112	mov	r0, r0				@ safety
113	mov	r0, r0				@ safety
114	mov	r0, r0				@ safety
115	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
116	mov	pc, lr
117
118/* ================================= CACHE ================================ */
119
120/*
121 * cpu_sa110_dcache_clean_area(addr,sz)
122 *
123 * Clean the specified entry of any caches such that the MMU
124 * translation fetches will obtain correct data.
125 *
126 * addr: cache-unaligned virtual address
127 */
128	.align	5
129ENTRY(cpu_sa110_dcache_clean_area)
1301:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
131	add	r0, r0, #DCACHELINESIZE
132	subs	r1, r1, #DCACHELINESIZE
133	bhi	1b
134	mov	pc, lr
135
136/* =============================== PageTable ============================== */
137
138/*
139 * cpu_sa110_switch_mm(pgd)
140 *
141 * Set the translation base pointer to be as described by pgd.
142 *
143 * pgd: new page tables
144 */
145	.align	5
146ENTRY(cpu_sa110_switch_mm)
147	flush_110_dcache	r3, ip, r1
148	mov	r1, #0
149	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
150	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
151	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
152	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
153	mov	pc, lr
154
155/*
156 * cpu_sa110_set_pte(ptep, pte)
157 *
158 * Set a PTE and flush it out
159 */
160	.align	5
161ENTRY(cpu_sa110_set_pte)
162	str	r1, [r0], #-2048		@ linux version
163
164	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
165
166	bic	r2, r1, #PTE_SMALL_AP_MASK
167	bic	r2, r2, #PTE_TYPE_MASK
168	orr	r2, r2, #PTE_TYPE_SMALL
169
170	tst	r1, #L_PTE_USER			@ User?
171	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
172
173	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
174	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
175
176	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?
177	movne	r2, #0
178
179	str	r2, [r0]			@ hardware version
180	mov	r0, r0
181	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
182	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
183	mov	pc, lr
184
185	__INIT
186
187	.type	__sa110_setup, #function
188__sa110_setup:
189	mov	r10, #0
190	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
191	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
192	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
193	mrc	p15, 0, r0, c1, c0		@ get control register v4
194	ldr	r5, sa110_cr1_clear
195	bic	r0, r0, r5
196	ldr	r5, sa110_cr1_set
197	orr	r0, r0, r5
198	mov	pc, lr
199	.size	__sa110_setup, . - __sa110_setup
200
201	/*
202	 *  R
203	 * .RVI ZFRS BLDP WCAM
204	 * ..01 0001 ..11 1101
205	 *
206	 */
207	.type	sa110_cr1_clear, #object
208	.type	sa110_cr1_set, #object
209sa110_cr1_clear:
210	.word	0x3f3f
211sa110_cr1_set:
212	.word	0x113d
213
214	__INITDATA
215
216/*
217 * Purpose : Function pointers used to access above functions - all calls
218 *	     come through these
219 */
220
221	.type	sa110_processor_functions, #object
222ENTRY(sa110_processor_functions)
223	.word	v4_early_abort
224	.word	cpu_sa110_proc_init
225	.word	cpu_sa110_proc_fin
226	.word	cpu_sa110_reset
227	.word	cpu_sa110_do_idle
228	.word	cpu_sa110_dcache_clean_area
229	.word	cpu_sa110_switch_mm
230	.word	cpu_sa110_set_pte
231	.size	sa110_processor_functions, . - sa110_processor_functions
232
233	.section ".rodata"
234
235	.type	cpu_arch_name, #object
236cpu_arch_name:
237	.asciz	"armv4"
238	.size	cpu_arch_name, . - cpu_arch_name
239
240	.type	cpu_elf_name, #object
241cpu_elf_name:
242	.asciz	"v4"
243	.size	cpu_elf_name, . - cpu_elf_name
244
245	.type	cpu_sa110_name, #object
246cpu_sa110_name:
247	.asciz	"StrongARM-110"
248	.size	cpu_sa110_name, . - cpu_sa110_name
249
250	.align
251
252	.section ".proc.info", #alloc, #execinstr
253
254	.type	__sa110_proc_info,#object
255__sa110_proc_info:
256	.long	0x4401a100
257	.long	0xfffffff0
258	.long   PMD_TYPE_SECT | \
259		PMD_SECT_BUFFERABLE | \
260		PMD_SECT_CACHEABLE | \
261		PMD_SECT_AP_WRITE | \
262		PMD_SECT_AP_READ
263	b	__sa110_setup
264	.long	cpu_arch_name
265	.long	cpu_elf_name
266	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
267	.long	cpu_sa110_name
268	.long	sa110_processor_functions
269	.long	v4wb_tlb_fns
270	.long	v4wb_user_fns
271	.long	v4wb_cache_fns
272	.size	__sa110_proc_info, . - __sa110_proc_info
273