1/* 2 * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core 3 * 4 * PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core. 5 * 6 * Heavily based on proc-arm926.S and proc-xsc3.S 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <asm/assembler.h> 26#include <asm/hwcap.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable.h> 29#include <asm/page.h> 30#include <asm/ptrace.h> 31#include "proc-macros.S" 32 33/* 34 * This is the maximum size of an area which will be flushed. If the 35 * area is larger than this, then we flush the whole cache. 36 */ 37#define CACHE_DLIMIT 32768 38 39/* 40 * The cache line size of the L1 D cache. 41 */ 42#define CACHE_DLINESIZE 32 43 44/* 45 * cpu_mohawk_proc_init() 46 */ 47ENTRY(cpu_mohawk_proc_init) 48 mov pc, lr 49 50/* 51 * cpu_mohawk_proc_fin() 52 */ 53ENTRY(cpu_mohawk_proc_fin) 54 stmfd sp!, {lr} 55 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 56 msr cpsr_c, ip 57 bl mohawk_flush_kern_cache_all 58 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 59 bic r0, r0, #0x1800 @ ...iz........... 60 bic r0, r0, #0x0006 @ .............ca. 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 ldmfd sp!, {pc} 63 64/* 65 * cpu_mohawk_reset(loc) 66 * 67 * Perform a soft reset of the system. Put the CPU into the 68 * same state as it would be if it had been reset, and branch 69 * to what would be the reset vector. 70 * 71 * loc: location to jump to for soft reset 72 * 73 * (same as arm926) 74 */ 75 .align 5 76ENTRY(cpu_mohawk_reset) 77 mov ip, #0 78 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 82 bic ip, ip, #0x0007 @ .............cam 83 bic ip, ip, #0x1100 @ ...i...s........ 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 85 mov pc, r0 86 87/* 88 * cpu_mohawk_do_idle() 89 * 90 * Called with IRQs disabled 91 */ 92 .align 5 93ENTRY(cpu_mohawk_do_idle) 94 mov r0, #0 95 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 96 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 97 mov pc, lr 98 99/* 100 * flush_user_cache_all() 101 * 102 * Clean and invalidate all cache entries in a particular 103 * address space. 104 */ 105ENTRY(mohawk_flush_user_cache_all) 106 /* FALLTHROUGH */ 107 108/* 109 * flush_kern_cache_all() 110 * 111 * Clean and invalidate the entire cache. 112 */ 113ENTRY(mohawk_flush_kern_cache_all) 114 mov r2, #VM_EXEC 115 mov ip, #0 116__flush_whole_cache: 117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 118 tst r2, #VM_EXEC 119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 120 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 121 mov pc, lr 122 123/* 124 * flush_user_cache_range(start, end, flags) 125 * 126 * Clean and invalidate a range of cache entries in the 127 * specified address range. 128 * 129 * - start - start address (inclusive) 130 * - end - end address (exclusive) 131 * - flags - vm_flags describing address space 132 * 133 * (same as arm926) 134 */ 135ENTRY(mohawk_flush_user_cache_range) 136 mov ip, #0 137 sub r3, r1, r0 @ calculate total size 138 cmp r3, #CACHE_DLIMIT 139 bgt __flush_whole_cache 1401: tst r2, #VM_EXEC 141 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 143 add r0, r0, #CACHE_DLINESIZE 144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 146 add r0, r0, #CACHE_DLINESIZE 147 cmp r0, r1 148 blo 1b 149 tst r2, #VM_EXEC 150 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 151 mov pc, lr 152 153/* 154 * coherent_kern_range(start, end) 155 * 156 * Ensure coherency between the Icache and the Dcache in the 157 * region described by start, end. If you have non-snooping 158 * Harvard caches, you need to implement this function. 159 * 160 * - start - virtual start address 161 * - end - virtual end address 162 */ 163ENTRY(mohawk_coherent_kern_range) 164 /* FALLTHROUGH */ 165 166/* 167 * coherent_user_range(start, end) 168 * 169 * Ensure coherency between the Icache and the Dcache in the 170 * region described by start, end. If you have non-snooping 171 * Harvard caches, you need to implement this function. 172 * 173 * - start - virtual start address 174 * - end - virtual end address 175 * 176 * (same as arm926) 177 */ 178ENTRY(mohawk_coherent_user_range) 179 bic r0, r0, #CACHE_DLINESIZE - 1 1801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 181 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 182 add r0, r0, #CACHE_DLINESIZE 183 cmp r0, r1 184 blo 1b 185 mcr p15, 0, r0, c7, c10, 4 @ drain WB 186 mov pc, lr 187 188/* 189 * flush_kern_dcache_area(void *addr, size_t size) 190 * 191 * Ensure no D cache aliasing occurs, either with itself or 192 * the I cache 193 * 194 * - addr - kernel address 195 * - size - region size 196 */ 197ENTRY(mohawk_flush_kern_dcache_area) 198 add r1, r0, r1 1991: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 200 add r0, r0, #CACHE_DLINESIZE 201 cmp r0, r1 202 blo 1b 203 mov r0, #0 204 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 205 mcr p15, 0, r0, c7, c10, 4 @ drain WB 206 mov pc, lr 207 208/* 209 * dma_inv_range(start, end) 210 * 211 * Invalidate (discard) the specified virtual address range. 212 * May not write back any entries. If 'start' or 'end' 213 * are not cache line aligned, those lines must be written 214 * back. 215 * 216 * - start - virtual start address 217 * - end - virtual end address 218 * 219 * (same as v4wb) 220 */ 221ENTRY(mohawk_dma_inv_range) 222 tst r0, #CACHE_DLINESIZE - 1 223 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 224 tst r1, #CACHE_DLINESIZE - 1 225 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 226 bic r0, r0, #CACHE_DLINESIZE - 1 2271: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 228 add r0, r0, #CACHE_DLINESIZE 229 cmp r0, r1 230 blo 1b 231 mcr p15, 0, r0, c7, c10, 4 @ drain WB 232 mov pc, lr 233 234/* 235 * dma_clean_range(start, end) 236 * 237 * Clean the specified virtual address range. 238 * 239 * - start - virtual start address 240 * - end - virtual end address 241 * 242 * (same as v4wb) 243 */ 244ENTRY(mohawk_dma_clean_range) 245 bic r0, r0, #CACHE_DLINESIZE - 1 2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 247 add r0, r0, #CACHE_DLINESIZE 248 cmp r0, r1 249 blo 1b 250 mcr p15, 0, r0, c7, c10, 4 @ drain WB 251 mov pc, lr 252 253/* 254 * dma_flush_range(start, end) 255 * 256 * Clean and invalidate the specified virtual address range. 257 * 258 * - start - virtual start address 259 * - end - virtual end address 260 */ 261ENTRY(mohawk_dma_flush_range) 262 bic r0, r0, #CACHE_DLINESIZE - 1 2631: 264 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 265 add r0, r0, #CACHE_DLINESIZE 266 cmp r0, r1 267 blo 1b 268 mcr p15, 0, r0, c7, c10, 4 @ drain WB 269 mov pc, lr 270 271ENTRY(mohawk_cache_fns) 272 .long mohawk_flush_kern_cache_all 273 .long mohawk_flush_user_cache_all 274 .long mohawk_flush_user_cache_range 275 .long mohawk_coherent_kern_range 276 .long mohawk_coherent_user_range 277 .long mohawk_flush_kern_dcache_area 278 .long mohawk_dma_inv_range 279 .long mohawk_dma_clean_range 280 .long mohawk_dma_flush_range 281 282ENTRY(cpu_mohawk_dcache_clean_area) 2831: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 284 add r0, r0, #CACHE_DLINESIZE 285 subs r1, r1, #CACHE_DLINESIZE 286 bhi 1b 287 mcr p15, 0, r0, c7, c10, 4 @ drain WB 288 mov pc, lr 289 290/* 291 * cpu_mohawk_switch_mm(pgd) 292 * 293 * Set the translation base pointer to be as described by pgd. 294 * 295 * pgd: new page tables 296 */ 297 .align 5 298ENTRY(cpu_mohawk_switch_mm) 299 mov ip, #0 300 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 301 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 302 mcr p15, 0, ip, c7, c10, 4 @ drain WB 303 orr r0, r0, #0x18 @ cache the page table in L2 304 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 305 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 306 mov pc, lr 307 308/* 309 * cpu_mohawk_set_pte_ext(ptep, pte, ext) 310 * 311 * Set a PTE and flush it out 312 */ 313 .align 5 314ENTRY(cpu_mohawk_set_pte_ext) 315 armv3_set_pte_ext 316 mov r0, r0 317 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 318 mcr p15, 0, r0, c7, c10, 4 @ drain WB 319 mov pc, lr 320 321 __INIT 322 323 .type __mohawk_setup, #function 324__mohawk_setup: 325 mov r0, #0 326 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches 327 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 328 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs 329 orr r4, r4, #0x18 @ cache the page table in L2 330 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 331 332 mov r0, #0 @ don't allow CP access 333 mcr p15, 0, r0, c15, c1, 0 @ write CP access register 334 335 adr r5, mohawk_crval 336 ldmia r5, {r5, r6} 337 mrc p15, 0, r0, c1, c0 @ get control register 338 bic r0, r0, r5 339 orr r0, r0, r6 340 mov pc, lr 341 342 .size __mohawk_setup, . - __mohawk_setup 343 344 /* 345 * R 346 * .RVI ZFRS BLDP WCAM 347 * .011 1001 ..00 0101 348 * 349 */ 350 .type mohawk_crval, #object 351mohawk_crval: 352 crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134 353 354 __INITDATA 355 356/* 357 * Purpose : Function pointers used to access above functions - all calls 358 * come through these 359 */ 360 .type mohawk_processor_functions, #object 361mohawk_processor_functions: 362 .word v5t_early_abort 363 .word legacy_pabort 364 .word cpu_mohawk_proc_init 365 .word cpu_mohawk_proc_fin 366 .word cpu_mohawk_reset 367 .word cpu_mohawk_do_idle 368 .word cpu_mohawk_dcache_clean_area 369 .word cpu_mohawk_switch_mm 370 .word cpu_mohawk_set_pte_ext 371 .size mohawk_processor_functions, . - mohawk_processor_functions 372 373 .section ".rodata" 374 375 .type cpu_arch_name, #object 376cpu_arch_name: 377 .asciz "armv5te" 378 .size cpu_arch_name, . - cpu_arch_name 379 380 .type cpu_elf_name, #object 381cpu_elf_name: 382 .asciz "v5" 383 .size cpu_elf_name, . - cpu_elf_name 384 385 .type cpu_mohawk_name, #object 386cpu_mohawk_name: 387 .asciz "Marvell 88SV331x" 388 .size cpu_mohawk_name, . - cpu_mohawk_name 389 390 .align 391 392 .section ".proc.info.init", #alloc, #execinstr 393 394 .type __88sv331x_proc_info,#object 395__88sv331x_proc_info: 396 .long 0x56158000 @ Marvell 88SV331x (MOHAWK) 397 .long 0xfffff000 398 .long PMD_TYPE_SECT | \ 399 PMD_SECT_BUFFERABLE | \ 400 PMD_SECT_CACHEABLE | \ 401 PMD_BIT4 | \ 402 PMD_SECT_AP_WRITE | \ 403 PMD_SECT_AP_READ 404 .long PMD_TYPE_SECT | \ 405 PMD_BIT4 | \ 406 PMD_SECT_AP_WRITE | \ 407 PMD_SECT_AP_READ 408 b __mohawk_setup 409 .long cpu_arch_name 410 .long cpu_elf_name 411 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 412 .long cpu_mohawk_name 413 .long mohawk_processor_functions 414 .long v4wbi_tlb_fns 415 .long v4wb_user_fns 416 .long mohawk_cache_fns 417 .size __88sv331x_proc_info, . - __88sv331x_proc_info 418