1/* 2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon 3 * 4 * Heavily based on proc-arm926.S 5 * Maintainer: Assaf Hoffman <hoffman@marvell.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <linux/linkage.h> 23#include <linux/init.h> 24#include <asm/assembler.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28#include <asm/page.h> 29#include <asm/ptrace.h> 30#include "proc-macros.S" 31 32/* 33 * This is the maximum size of an area which will be invalidated 34 * using the single invalidate entry instructions. Anything larger 35 * than this, and we go for the whole cache. 36 * 37 * This value should be chosen such that we choose the cheapest 38 * alternative. 39 */ 40#define CACHE_DLIMIT 16384 41 42/* 43 * the cache line size of the I and D cache 44 */ 45#define CACHE_DLINESIZE 32 46 47 .bss 48 .align 3 49__cache_params_loc: 50 .space 8 51 52 .text 53__cache_params: 54 .word __cache_params_loc 55 56/* 57 * cpu_feroceon_proc_init() 58 */ 59ENTRY(cpu_feroceon_proc_init) 60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register 61 ldr r1, __cache_params 62 mov r2, #(16 << 5) 63 tst r0, #(1 << 16) @ get way 64 mov r0, r0, lsr #18 @ get cache size order 65 movne r3, #((4 - 1) << 30) @ 4-way 66 and r0, r0, #0xf 67 moveq r3, #0 @ 1-way 68 mov r2, r2, lsl r0 @ actual cache size 69 movne r2, r2, lsr #2 @ turned into # of sets 70 sub r2, r2, #(1 << 5) 71 stmia r1, {r2, r3} 72 mov pc, lr 73 74/* 75 * cpu_feroceon_proc_fin() 76 */ 77ENTRY(cpu_feroceon_proc_fin) 78 stmfd sp!, {lr} 79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 80 msr cpsr_c, ip 81 bl feroceon_flush_kern_cache_all 82 83#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 85 mov r0, #0 86 mcr p15, 1, r0, c15, c9, 0 @ clean L2 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 88#endif 89 90 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 91 bic r0, r0, #0x1000 @ ...i............ 92 bic r0, r0, #0x000e @ ............wca. 93 mcr p15, 0, r0, c1, c0, 0 @ disable caches 94 ldmfd sp!, {pc} 95 96/* 97 * cpu_feroceon_reset(loc) 98 * 99 * Perform a soft reset of the system. Put the CPU into the 100 * same state as it would be if it had been reset, and branch 101 * to what would be the reset vector. 102 * 103 * loc: location to jump to for soft reset 104 */ 105 .align 5 106ENTRY(cpu_feroceon_reset) 107 mov ip, #0 108 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 109 mcr p15, 0, ip, c7, c10, 4 @ drain WB 110#ifdef CONFIG_MMU 111 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112#endif 113 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 114 bic ip, ip, #0x000f @ ............wcam 115 bic ip, ip, #0x1100 @ ...i...s........ 116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mov pc, r0 118 119/* 120 * cpu_feroceon_do_idle() 121 * 122 * Called with IRQs disabled 123 */ 124 .align 5 125ENTRY(cpu_feroceon_do_idle) 126 mov r0, #0 127 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 128 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 129 mov pc, lr 130 131/* 132 * flush_user_cache_all() 133 * 134 * Clean and invalidate all cache entries in a particular 135 * address space. 136 */ 137 .align 5 138ENTRY(feroceon_flush_user_cache_all) 139 /* FALLTHROUGH */ 140 141/* 142 * flush_kern_cache_all() 143 * 144 * Clean and invalidate the entire cache. 145 */ 146ENTRY(feroceon_flush_kern_cache_all) 147 mov r2, #VM_EXEC 148 149__flush_whole_cache: 150 ldr r1, __cache_params 151 ldmia r1, {r1, r3} 1521: orr ip, r1, r3 1532: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 154 subs ip, ip, #(1 << 30) @ next way 155 bcs 2b 156 subs r1, r1, #(1 << 5) @ next set 157 bcs 1b 158 159 tst r2, #VM_EXEC 160 mov ip, #0 161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 163 mov pc, lr 164 165/* 166 * flush_user_cache_range(start, end, flags) 167 * 168 * Clean and invalidate a range of cache entries in the 169 * specified address range. 170 * 171 * - start - start address (inclusive) 172 * - end - end address (exclusive) 173 * - flags - vm_flags describing address space 174 */ 175 .align 5 176ENTRY(feroceon_flush_user_cache_range) 177 sub r3, r1, r0 @ calculate total size 178 cmp r3, #CACHE_DLIMIT 179 bgt __flush_whole_cache 1801: tst r2, #VM_EXEC 181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 183 add r0, r0, #CACHE_DLINESIZE 184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 186 add r0, r0, #CACHE_DLINESIZE 187 cmp r0, r1 188 blo 1b 189 tst r2, #VM_EXEC 190 mov ip, #0 191 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 192 mov pc, lr 193 194/* 195 * coherent_kern_range(start, end) 196 * 197 * Ensure coherency between the Icache and the Dcache in the 198 * region described by start, end. If you have non-snooping 199 * Harvard caches, you need to implement this function. 200 * 201 * - start - virtual start address 202 * - end - virtual end address 203 */ 204 .align 5 205ENTRY(feroceon_coherent_kern_range) 206 /* FALLTHROUGH */ 207 208/* 209 * coherent_user_range(start, end) 210 * 211 * Ensure coherency between the Icache and the Dcache in the 212 * region described by start, end. If you have non-snooping 213 * Harvard caches, you need to implement this function. 214 * 215 * - start - virtual start address 216 * - end - virtual end address 217 */ 218ENTRY(feroceon_coherent_user_range) 219 bic r0, r0, #CACHE_DLINESIZE - 1 2201: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 222 add r0, r0, #CACHE_DLINESIZE 223 cmp r0, r1 224 blo 1b 225 mcr p15, 0, r0, c7, c10, 4 @ drain WB 226 mov pc, lr 227 228/* 229 * flush_kern_dcache_area(void *addr, size_t size) 230 * 231 * Ensure no D cache aliasing occurs, either with itself or 232 * the I cache 233 * 234 * - addr - kernel address 235 * - size - region size 236 */ 237 .align 5 238ENTRY(feroceon_flush_kern_dcache_area) 239 add r1, r0, r1 2401: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 241 add r0, r0, #CACHE_DLINESIZE 242 cmp r0, r1 243 blo 1b 244 mov r0, #0 245 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 246 mcr p15, 0, r0, c7, c10, 4 @ drain WB 247 mov pc, lr 248 249 .align 5 250ENTRY(feroceon_range_flush_kern_dcache_area) 251 mrs r2, cpsr 252 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive 253 orr r3, r2, #PSR_I_BIT 254 msr cpsr_c, r3 @ disable interrupts 255 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 256 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 257 msr cpsr_c, r2 @ restore interrupts 258 mov r0, #0 259 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 260 mcr p15, 0, r0, c7, c10, 4 @ drain WB 261 mov pc, lr 262 263/* 264 * dma_inv_range(start, end) 265 * 266 * Invalidate (discard) the specified virtual address range. 267 * May not write back any entries. If 'start' or 'end' 268 * are not cache line aligned, those lines must be written 269 * back. 270 * 271 * - start - virtual start address 272 * - end - virtual end address 273 * 274 * (same as v4wb) 275 */ 276 .align 5 277ENTRY(feroceon_dma_inv_range) 278 tst r0, #CACHE_DLINESIZE - 1 279 bic r0, r0, #CACHE_DLINESIZE - 1 280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 281 tst r1, #CACHE_DLINESIZE - 1 282 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2831: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 284 add r0, r0, #CACHE_DLINESIZE 285 cmp r0, r1 286 blo 1b 287 mcr p15, 0, r0, c7, c10, 4 @ drain WB 288 mov pc, lr 289 290 .align 5 291ENTRY(feroceon_range_dma_inv_range) 292 mrs r2, cpsr 293 tst r0, #CACHE_DLINESIZE - 1 294 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 295 tst r1, #CACHE_DLINESIZE - 1 296 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 297 cmp r1, r0 298 subne r1, r1, #1 @ top address is inclusive 299 orr r3, r2, #PSR_I_BIT 300 msr cpsr_c, r3 @ disable interrupts 301 mcr p15, 5, r0, c15, c14, 0 @ D inv range start 302 mcr p15, 5, r1, c15, c14, 1 @ D inv range top 303 msr cpsr_c, r2 @ restore interrupts 304 mov pc, lr 305 306/* 307 * dma_clean_range(start, end) 308 * 309 * Clean the specified virtual address range. 310 * 311 * - start - virtual start address 312 * - end - virtual end address 313 * 314 * (same as v4wb) 315 */ 316 .align 5 317ENTRY(feroceon_dma_clean_range) 318 bic r0, r0, #CACHE_DLINESIZE - 1 3191: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 320 add r0, r0, #CACHE_DLINESIZE 321 cmp r0, r1 322 blo 1b 323 mcr p15, 0, r0, c7, c10, 4 @ drain WB 324 mov pc, lr 325 326 .align 5 327ENTRY(feroceon_range_dma_clean_range) 328 mrs r2, cpsr 329 cmp r1, r0 330 subne r1, r1, #1 @ top address is inclusive 331 orr r3, r2, #PSR_I_BIT 332 msr cpsr_c, r3 @ disable interrupts 333 mcr p15, 5, r0, c15, c13, 0 @ D clean range start 334 mcr p15, 5, r1, c15, c13, 1 @ D clean range top 335 msr cpsr_c, r2 @ restore interrupts 336 mcr p15, 0, r0, c7, c10, 4 @ drain WB 337 mov pc, lr 338 339/* 340 * dma_flush_range(start, end) 341 * 342 * Clean and invalidate the specified virtual address range. 343 * 344 * - start - virtual start address 345 * - end - virtual end address 346 */ 347 .align 5 348ENTRY(feroceon_dma_flush_range) 349 bic r0, r0, #CACHE_DLINESIZE - 1 3501: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 351 add r0, r0, #CACHE_DLINESIZE 352 cmp r0, r1 353 blo 1b 354 mcr p15, 0, r0, c7, c10, 4 @ drain WB 355 mov pc, lr 356 357 .align 5 358ENTRY(feroceon_range_dma_flush_range) 359 mrs r2, cpsr 360 cmp r1, r0 361 subne r1, r1, #1 @ top address is inclusive 362 orr r3, r2, #PSR_I_BIT 363 msr cpsr_c, r3 @ disable interrupts 364 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 365 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 366 msr cpsr_c, r2 @ restore interrupts 367 mcr p15, 0, r0, c7, c10, 4 @ drain WB 368 mov pc, lr 369 370ENTRY(feroceon_cache_fns) 371 .long feroceon_flush_kern_cache_all 372 .long feroceon_flush_user_cache_all 373 .long feroceon_flush_user_cache_range 374 .long feroceon_coherent_kern_range 375 .long feroceon_coherent_user_range 376 .long feroceon_flush_kern_dcache_area 377 .long feroceon_dma_inv_range 378 .long feroceon_dma_clean_range 379 .long feroceon_dma_flush_range 380 381ENTRY(feroceon_range_cache_fns) 382 .long feroceon_flush_kern_cache_all 383 .long feroceon_flush_user_cache_all 384 .long feroceon_flush_user_cache_range 385 .long feroceon_coherent_kern_range 386 .long feroceon_coherent_user_range 387 .long feroceon_range_flush_kern_dcache_area 388 .long feroceon_range_dma_inv_range 389 .long feroceon_range_dma_clean_range 390 .long feroceon_range_dma_flush_range 391 392 .align 5 393ENTRY(cpu_feroceon_dcache_clean_area) 394#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 395 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 396 mov r2, r0 397 mov r3, r1 398#endif 3991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 400 add r0, r0, #CACHE_DLINESIZE 401 subs r1, r1, #CACHE_DLINESIZE 402 bhi 1b 403#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 404 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 4051: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry 406 add r2, r2, #CACHE_DLINESIZE 407 subs r3, r3, #CACHE_DLINESIZE 408 bhi 1b 409#endif 410 mcr p15, 0, r0, c7, c10, 4 @ drain WB 411 mov pc, lr 412 413/* =============================== PageTable ============================== */ 414 415/* 416 * cpu_feroceon_switch_mm(pgd) 417 * 418 * Set the translation base pointer to be as described by pgd. 419 * 420 * pgd: new page tables 421 */ 422 .align 5 423ENTRY(cpu_feroceon_switch_mm) 424#ifdef CONFIG_MMU 425 /* 426 * Note: we wish to call __flush_whole_cache but we need to preserve 427 * lr to do so. The only way without touching main memory is to 428 * use r2 which is normally used to test the VM_EXEC flag, and 429 * compensate locally for the skipped ops if it is not set. 430 */ 431 mov r2, lr @ abuse r2 to preserve lr 432 bl __flush_whole_cache 433 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already 434 tst r2, #VM_EXEC 435 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache 436 mcreq p15, 0, ip, c7, c10, 4 @ drain WB 437 438 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 439 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 440 mov pc, r2 441#else 442 mov pc, lr 443#endif 444 445/* 446 * cpu_feroceon_set_pte_ext(ptep, pte, ext) 447 * 448 * Set a PTE and flush it out 449 */ 450 .align 5 451ENTRY(cpu_feroceon_set_pte_ext) 452#ifdef CONFIG_MMU 453 armv3_set_pte_ext wc_disable=0 454 mov r0, r0 455 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 456#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 457 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 458 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry 459#endif 460 mcr p15, 0, r0, c7, c10, 4 @ drain WB 461#endif 462 mov pc, lr 463 464 __INIT 465 466 .type __feroceon_setup, #function 467__feroceon_setup: 468 mov r0, #0 469 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 470 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 471#ifdef CONFIG_MMU 472 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 473#endif 474 475 adr r5, feroceon_crval 476 ldmia r5, {r5, r6} 477 mrc p15, 0, r0, c1, c0 @ get control register v4 478 bic r0, r0, r5 479 orr r0, r0, r6 480 mov pc, lr 481 .size __feroceon_setup, . - __feroceon_setup 482 483 /* 484 * B 485 * R P 486 * .RVI UFRS BLDP WCAM 487 * .011 .001 ..11 0101 488 * 489 */ 490 .type feroceon_crval, #object 491feroceon_crval: 492 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134 493 494 __INITDATA 495 496/* 497 * Purpose : Function pointers used to access above functions - all calls 498 * come through these 499 */ 500 .type feroceon_processor_functions, #object 501feroceon_processor_functions: 502 .word v5t_early_abort 503 .word legacy_pabort 504 .word cpu_feroceon_proc_init 505 .word cpu_feroceon_proc_fin 506 .word cpu_feroceon_reset 507 .word cpu_feroceon_do_idle 508 .word cpu_feroceon_dcache_clean_area 509 .word cpu_feroceon_switch_mm 510 .word cpu_feroceon_set_pte_ext 511 .size feroceon_processor_functions, . - feroceon_processor_functions 512 513 .section ".rodata" 514 515 .type cpu_arch_name, #object 516cpu_arch_name: 517 .asciz "armv5te" 518 .size cpu_arch_name, . - cpu_arch_name 519 520 .type cpu_elf_name, #object 521cpu_elf_name: 522 .asciz "v5" 523 .size cpu_elf_name, . - cpu_elf_name 524 525 .type cpu_feroceon_name, #object 526cpu_feroceon_name: 527 .asciz "Feroceon" 528 .size cpu_feroceon_name, . - cpu_feroceon_name 529 530 .type cpu_88fr531_name, #object 531cpu_88fr531_name: 532 .asciz "Feroceon 88FR531-vd" 533 .size cpu_88fr531_name, . - cpu_88fr531_name 534 535 .type cpu_88fr571_name, #object 536cpu_88fr571_name: 537 .asciz "Feroceon 88FR571-vd" 538 .size cpu_88fr571_name, . - cpu_88fr571_name 539 540 .type cpu_88fr131_name, #object 541cpu_88fr131_name: 542 .asciz "Feroceon 88FR131" 543 .size cpu_88fr131_name, . - cpu_88fr131_name 544 545 .align 546 547 .section ".proc.info.init", #alloc, #execinstr 548 549#ifdef CONFIG_CPU_FEROCEON_OLD_ID 550 .type __feroceon_old_id_proc_info,#object 551__feroceon_old_id_proc_info: 552 .long 0x41009260 553 .long 0xff00fff0 554 .long PMD_TYPE_SECT | \ 555 PMD_SECT_BUFFERABLE | \ 556 PMD_SECT_CACHEABLE | \ 557 PMD_BIT4 | \ 558 PMD_SECT_AP_WRITE | \ 559 PMD_SECT_AP_READ 560 .long PMD_TYPE_SECT | \ 561 PMD_BIT4 | \ 562 PMD_SECT_AP_WRITE | \ 563 PMD_SECT_AP_READ 564 b __feroceon_setup 565 .long cpu_arch_name 566 .long cpu_elf_name 567 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 568 .long cpu_feroceon_name 569 .long feroceon_processor_functions 570 .long v4wbi_tlb_fns 571 .long feroceon_user_fns 572 .long feroceon_cache_fns 573 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info 574#endif 575 576 .type __88fr531_proc_info,#object 577__88fr531_proc_info: 578 .long 0x56055310 579 .long 0xfffffff0 580 .long PMD_TYPE_SECT | \ 581 PMD_SECT_BUFFERABLE | \ 582 PMD_SECT_CACHEABLE | \ 583 PMD_BIT4 | \ 584 PMD_SECT_AP_WRITE | \ 585 PMD_SECT_AP_READ 586 .long PMD_TYPE_SECT | \ 587 PMD_BIT4 | \ 588 PMD_SECT_AP_WRITE | \ 589 PMD_SECT_AP_READ 590 b __feroceon_setup 591 .long cpu_arch_name 592 .long cpu_elf_name 593 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 594 .long cpu_88fr531_name 595 .long feroceon_processor_functions 596 .long v4wbi_tlb_fns 597 .long feroceon_user_fns 598 .long feroceon_cache_fns 599 .size __88fr531_proc_info, . - __88fr531_proc_info 600 601 .type __88fr571_proc_info,#object 602__88fr571_proc_info: 603 .long 0x56155710 604 .long 0xfffffff0 605 .long PMD_TYPE_SECT | \ 606 PMD_SECT_BUFFERABLE | \ 607 PMD_SECT_CACHEABLE | \ 608 PMD_BIT4 | \ 609 PMD_SECT_AP_WRITE | \ 610 PMD_SECT_AP_READ 611 .long PMD_TYPE_SECT | \ 612 PMD_BIT4 | \ 613 PMD_SECT_AP_WRITE | \ 614 PMD_SECT_AP_READ 615 b __feroceon_setup 616 .long cpu_arch_name 617 .long cpu_elf_name 618 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 619 .long cpu_88fr571_name 620 .long feroceon_processor_functions 621 .long v4wbi_tlb_fns 622 .long feroceon_user_fns 623 .long feroceon_range_cache_fns 624 .size __88fr571_proc_info, . - __88fr571_proc_info 625 626 .type __88fr131_proc_info,#object 627__88fr131_proc_info: 628 .long 0x56251310 629 .long 0xfffffff0 630 .long PMD_TYPE_SECT | \ 631 PMD_SECT_BUFFERABLE | \ 632 PMD_SECT_CACHEABLE | \ 633 PMD_BIT4 | \ 634 PMD_SECT_AP_WRITE | \ 635 PMD_SECT_AP_READ 636 .long PMD_TYPE_SECT | \ 637 PMD_BIT4 | \ 638 PMD_SECT_AP_WRITE | \ 639 PMD_SECT_AP_READ 640 b __feroceon_setup 641 .long cpu_arch_name 642 .long cpu_elf_name 643 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 644 .long cpu_88fr131_name 645 .long feroceon_processor_functions 646 .long v4wbi_tlb_fns 647 .long feroceon_user_fns 648 .long feroceon_range_cache_fns 649 .size __88fr131_proc_info, . - __88fr131_proc_info 650