1/* 2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon 3 * 4 * Heavily based on proc-arm926.S 5 * Maintainer: Assaf Hoffman <hoffman@marvell.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <linux/linkage.h> 23#include <linux/init.h> 24#include <asm/assembler.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28#include <asm/page.h> 29#include <asm/ptrace.h> 30#include "proc-macros.S" 31 32/* 33 * This is the maximum size of an area which will be invalidated 34 * using the single invalidate entry instructions. Anything larger 35 * than this, and we go for the whole cache. 36 * 37 * This value should be chosen such that we choose the cheapest 38 * alternative. 39 */ 40#define CACHE_DLIMIT 16384 41 42/* 43 * the cache line size of the I and D cache 44 */ 45#define CACHE_DLINESIZE 32 46 47 .bss 48 .align 3 49__cache_params_loc: 50 .space 8 51 52 .text 53__cache_params: 54 .word __cache_params_loc 55 56/* 57 * cpu_feroceon_proc_init() 58 */ 59ENTRY(cpu_feroceon_proc_init) 60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register 61 ldr r1, __cache_params 62 mov r2, #(16 << 5) 63 tst r0, #(1 << 16) @ get way 64 mov r0, r0, lsr #18 @ get cache size order 65 movne r3, #((4 - 1) << 30) @ 4-way 66 and r0, r0, #0xf 67 moveq r3, #0 @ 1-way 68 mov r2, r2, lsl r0 @ actual cache size 69 movne r2, r2, lsr #2 @ turned into # of sets 70 sub r2, r2, #(1 << 5) 71 stmia r1, {r2, r3} 72 mov pc, lr 73 74/* 75 * cpu_feroceon_proc_fin() 76 */ 77ENTRY(cpu_feroceon_proc_fin) 78#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 79 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 80 mov r0, #0 81 mcr p15, 1, r0, c15, c9, 0 @ clean L2 82 mcr p15, 0, r0, c7, c10, 4 @ drain WB 83#endif 84 85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 86 bic r0, r0, #0x1000 @ ...i............ 87 bic r0, r0, #0x000e @ ............wca. 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches 89 mov pc, lr 90 91/* 92 * cpu_feroceon_reset(loc) 93 * 94 * Perform a soft reset of the system. Put the CPU into the 95 * same state as it would be if it had been reset, and branch 96 * to what would be the reset vector. 97 * 98 * loc: location to jump to for soft reset 99 */ 100 .align 5 101ENTRY(cpu_feroceon_reset) 102 mov ip, #0 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB 105#ifdef CONFIG_MMU 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107#endif 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 109 bic ip, ip, #0x000f @ ............wcam 110 bic ip, ip, #0x1100 @ ...i...s........ 111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 112 mov pc, r0 113 114/* 115 * cpu_feroceon_do_idle() 116 * 117 * Called with IRQs disabled 118 */ 119 .align 5 120ENTRY(cpu_feroceon_do_idle) 121 mov r0, #0 122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 124 mov pc, lr 125 126/* 127 * flush_user_cache_all() 128 * 129 * Clean and invalidate all cache entries in a particular 130 * address space. 131 */ 132 .align 5 133ENTRY(feroceon_flush_user_cache_all) 134 /* FALLTHROUGH */ 135 136/* 137 * flush_kern_cache_all() 138 * 139 * Clean and invalidate the entire cache. 140 */ 141ENTRY(feroceon_flush_kern_cache_all) 142 mov r2, #VM_EXEC 143 144__flush_whole_cache: 145 ldr r1, __cache_params 146 ldmia r1, {r1, r3} 1471: orr ip, r1, r3 1482: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 149 subs ip, ip, #(1 << 30) @ next way 150 bcs 2b 151 subs r1, r1, #(1 << 5) @ next set 152 bcs 1b 153 154 tst r2, #VM_EXEC 155 mov ip, #0 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 mov pc, lr 159 160/* 161 * flush_user_cache_range(start, end, flags) 162 * 163 * Clean and invalidate a range of cache entries in the 164 * specified address range. 165 * 166 * - start - start address (inclusive) 167 * - end - end address (exclusive) 168 * - flags - vm_flags describing address space 169 */ 170 .align 5 171ENTRY(feroceon_flush_user_cache_range) 172 sub r3, r1, r0 @ calculate total size 173 cmp r3, #CACHE_DLIMIT 174 bgt __flush_whole_cache 1751: tst r2, #VM_EXEC 176 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 178 add r0, r0, #CACHE_DLINESIZE 179 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 180 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 181 add r0, r0, #CACHE_DLINESIZE 182 cmp r0, r1 183 blo 1b 184 tst r2, #VM_EXEC 185 mov ip, #0 186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 187 mov pc, lr 188 189/* 190 * coherent_kern_range(start, end) 191 * 192 * Ensure coherency between the Icache and the Dcache in the 193 * region described by start, end. If you have non-snooping 194 * Harvard caches, you need to implement this function. 195 * 196 * - start - virtual start address 197 * - end - virtual end address 198 */ 199 .align 5 200ENTRY(feroceon_coherent_kern_range) 201 /* FALLTHROUGH */ 202 203/* 204 * coherent_user_range(start, end) 205 * 206 * Ensure coherency between the Icache and the Dcache in the 207 * region described by start, end. If you have non-snooping 208 * Harvard caches, you need to implement this function. 209 * 210 * - start - virtual start address 211 * - end - virtual end address 212 */ 213ENTRY(feroceon_coherent_user_range) 214 bic r0, r0, #CACHE_DLINESIZE - 1 2151: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 217 add r0, r0, #CACHE_DLINESIZE 218 cmp r0, r1 219 blo 1b 220 mcr p15, 0, r0, c7, c10, 4 @ drain WB 221 mov pc, lr 222 223/* 224 * flush_kern_dcache_area(void *addr, size_t size) 225 * 226 * Ensure no D cache aliasing occurs, either with itself or 227 * the I cache 228 * 229 * - addr - kernel address 230 * - size - region size 231 */ 232 .align 5 233ENTRY(feroceon_flush_kern_dcache_area) 234 add r1, r0, r1 2351: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 236 add r0, r0, #CACHE_DLINESIZE 237 cmp r0, r1 238 blo 1b 239 mov r0, #0 240 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 241 mcr p15, 0, r0, c7, c10, 4 @ drain WB 242 mov pc, lr 243 244 .align 5 245ENTRY(feroceon_range_flush_kern_dcache_area) 246 mrs r2, cpsr 247 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive 248 orr r3, r2, #PSR_I_BIT 249 msr cpsr_c, r3 @ disable interrupts 250 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 251 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 252 msr cpsr_c, r2 @ restore interrupts 253 mov r0, #0 254 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 255 mcr p15, 0, r0, c7, c10, 4 @ drain WB 256 mov pc, lr 257 258/* 259 * dma_inv_range(start, end) 260 * 261 * Invalidate (discard) the specified virtual address range. 262 * May not write back any entries. If 'start' or 'end' 263 * are not cache line aligned, those lines must be written 264 * back. 265 * 266 * - start - virtual start address 267 * - end - virtual end address 268 * 269 * (same as v4wb) 270 */ 271 .align 5 272feroceon_dma_inv_range: 273 tst r0, #CACHE_DLINESIZE - 1 274 bic r0, r0, #CACHE_DLINESIZE - 1 275 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 276 tst r1, #CACHE_DLINESIZE - 1 277 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2781: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 279 add r0, r0, #CACHE_DLINESIZE 280 cmp r0, r1 281 blo 1b 282 mcr p15, 0, r0, c7, c10, 4 @ drain WB 283 mov pc, lr 284 285 .align 5 286feroceon_range_dma_inv_range: 287 mrs r2, cpsr 288 tst r0, #CACHE_DLINESIZE - 1 289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 290 tst r1, #CACHE_DLINESIZE - 1 291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 292 cmp r1, r0 293 subne r1, r1, #1 @ top address is inclusive 294 orr r3, r2, #PSR_I_BIT 295 msr cpsr_c, r3 @ disable interrupts 296 mcr p15, 5, r0, c15, c14, 0 @ D inv range start 297 mcr p15, 5, r1, c15, c14, 1 @ D inv range top 298 msr cpsr_c, r2 @ restore interrupts 299 mov pc, lr 300 301/* 302 * dma_clean_range(start, end) 303 * 304 * Clean the specified virtual address range. 305 * 306 * - start - virtual start address 307 * - end - virtual end address 308 * 309 * (same as v4wb) 310 */ 311 .align 5 312feroceon_dma_clean_range: 313 bic r0, r0, #CACHE_DLINESIZE - 1 3141: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 315 add r0, r0, #CACHE_DLINESIZE 316 cmp r0, r1 317 blo 1b 318 mcr p15, 0, r0, c7, c10, 4 @ drain WB 319 mov pc, lr 320 321 .align 5 322feroceon_range_dma_clean_range: 323 mrs r2, cpsr 324 cmp r1, r0 325 subne r1, r1, #1 @ top address is inclusive 326 orr r3, r2, #PSR_I_BIT 327 msr cpsr_c, r3 @ disable interrupts 328 mcr p15, 5, r0, c15, c13, 0 @ D clean range start 329 mcr p15, 5, r1, c15, c13, 1 @ D clean range top 330 msr cpsr_c, r2 @ restore interrupts 331 mcr p15, 0, r0, c7, c10, 4 @ drain WB 332 mov pc, lr 333 334/* 335 * dma_flush_range(start, end) 336 * 337 * Clean and invalidate the specified virtual address range. 338 * 339 * - start - virtual start address 340 * - end - virtual end address 341 */ 342 .align 5 343ENTRY(feroceon_dma_flush_range) 344 bic r0, r0, #CACHE_DLINESIZE - 1 3451: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 346 add r0, r0, #CACHE_DLINESIZE 347 cmp r0, r1 348 blo 1b 349 mcr p15, 0, r0, c7, c10, 4 @ drain WB 350 mov pc, lr 351 352 .align 5 353ENTRY(feroceon_range_dma_flush_range) 354 mrs r2, cpsr 355 cmp r1, r0 356 subne r1, r1, #1 @ top address is inclusive 357 orr r3, r2, #PSR_I_BIT 358 msr cpsr_c, r3 @ disable interrupts 359 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 360 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 361 msr cpsr_c, r2 @ restore interrupts 362 mcr p15, 0, r0, c7, c10, 4 @ drain WB 363 mov pc, lr 364 365/* 366 * dma_map_area(start, size, dir) 367 * - start - kernel virtual start address 368 * - size - size of region 369 * - dir - DMA direction 370 */ 371ENTRY(feroceon_dma_map_area) 372 add r1, r1, r0 373 cmp r2, #DMA_TO_DEVICE 374 beq feroceon_dma_clean_range 375 bcs feroceon_dma_inv_range 376 b feroceon_dma_flush_range 377ENDPROC(feroceon_dma_map_area) 378 379/* 380 * dma_map_area(start, size, dir) 381 * - start - kernel virtual start address 382 * - size - size of region 383 * - dir - DMA direction 384 */ 385ENTRY(feroceon_range_dma_map_area) 386 add r1, r1, r0 387 cmp r2, #DMA_TO_DEVICE 388 beq feroceon_range_dma_clean_range 389 bcs feroceon_range_dma_inv_range 390 b feroceon_range_dma_flush_range 391ENDPROC(feroceon_range_dma_map_area) 392 393/* 394 * dma_unmap_area(start, size, dir) 395 * - start - kernel virtual start address 396 * - size - size of region 397 * - dir - DMA direction 398 */ 399ENTRY(feroceon_dma_unmap_area) 400 mov pc, lr 401ENDPROC(feroceon_dma_unmap_area) 402 403ENTRY(feroceon_cache_fns) 404 .long feroceon_flush_kern_cache_all 405 .long feroceon_flush_user_cache_all 406 .long feroceon_flush_user_cache_range 407 .long feroceon_coherent_kern_range 408 .long feroceon_coherent_user_range 409 .long feroceon_flush_kern_dcache_area 410 .long feroceon_dma_map_area 411 .long feroceon_dma_unmap_area 412 .long feroceon_dma_flush_range 413 414ENTRY(feroceon_range_cache_fns) 415 .long feroceon_flush_kern_cache_all 416 .long feroceon_flush_user_cache_all 417 .long feroceon_flush_user_cache_range 418 .long feroceon_coherent_kern_range 419 .long feroceon_coherent_user_range 420 .long feroceon_range_flush_kern_dcache_area 421 .long feroceon_range_dma_map_area 422 .long feroceon_dma_unmap_area 423 .long feroceon_range_dma_flush_range 424 425 .align 5 426ENTRY(cpu_feroceon_dcache_clean_area) 427#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 428 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 429 mov r2, r0 430 mov r3, r1 431#endif 4321: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 433 add r0, r0, #CACHE_DLINESIZE 434 subs r1, r1, #CACHE_DLINESIZE 435 bhi 1b 436#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 437 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 4381: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry 439 add r2, r2, #CACHE_DLINESIZE 440 subs r3, r3, #CACHE_DLINESIZE 441 bhi 1b 442#endif 443 mcr p15, 0, r0, c7, c10, 4 @ drain WB 444 mov pc, lr 445 446/* =============================== PageTable ============================== */ 447 448/* 449 * cpu_feroceon_switch_mm(pgd) 450 * 451 * Set the translation base pointer to be as described by pgd. 452 * 453 * pgd: new page tables 454 */ 455 .align 5 456ENTRY(cpu_feroceon_switch_mm) 457#ifdef CONFIG_MMU 458 /* 459 * Note: we wish to call __flush_whole_cache but we need to preserve 460 * lr to do so. The only way without touching main memory is to 461 * use r2 which is normally used to test the VM_EXEC flag, and 462 * compensate locally for the skipped ops if it is not set. 463 */ 464 mov r2, lr @ abuse r2 to preserve lr 465 bl __flush_whole_cache 466 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already 467 tst r2, #VM_EXEC 468 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache 469 mcreq p15, 0, ip, c7, c10, 4 @ drain WB 470 471 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 472 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 473 mov pc, r2 474#else 475 mov pc, lr 476#endif 477 478/* 479 * cpu_feroceon_set_pte_ext(ptep, pte, ext) 480 * 481 * Set a PTE and flush it out 482 */ 483 .align 5 484ENTRY(cpu_feroceon_set_pte_ext) 485#ifdef CONFIG_MMU 486 armv3_set_pte_ext wc_disable=0 487 mov r0, r0 488 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 489#if defined(CONFIG_CACHE_FEROCEON_L2) && \ 490 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) 491 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry 492#endif 493 mcr p15, 0, r0, c7, c10, 4 @ drain WB 494#endif 495 mov pc, lr 496 497 __CPUINIT 498 499 .type __feroceon_setup, #function 500__feroceon_setup: 501 mov r0, #0 502 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 503 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 504#ifdef CONFIG_MMU 505 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 506#endif 507 508 adr r5, feroceon_crval 509 ldmia r5, {r5, r6} 510 mrc p15, 0, r0, c1, c0 @ get control register v4 511 bic r0, r0, r5 512 orr r0, r0, r6 513 mov pc, lr 514 .size __feroceon_setup, . - __feroceon_setup 515 516 /* 517 * B 518 * R P 519 * .RVI UFRS BLDP WCAM 520 * .011 .001 ..11 0101 521 * 522 */ 523 .type feroceon_crval, #object 524feroceon_crval: 525 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134 526 527 __INITDATA 528 529/* 530 * Purpose : Function pointers used to access above functions - all calls 531 * come through these 532 */ 533 .type feroceon_processor_functions, #object 534feroceon_processor_functions: 535 .word v5t_early_abort 536 .word legacy_pabort 537 .word cpu_feroceon_proc_init 538 .word cpu_feroceon_proc_fin 539 .word cpu_feroceon_reset 540 .word cpu_feroceon_do_idle 541 .word cpu_feroceon_dcache_clean_area 542 .word cpu_feroceon_switch_mm 543 .word cpu_feroceon_set_pte_ext 544 .size feroceon_processor_functions, . - feroceon_processor_functions 545 546 .section ".rodata" 547 548 .type cpu_arch_name, #object 549cpu_arch_name: 550 .asciz "armv5te" 551 .size cpu_arch_name, . - cpu_arch_name 552 553 .type cpu_elf_name, #object 554cpu_elf_name: 555 .asciz "v5" 556 .size cpu_elf_name, . - cpu_elf_name 557 558 .type cpu_feroceon_name, #object 559cpu_feroceon_name: 560 .asciz "Feroceon" 561 .size cpu_feroceon_name, . - cpu_feroceon_name 562 563 .type cpu_88fr531_name, #object 564cpu_88fr531_name: 565 .asciz "Feroceon 88FR531-vd" 566 .size cpu_88fr531_name, . - cpu_88fr531_name 567 568 .type cpu_88fr571_name, #object 569cpu_88fr571_name: 570 .asciz "Feroceon 88FR571-vd" 571 .size cpu_88fr571_name, . - cpu_88fr571_name 572 573 .type cpu_88fr131_name, #object 574cpu_88fr131_name: 575 .asciz "Feroceon 88FR131" 576 .size cpu_88fr131_name, . - cpu_88fr131_name 577 578 .align 579 580 .section ".proc.info.init", #alloc, #execinstr 581 582#ifdef CONFIG_CPU_FEROCEON_OLD_ID 583 .type __feroceon_old_id_proc_info,#object 584__feroceon_old_id_proc_info: 585 .long 0x41009260 586 .long 0xff00fff0 587 .long PMD_TYPE_SECT | \ 588 PMD_SECT_BUFFERABLE | \ 589 PMD_SECT_CACHEABLE | \ 590 PMD_BIT4 | \ 591 PMD_SECT_AP_WRITE | \ 592 PMD_SECT_AP_READ 593 .long PMD_TYPE_SECT | \ 594 PMD_BIT4 | \ 595 PMD_SECT_AP_WRITE | \ 596 PMD_SECT_AP_READ 597 b __feroceon_setup 598 .long cpu_arch_name 599 .long cpu_elf_name 600 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 601 .long cpu_feroceon_name 602 .long feroceon_processor_functions 603 .long v4wbi_tlb_fns 604 .long feroceon_user_fns 605 .long feroceon_cache_fns 606 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info 607#endif 608 609 .type __88fr531_proc_info,#object 610__88fr531_proc_info: 611 .long 0x56055310 612 .long 0xfffffff0 613 .long PMD_TYPE_SECT | \ 614 PMD_SECT_BUFFERABLE | \ 615 PMD_SECT_CACHEABLE | \ 616 PMD_BIT4 | \ 617 PMD_SECT_AP_WRITE | \ 618 PMD_SECT_AP_READ 619 .long PMD_TYPE_SECT | \ 620 PMD_BIT4 | \ 621 PMD_SECT_AP_WRITE | \ 622 PMD_SECT_AP_READ 623 b __feroceon_setup 624 .long cpu_arch_name 625 .long cpu_elf_name 626 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 627 .long cpu_88fr531_name 628 .long feroceon_processor_functions 629 .long v4wbi_tlb_fns 630 .long feroceon_user_fns 631 .long feroceon_cache_fns 632 .size __88fr531_proc_info, . - __88fr531_proc_info 633 634 .type __88fr571_proc_info,#object 635__88fr571_proc_info: 636 .long 0x56155710 637 .long 0xfffffff0 638 .long PMD_TYPE_SECT | \ 639 PMD_SECT_BUFFERABLE | \ 640 PMD_SECT_CACHEABLE | \ 641 PMD_BIT4 | \ 642 PMD_SECT_AP_WRITE | \ 643 PMD_SECT_AP_READ 644 .long PMD_TYPE_SECT | \ 645 PMD_BIT4 | \ 646 PMD_SECT_AP_WRITE | \ 647 PMD_SECT_AP_READ 648 b __feroceon_setup 649 .long cpu_arch_name 650 .long cpu_elf_name 651 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 652 .long cpu_88fr571_name 653 .long feroceon_processor_functions 654 .long v4wbi_tlb_fns 655 .long feroceon_user_fns 656 .long feroceon_range_cache_fns 657 .size __88fr571_proc_info, . - __88fr571_proc_info 658 659 .type __88fr131_proc_info,#object 660__88fr131_proc_info: 661 .long 0x56251310 662 .long 0xfffffff0 663 .long PMD_TYPE_SECT | \ 664 PMD_SECT_BUFFERABLE | \ 665 PMD_SECT_CACHEABLE | \ 666 PMD_BIT4 | \ 667 PMD_SECT_AP_WRITE | \ 668 PMD_SECT_AP_READ 669 .long PMD_TYPE_SECT | \ 670 PMD_BIT4 | \ 671 PMD_SECT_AP_WRITE | \ 672 PMD_SECT_AP_READ 673 b __feroceon_setup 674 .long cpu_arch_name 675 .long cpu_elf_name 676 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 677 .long cpu_88fr131_name 678 .long feroceon_processor_functions 679 .long v4wbi_tlb_fns 680 .long feroceon_user_fns 681 .long feroceon_range_cache_fns 682 .size __88fr131_proc_info, . - __88fr131_proc_info 683